1#
2# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7override PROGRAMMABLE_RESET_ADDRESS	:= 1
8override USE_COHERENT_MEM		:= 1
9override SEPARATE_CODE_AND_RODATA	:= 1
10override ENABLE_SVE_FOR_NS		:= 0
11# Enable workarounds for selected Cortex-A53 erratas.
12ERRATA_A53_855873		:= 1
13
14ifeq (${RESET_TO_BL31}, 1)
15override RESET_TO_BL31          := 1
16override TRUSTED_BOARD_BOOT     := 0
17SQ_USE_SCMI_DRIVER              ?= 0
18else
19override RESET_TO_BL31          := 0
20override RESET_TO_BL2		:= 1
21SQ_USE_SCMI_DRIVER              := 1
22BL2_CPPFLAGS                    += -DPLAT_XLAT_TABLES_DYNAMIC
23endif
24
25# Libraries
26include lib/xlat_tables_v2/xlat_tables.mk
27
28PLAT_PATH		:=	plat/socionext/synquacer
29PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include		\
30				-I$(PLAT_PATH)/drivers/scpi	\
31				-I$(PLAT_PATH)/drivers/mhu \
32				-Idrivers/arm/css/scmi \
33				-Idrivers/arm/css/scmi/vendor
34
35PLAT_BL_COMMON_SOURCES	+=	$(PLAT_PATH)/sq_helpers.S		\
36				drivers/arm/pl011/aarch64/pl011_console.S \
37				drivers/delay_timer/delay_timer.c	\
38				drivers/delay_timer/generic_delay_timer.c \
39				lib/cpus/aarch64/cortex_a53.S		\
40				$(PLAT_PATH)/sq_xlat_setup.c	\
41				${XLAT_TABLES_LIB_SRCS}
42
43# Include GICv3 driver files
44include drivers/arm/gic/v3/gicv3.mk
45
46ifneq (${RESET_TO_BL31}, 1)
47BL2_SOURCES		+=	common/desc_image_load.c		\
48				drivers/io/io_fip.c			\
49				drivers/io/io_memmap.c			\
50				drivers/io/io_storage.c			\
51				$(PLAT_PATH)/sq_bl2_setup.c		\
52				$(PLAT_PATH)/sq_image_desc.c	\
53				$(PLAT_PATH)/sq_io_storage.c
54
55ifeq (${TRUSTED_BOARD_BOOT},1)
56include drivers/auth/mbedtls/mbedtls_crypto.mk
57include drivers/auth/mbedtls/mbedtls_x509.mk
58BL2_SOURCES		+=	drivers/auth/auth_mod.c			\
59				drivers/auth/crypto_mod.c		\
60				drivers/auth/img_parser_mod.c		\
61				drivers/auth/tbbr/tbbr_cot_common.c	\
62				drivers/auth/tbbr/tbbr_cot_bl2.c	\
63				plat/common/tbbr/plat_tbbr.c		\
64				$(PLAT_PATH)/sq_rotpk.S		\
65				$(PLAT_PATH)/sq_tbbr.c
66
67ROT_KEY			= $(BUILD_PLAT)/rot_key.pem
68ROTPK_HASH		= $(BUILD_PLAT)/rotpk_sha256.bin
69
70$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
71$(BUILD_PLAT)/bl2/sq_rotpk.o: $(ROTPK_HASH)
72
73certificates: $(ROT_KEY)
74$(ROT_KEY): | $(BUILD_PLAT)
75	@echo "  OPENSSL $@"
76	$(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
77
78$(ROTPK_HASH): $(ROT_KEY)
79	@echo "  OPENSSL $@"
80	$(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
81	${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
82
83endif	# TRUSTED_BOARD_BOOT
84endif
85
86BL31_SOURCES		+=	drivers/arm/ccn/ccn.c			\
87				${GICV3_SOURCES}			\
88				plat/common/plat_gicv3.c		\
89				plat/common/plat_psci_common.c		\
90				$(PLAT_PATH)/sq_bl31_setup.c		\
91				$(PLAT_PATH)/sq_ccn.c			\
92				$(PLAT_PATH)/sq_topology.c		\
93				$(PLAT_PATH)/sq_psci.c			\
94				$(PLAT_PATH)/sq_gicv3.c			\
95				$(PLAT_PATH)/drivers/scp/sq_scp.c
96
97ifeq (${SQ_USE_SCMI_DRIVER},0)
98BL31_SOURCES		+=	$(PLAT_PATH)/drivers/scpi/sq_scpi.c	\
99				$(PLAT_PATH)/drivers/mhu/sq_mhu.c
100else
101BL31_SOURCES		+=	$(PLAT_PATH)/drivers/scp/sq_scmi.c		\
102				drivers/arm/css/scmi/scmi_common.c		\
103				drivers/arm/css/scmi/scmi_pwr_dmn_proto.c	\
104				drivers/arm/css/scmi/scmi_sys_pwr_proto.c	\
105				drivers/arm/css/scmi/vendor/scmi_sq.c	\
106				drivers/arm/css/mhu/css_mhu_doorbell.c
107endif
108
109ifeq (${SPM_MM},1)
110$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
111
112BL31_SOURCES		+=	$(PLAT_PATH)/sq_spm.c
113endif
114
115ifeq (${SQ_USE_SCMI_DRIVER},1)
116$(eval $(call add_define,SQ_USE_SCMI_DRIVER))
117endif
118