1/*
2 * Copyright (c) 2021-2023, Stephan Gerhold <[email protected]>
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10
11#include <msm8916_mmap.h>
12
13#if PLATFORM_CORE_COUNT > 1
14#define APCS_TCM_START_ADDR	0x10
15#else
16#define APCS_TCM_START_ADDR	0x34
17#endif
18#define APCS_TCM_REDIRECT_EN_0	BIT_32(0)
19
20	.globl	plat_crash_console_init
21	.globl	plat_crash_console_putc
22	.globl	plat_crash_console_flush
23	.globl	plat_panic_handler
24	.globl	plat_my_core_pos
25	.globl	plat_get_my_entrypoint
26	.globl	plat_reset_handler
27	.globl	platform_mem_init
28	.globl	msm8916_entry_point
29
30	/* -------------------------------------------------
31	 * int plat_crash_console_init(void)
32	 * Initialize the crash console.
33	 * Out: x0 - 1 on success, 0 on error
34	 * Clobber list : x0 - x4
35	 * -------------------------------------------------
36	 */
37func plat_crash_console_init
38	mov_imm	x1, BLSP_UART_BASE
39	mov	x0, #1
40	b	console_uartdm_core_init
41endfunc plat_crash_console_init
42
43	/* -------------------------------------------------
44	 * int plat_crash_console_putc(int c)
45	 * Print a character on the crash console.
46	 * In : w0 - character to be printed
47	 * Out: w0 - printed character on success
48	 * Clobber list : x1, x2
49	 * -------------------------------------------------
50	 */
51func plat_crash_console_putc
52	mov_imm	x1, BLSP_UART_BASE
53	b	console_uartdm_core_putc
54endfunc plat_crash_console_putc
55
56	/* -------------------------------------------------
57	 * void plat_crash_console_flush(void)
58	 * Force a write of all buffered data that has not
59	 * been output.
60	 * Clobber list : x1, x2
61	 * -------------------------------------------------
62	 */
63func plat_crash_console_flush
64	mov_imm	x1, BLSP_UART_BASE
65	b	console_uartdm_core_flush
66endfunc plat_crash_console_flush
67
68	/* -------------------------------------------------
69	 * void plat_panic_handler(void) __dead
70	 * Called when an unrecoverable error occurs.
71	 * -------------------------------------------------
72	 */
73func plat_panic_handler
74	/* Try to shutdown/reset */
75	mov_imm	x0, MPM_PS_HOLD
76	str	wzr, [x0]
771:	b	1b
78endfunc plat_panic_handler
79
80	/* -------------------------------------------------
81	 * unsigned int plat_my_core_pos(void)
82	 * Out: x0 - index of the calling CPU
83	 * -------------------------------------------------
84	 */
85func plat_my_core_pos
86	.if PLATFORM_CORE_COUNT > 1
87		mrs	x1, mpidr_el1
88		and	x0, x1, #MPIDR_CPU_MASK
89		.if PLATFORM_CLUSTER_COUNT > 1
90			and	x1, x1, #MPIDR_CLUSTER_MASK
91			orr	x0, x0, x1, LSR #(MPIDR_AFFINITY_BITS - \
92						  PLATFORM_CPU_PER_CLUSTER_SHIFT)
93		.endif
94	.else
95		/* There is just a single core so always 0 */
96		mov	x0, #0
97	.endif
98	ret
99endfunc plat_my_core_pos
100
101	/* -------------------------------------------------
102	 * uintptr_t plat_get_my_entrypoint(void)
103	 * Distinguish cold and warm boot and return warm boot
104	 * entry address if available.
105	 * Out: x0 - warm boot entry point or 0 on cold boot
106	 * -------------------------------------------------
107	 */
108func plat_get_my_entrypoint
109	ldr	x0, msm8916_entry_point
110	cbz	x0, 1f
111	ret
1121:
113	/*
114	 * Cold boot: Disable TCM redirect to L2 cache as early as
115	 * possible to avoid crashes when making use of the cache.
116	 */
117	mov_imm	x1, APCS_CFG(0)
118	ldr	w2, [x1, #APCS_TCM_START_ADDR]
119	and	w2, w2, #~APCS_TCM_REDIRECT_EN_0
120	str	w2, [x1, #APCS_TCM_START_ADDR]
121
122	/*
123	 * After reset the CPU always starts executing at the fixed reset
124	 * address (0x0), which does not match the link address of BL31.
125	 * The "boot remapper" redirects all memory accesses to the real
126	 * physical address in DRAM.
127	 *
128	 * For warm boots, this is already handled by loading the real
129	 * entry point address above.
130	 *
131	 * For cold boots, check if the CPU is using the boot remapper,
132	 * i.e. if bl31_entrypoint appears to be at the reset address (0x0).
133	 */
134	adr	x1, bl31_entrypoint
135	cbnz	x1, 2f
136
137	/*
138	 * Add the real BL31_BASE offset to the return address in the link
139	 * register so the CPU will continue at the real address after return.
140	 */
141	mov_imm	x1, BL31_BASE
142	add	lr, lr, x1
1432:
144	ret
145endfunc plat_get_my_entrypoint
146
147	/* -------------------------------------------------
148	 * void platform_mem_init(void)
149	 * Performs additional memory initialization early
150	 * in the boot process.
151	 * -------------------------------------------------
152	 */
153func platform_mem_init
154	/* Nothing to do here, all memory is already initialized */
155	ret
156endfunc platform_mem_init
157
158	.data
159	.align	3
160
161	/* -------------------------------------------------
162	 * Warm boot entry point for CPU. Set by PSCI code.
163	 * -------------------------------------------------
164	 */
165msm8916_entry_point:
166	.quad	0
167