1#
2# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/libfdt/libfdt.mk
8include common/fdt_wrappers.mk
9
10PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/		\
11				-I${PLAT_QEMU_COMMON_PATH}/include	\
12				-I${PLAT_QEMU_PATH}/include		\
13				-Iinclude/common/tbbr
14
15ifeq (${ARCH},aarch32)
16QEMU_CPU_LIBS		:=	lib/cpus/${ARCH}/cortex_a15.S
17else
18QEMU_CPU_LIBS		:=	lib/cpus/aarch64/aem_generic.S		\
19				lib/cpus/aarch64/cortex_a53.S		\
20				lib/cpus/aarch64/cortex_a55.S		\
21				lib/cpus/aarch64/cortex_a57.S		\
22				lib/cpus/aarch64/cortex_a72.S		\
23				lib/cpus/aarch64/cortex_a76.S		\
24				lib/cpus/aarch64/cortex_a710.S		\
25				lib/cpus/aarch64/neoverse_n_common.S	\
26				lib/cpus/aarch64/neoverse_n1.S		\
27				lib/cpus/aarch64/neoverse_v1.S		\
28				lib/cpus/aarch64/neoverse_n2.S		\
29				lib/cpus/aarch64/qemu_max.S
30
31PLAT_INCLUDES		+=	-Iinclude/plat/arm/common/${ARCH}
32endif
33
34PLAT_BL_COMMON_SOURCES	:=	${PLAT_QEMU_COMMON_PATH}/qemu_common.c		\
35				${PLAT_QEMU_COMMON_PATH}/qemu_console.c		\
36				drivers/arm/pl011/${ARCH}/pl011_console.S
37
38include lib/xlat_tables_v2/xlat_tables.mk
39PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
40
41ifneq ($(ENABLE_STACK_PROTECTOR), 0)
42	PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c
43endif
44
45BL1_SOURCES		+=	drivers/io/io_semihosting.c		\
46				drivers/io/io_storage.c			\
47				drivers/io/io_fip.c			\
48				drivers/io/io_memmap.c			\
49				lib/semihosting/semihosting.c		\
50				lib/semihosting/${ARCH}/semihosting_call.S	\
51				${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c	\
52				${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S	\
53				${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c	\
54				${QEMU_CPU_LIBS}
55
56BL2_SOURCES		+=	drivers/io/io_semihosting.c		\
57				drivers/io/io_storage.c			\
58				drivers/io/io_fip.c			\
59				drivers/io/io_memmap.c			\
60				lib/semihosting/semihosting.c		\
61				lib/semihosting/${ARCH}/semihosting_call.S		\
62				${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c		\
63				${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S		\
64				${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c		\
65				${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c	\
66				${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c		\
67				common/desc_image_load.c		\
68				common/fdt_fixup.c
69
70BL31_SOURCES		+=	${QEMU_CPU_LIBS}				\
71				lib/semihosting/semihosting.c			\
72				lib/semihosting/${ARCH}/semihosting_call.S	\
73				plat/common/plat_psci_common.c			\
74				${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S	\
75				${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c	\
76				common/fdt_fixup.c				\
77				${QEMU_GIC_SOURCES}
78
79# CPU flag enablement
80ifeq (${ARCH},aarch64)
81
82# Cpu core architecture level:
83# v8.0: a53, a57, a72
84# v8.2: a55, a76, n1
85# v8.4: v1
86# v9.0: a710, n2
87#
88#
89# We go v8.0 by default and will enable all features we want
90
91ARM_ARCH_MAJOR		?=	8
92ARM_ARCH_MINOR		?=	0
93
94# 8.0
95ENABLE_FEAT_CSV2_2	:=	2
96
97# 8.1
98ENABLE_FEAT_PAN		:=	2
99ENABLE_FEAT_VHE		:=	2
100
101# 8.2
102# TF-A currently does not permit dynamic detection of FEAT_RAS
103# so this is the only safe setting
104ENABLE_FEAT_RAS		:=	0
105
106# 8.4
107ENABLE_FEAT_SEL2	:=	2
108ENABLE_FEAT_DIT		:=	2
109ENABLE_TRF_FOR_NS	:=	2
110
111# 8.5
112ENABLE_FEAT_RNG		:=	2
113# TF-A currently does not do dynamic detection of FEAT_SB.
114# Compiler puts SB instruction when it is enabled.
115ENABLE_FEAT_SB		:=	0
116
117# 8.6
118ENABLE_FEAT_ECV		:=	2
119ENABLE_FEAT_FGT		:=	2
120
121# 8.7
122ENABLE_FEAT_HCX		:=	2
123
124ENABLE_SVE := 1
125# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks)
126ifeq (${SPM_MM},1)
127	ENABLE_SVE := 0
128endif
129# Same for CTX_INCLUDE_FPREGS
130ifeq (${CTX_INCLUDE_FPREGS},1)
131	ENABLE_SVE := 0
132endif
133ifeq (${ENABLE_SVE},0)
134	ENABLE_SVE_FOR_NS	:= 0
135	ENABLE_SME_FOR_NS	:= 0
136else
137	ENABLE_SVE_FOR_NS	:= 2
138	ENABLE_SVE_FOR_SWD	:= 1
139	ENABLE_SME_FOR_NS	:= 2
140endif
141
142ifeq (${ENABLE_RME},1)
143BL31_SOURCES			+= plat/qemu/common/qemu_plat_attest_token.c \
144				   plat/qemu/common/qemu_realm_attest_key.c
145endif
146
147# Treating this as a memory-constrained port for now
148USE_COHERENT_MEM	:=	0
149
150# This can be overridden depending on CPU(s) used in the QEMU image
151HW_ASSISTED_COHERENCY	:=	1
152
153CTX_INCLUDE_AARCH32_REGS := 0
154ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
155$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
156endif
157
158# Pointer Authentication sources
159ifeq (${ENABLE_PAUTH}, 1)
160PLAT_BL_COMMON_SOURCES	+=	plat/arm/common/aarch64/arm_pauth.c
161CTX_INCLUDE_PAUTH_REGS	:=	1
162endif
163
164endif
165