1/* 2 * Copyright 2018-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8#include <arch.h> 9#include <asm_macros.S> 10 11#include <platform_def.h> 12 13 .globl plat_secondary_cold_boot_setup 14 .globl plat_is_my_cpu_primary 15 .globl plat_reset_handler 16 .globl platform_mem_init 17 18func platform_mem1_init 19 ret 20endfunc platform_mem1_init 21 22func platform_mem_init 23 ret 24endfunc platform_mem_init 25 26func l2_mem_init 27 /* Initialize the L2 RAM latency */ 28 mrs x1, S3_1_c11_c0_2 29 mov x0, #0x1C7 30 /* Clear L2 Tag RAM latency and L2 Data RAM latency */ 31 bic x1, x1, x0 32 /* Set L2 data ram latency bits [2:0] */ 33 orr x1, x1, #0x2 34 /* set L2 tag ram latency bits [8:6] */ 35 orr x1, x1, #0x80 36 msr S3_1_c11_c0_2, x1 37 isb 38 ret 39endfunc l2_mem_init 40 41func apply_platform_errata 42 ret 43endfunc apply_platform_errata 44 45func plat_reset_handler 46 mov x29, x30 47#if (defined(IMAGE_BL2) && RESET_TO_BL2) 48 bl l2_mem_init 49#endif 50 bl apply_platform_errata 51 52#if defined(IMAGE_BL31) 53 ldr x0, =POLICY_SMMU_PAGESZ_64K 54 cbz x0, 1f 55 /* Set the SMMU page size in the SACR register */ 56 bl _set_smmu_pagesz_64 57#endif 581: 59 /* 60 * May be cntfrq_el0 needs to be assigned 61 * the value COUNTER_FREQUENCY 62 */ 63 mov x30, x29 64 ret 65endfunc plat_reset_handler 66 67/* 68 * void plat_secondary_cold_boot_setup (void); 69 * 70 * This function performs any platform specific actions 71 * needed for a secondary cpu after a cold reset e.g 72 * mark the cpu's presence, mechanism to place it in a 73 * holding pen etc. 74 */ 75func plat_secondary_cold_boot_setup 76 /* ls1046a does not do cold boot for secondary CPU */ 77cb_panic: 78 b cb_panic 79endfunc plat_secondary_cold_boot_setup 80 81/* 82 * unsigned int plat_is_my_cpu_primary (void); 83 * 84 * Find out whether the current cpu is the primary cpu. 85 */ 86func plat_is_my_cpu_primary 87 mrs x0, mpidr_el1 88 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 89 cmp x0, 0x0 90 cset w0, eq 91 ret 92endfunc plat_is_my_cpu_primary 93