1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <common/debug.h> 10 #include <ddr.h> 11 #include <lib/utils.h> 12 13 #include <errata.h> 14 #include <platform_def.h> 15 16 #ifdef CONFIG_STATIC_DDR 17 const struct ddr_cfg_regs static_1600 = { 18 .cs[0].config = U(0x80040322), 19 .cs[0].bnds = U(0x7F), 20 .sdram_cfg[0] = U(0xC50C0000), 21 .sdram_cfg[1] = U(0x401100), 22 .timing_cfg[0] = U(0x91550018), 23 .timing_cfg[1] = U(0xBBB48C42), 24 .timing_cfg[2] = U(0x48C111), 25 .timing_cfg[3] = U(0x10C1000), 26 .timing_cfg[4] = U(0x2), 27 .timing_cfg[5] = U(0x3401400), 28 .timing_cfg[7] = U(0x13300000), 29 .timing_cfg[8] = U(0x2115600), 30 .sdram_mode[0] = U(0x3010210), 31 .sdram_mode[9] = U(0x4000000), 32 .sdram_mode[8] = U(0x500), 33 .sdram_mode[2] = U(0x10210), 34 .sdram_mode[10] = U(0x400), 35 .sdram_mode[11] = U(0x4000000), 36 .sdram_mode[4] = U(0x10210), 37 .sdram_mode[12] = U(0x400), 38 .sdram_mode[13] = U(0x4000000), 39 .sdram_mode[6] = U(0x10210), 40 .sdram_mode[14] = U(0x400), 41 .sdram_mode[15] = U(0x4000000), 42 .interval = U(0x18600618), 43 .zq_cntl = U(0x8A090705), 44 .clk_cntl = U(0x3000000), 45 .cdr[0] = U(0x80040000), 46 .cdr[1] = U(0xA181), 47 .wrlvl_cntl[0] = U(0x8675F607), 48 .wrlvl_cntl[1] = U(0x7090807, 49 .wrlvl_cntl[2] = U(0x7070707), 50 .debug[28] = U(0x00700046), 51 }; 52 53 uint64_t board_static_ddr(struct ddr_info *priv) 54 { 55 memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600)); 56 57 return ULL(0x80000000); 58 } 59 60 #else 61 static const struct rc_timing rcz[] = { 62 {1600, 12, 7}, 63 {} 64 }; 65 66 static const struct board_timing ram[] = { 67 {0x1f, rcz, 0x00020100, 0}, 68 }; 69 70 int ddr_board_options(struct ddr_info *priv) 71 { 72 int ret; 73 struct memctl_opt *popts = &priv->opt; 74 75 ret = cal_board_params(priv, ram, ARRAY_SIZE(ram)); 76 if (ret) 77 return ret; 78 79 popts->cpo_sample = U(0x46); 80 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | 81 DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 82 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 83 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ 84 85 return 0; 86 } 87 88 /* DDR model number: MT40A1G8SA-062E:R */ 89 struct dimm_params ddr_raw_timing = { 90 .n_ranks = U(1), 91 .rank_density = ULL(2147483648), 92 .capacity = ULL(2147483648), 93 .primary_sdram_width = U(32), 94 .ec_sdram_width = U(4), 95 .rdimm = U(0), 96 .mirrored_dimm = U(0), 97 .n_row_addr = U(16), 98 .n_col_addr = U(10), 99 .bank_group_bits = U(2), 100 .edc_config = U(2), 101 .burst_lengths_bitmask = U(0x0c), 102 .tckmin_x_ps = 625, 103 .tckmax_ps = 2200, 104 .caslat_x = U(0x0001FFE00), 105 .taa_ps = 13500, 106 .trcd_ps = 13500, 107 .trp_ps = 13500, 108 .tras_ps = 32000, 109 .trc_ps = 45500, 110 .twr_ps = 15000, 111 .trfc1_ps = 350000, 112 .trfc2_ps = 260000, 113 .trfc4_ps = 160000, 114 .tfaw_ps = 21000, 115 .trrds_ps = 3000, 116 .trrdl_ps = 4900, 117 .tccdl_ps = 5000, 118 .refresh_rate_ps = U(7800000), 119 .rc = U(0x1f), 120 }; 121 122 int ddr_get_ddr_params(struct dimm_params *pdimm, 123 struct ddr_conf *conf) 124 { 125 static const char dimm_model[] = "Fixed DDR on board"; 126 127 conf->dimm_in_use[0] = 1; 128 memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params)); 129 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 130 131 return 1; 132 } 133 #endif 134 135 int64_t init_ddr(void) 136 { 137 struct ddr_info info; 138 struct sysinfo sys; 139 int64_t dram_size; 140 141 zeromem(&sys, sizeof(sys)); 142 get_clocks(&sys); 143 debug("platform clock %lu\n", sys.freq_platform); 144 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); 145 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); 146 147 zeromem(&info, sizeof(struct ddr_info)); 148 info.num_ctlrs = 1; 149 info.dimm_on_ctlr = 1; 150 info.clk = get_ddr_freq(&sys, 0); 151 info.ddr[0] = (void *)NXP_DDR_ADDR; 152 153 dram_size = dram_init(&info); 154 155 if (dram_size < 0) { 156 ERROR("DDR init failed\n"); 157 } 158 159 #ifdef ERRATA_SOC_A008850 160 erratum_a008850_post(); 161 #endif 162 return dram_size; 163 } 164