1#
2# Copyright 2018-2021 NXP
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6#
7#------------------------------------------------------------------------------
8#
9# This file contains the basic architecture definitions that drive the build
10#
11# -----------------------------------------------------------------------------
12
13CORE_TYPE	:=	a72
14
15CACHE_LINE	:=	6
16
17# Set to GIC400 or GIC500
18GIC		:=	GIC500
19
20# Set to CCI400 or CCN504 or CCN508
21INTERCONNECT	:=	CCI400
22
23# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
24CHASSIS		:=	3_2
25
26# TZC used is TZC380 or TZC400
27TZC_ID		:=	TZC400
28
29# CONSOLE is NS16550 or PL011
30CONSOLE		:=	NS16550
31
32# DDR PHY generation to be used
33PLAT_DDR_PHY	:=	PHY_GEN1
34
35PHYS_SYS	:=	64
36
37# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
38# Input to CST create_hdr_esbc tool
39CSF_HDR_SZ	:=	0x3000
40
41# In IMAGE_BL2, compile time flag for handling Cache coherency
42# with CAAM for BL2 running from OCRAM
43SEC_MEM_NON_COHERENT	:=	yes
44
45# OCRAM MAP for BL2
46# Before BL2
47# 0x18000000 - 0x18009fff -> Used by ROM code
48# 0x1800a000 - 0x1800dfff -> CSF header for BL2
49# For FlexSFlexSPI boot
50# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
51# For SD boot
52# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
53# 0x18030000 - 0x18040000 -> Reserved for SD buffer
54OCRAM_START_ADDR	:=	0x18000000
55OCRAM_SIZE		:=	0x40000
56
57# Area of OCRAM reserved by ROM code
58NXP_ROM_RSVD	:=	0xa000
59
60# Location of BL2 on OCRAM
61BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
62
63# Covert to HEX to be used by create_pbl.mk
64BL2_BASE	:=	$(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
65
66# BL2_HDR_LOC is at  (BL2_BASE + NXP_ROM_RSVD)
67# This value BL2_HDR_LOC + CSF_HDR_SZ should not
68# overalp with BL2_BASE
69# Input to CST create_hdr_isbc tool
70BL2_HDR_LOC	:=	0x1800A000
71
72# SoC ERRATAS to be enabled
73
74# DDR ERRATA
75ERRATA_DDR_A009803	:=	1
76ERRATA_DDR_A009942	:=	1
77ERRATA_DDR_A010165	:=	1
78
79# Enable dynamic memory mapping
80PLAT_XLAT_TABLES_DYNAMIC	:=	1
81
82# Define Endianness of each module
83NXP_GUR_ENDIANNESS	:=	LE
84NXP_DDR_ENDIANNESS	:=	LE
85NXP_SEC_ENDIANNESS	:=	LE
86NXP_SFP_ENDIANNESS	:=	LE
87NXP_SNVS_ENDIANNESS	:=	LE
88NXP_ESDHC_ENDIANNESS	:=	LE
89NXP_QSPI_ENDIANNESS	:=	LE
90NXP_FSPI_ENDIANNESS	:=	LE
91NXP_SCFG_ENDIANNESS	:=	LE
92NXP_GPIO_ENDIANNESS	:=	LE
93
94NXP_SFP_VER		:=	3_4
95
96# OCRAM ECC Enabled
97OCRAM_ECC_EN		:=	yes
98