1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <platform_def.h>
9
10#define S32G_NCORE_CAIU0_BASE_ADDR		UL(0x50400000)
11#define S32G_NCORE_CAIUTC_OFF			U(0x0)
12#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT		U(1)
13
14.globl	plat_crash_console_flush
15.globl	plat_crash_console_init
16.globl	plat_crash_console_putc
17.globl	plat_is_my_cpu_primary
18.globl	plat_my_core_pos
19.globl	plat_reset_handler
20.globl	plat_secondary_cold_boot_setup
21.globl	platform_mem_init
22.globl	s32g2_core_pos_by_mpidr
23
24/* int plat_crash_console_init(void); */
25func plat_crash_console_init
26	mov_imm	x0, UART_BASE
27	mov_imm	x1, UART_CLOCK_HZ
28	mov_imm	x2, UART_BAUDRATE
29	b	console_linflex_core_init
30endfunc plat_crash_console_init
31
32/* int plat_crash_console_putc(int); */
33func plat_crash_console_putc
34	mov_imm	x1, UART_BASE
35	b	console_linflex_core_putc
36	ret
37endfunc plat_crash_console_putc
38
39/* void plat_crash_console_flush(void); */
40func plat_crash_console_flush
41	ret
42endfunc plat_crash_console_flush
43
44/**
45 * unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr);
46 *
47 * In: x0 -  MPIDR_EL1
48 * Out: x0
49 * Clobber list: x0, x1
50 */
51func s32g2_core_pos_by_mpidr
52	and	x1, x0, #MPIDR_CPU_MASK
53	and	x0, x0, #MPIDR_CLUSTER_MASK
54	lsr	x0, x0, #MPIDR_AFF1_SHIFT
55	add	x0, x1, x0, lsl #PLATFORM_MPIDR_CPU_MASK_BITS
56	ret
57endfunc s32g2_core_pos_by_mpidr
58
59/**
60 * unsigned int plat_my_core_pos(void);
61 *
62 * Out: x0
63 * Clobber list: x0, x1, x8
64 */
65func plat_my_core_pos
66	mov	x8, x30
67	mrs x0, mpidr_el1
68	bl	s32g2_core_pos_by_mpidr
69	mov	x30, x8
70	ret
71endfunc plat_my_core_pos
72
73/**
74 * unsigned int plat_is_my_cpu_primary(void);
75 *
76 * Clobber list: x0, x1, x7, x8
77 */
78func plat_is_my_cpu_primary
79	mov	x7, x30
80	bl	plat_my_core_pos
81	cmp	x0, #PLATFORM_PRIMARY_CPU
82	cset	x0, eq
83	mov	x30, x7
84	ret
85endfunc plat_is_my_cpu_primary
86
87
88/**
89 * void plat_secondary_cold_boot_setup (void);
90 */
91func plat_secondary_cold_boot_setup
92	ret
93endfunc plat_secondary_cold_boot_setup
94
95/**
96 * void plat_reset_handler(void);
97 *
98 * Set the CAIUTC[IsolEn] bit for the primary A53 cluster.
99 * This is so cache invalidate operations from the early TF-A boot code
100 * won't cause Ncore to crash.
101 *
102 * Clobber list: x0, x1, x2
103 */
104func plat_reset_handler
105	mov	x0, #S32G_NCORE_CAIU0_BASE_ADDR
106	ldr	w1, [x0, #S32G_NCORE_CAIUTC_OFF]
107	movz	w2, #1
108	lsl	w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT
109	orr	w1, w1, w2
110	str	w1, [x0, #S32G_NCORE_CAIUTC_OFF]
111	ret
112endfunc plat_reset_handler
113
114/* void platform_mem_init(void); */
115func platform_mem_init
116	mov	x10, x30
117	mov	x0, #BL31_BASE
118	mov	x1, #(BL31_LIMIT & 0xFFFFU)
119	movk	x1, #(BL31_LIMIT >> 16), lsl #16
120	sub	x1, x1, x0
121	bl	zeromem
122	mov	x0, #BL33_BASE
123	mov	x1, #(BL33_LIMIT & 0xFFFFU)
124	movk	x1, #(BL33_LIMIT >> 16), lsl #16
125	sub	x1, x1, x0
126	bl	zeromem
127	mov	x30, x10
128	ret
129endfunc platform_mem_init
130
131