1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <arch_helpers.h>
9 #include <common/debug.h>
10 #include <drivers/gpio.h>
11 #include <lib/psci/psci.h>
12
13 #include <mt_gic_v3.h>
14 #include <mtspmc.h>
15 #include <plat/common/platform.h>
16 #include <plat_dfd.h>
17 #include <plat_mtk_lpm.h>
18 #include <plat_params.h>
19 #include <plat_pm.h>
20 #include <pmic.h>
21 #include <rtc.h>
22
23 /*
24 * Cluster state request:
25 * [0] : The CPU requires cluster power down
26 * [1] : The CPU requires cluster power on
27 */
28 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
29 #define coordinate_cluster_pwron() coordinate_cluster(1)
30 #define coordinate_cluster_pwroff() coordinate_cluster(0)
31
32 /* platform secure entry point */
33 static uintptr_t secure_entrypoint;
34 /* per-CPU power state */
35 static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
36
37 /* platform CPU power domain - ops */
38 static const struct mt_lpm_tz *plat_mt_pm;
39
plat_mt_pm_invoke(int (* func)(unsigned int cpu,const psci_power_state_t * state),int cpu,const psci_power_state_t * state)40 static inline int plat_mt_pm_invoke(int (*func)(unsigned int cpu,
41 const psci_power_state_t *state),
42 int cpu, const psci_power_state_t *state)
43 {
44 int ret = -1;
45
46 if (func != NULL) {
47 ret = func(cpu, state);
48 }
49 return ret;
50 }
51
52 /*
53 * Common MTK_platform operations to power on/off a
54 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
55 */
plat_cpu_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)56 static void plat_cpu_pwrdwn_common(unsigned int cpu,
57 const psci_power_state_t *state, unsigned int req_pstate)
58 {
59 assert(cpu == plat_my_core_pos());
60 assert(plat_mt_pm != NULL);
61
62 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_dwn, cpu, state);
63
64 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
65 (req_pstate == 0U)) { /* hotplug off */
66 coordinate_cluster_pwroff();
67 }
68
69 /* Prevent interrupts from spuriously waking up this CPU */
70 mt_gic_rdistif_save();
71 gicv3_cpuif_disable(cpu);
72 gicv3_rdistif_off(cpu);
73 }
74
plat_cpu_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)75 static void plat_cpu_pwron_common(unsigned int cpu,
76 const psci_power_state_t *state, unsigned int req_pstate)
77 {
78 assert(cpu == plat_my_core_pos());
79 assert(plat_mt_pm != NULL);
80
81 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_on, cpu, state);
82
83 coordinate_cluster_pwron();
84
85 /*
86 * If mcusys does power down before then restore
87 * all CPUs' GIC Redistributors
88 */
89 if (IS_MCUSYS_OFF_STATE(state)) {
90 mt_gic_rdistif_restore_all();
91 } else {
92 gicv3_rdistif_on(cpu);
93 gicv3_cpuif_enable(cpu);
94 mt_gic_rdistif_init();
95 mt_gic_rdistif_restore();
96 }
97 }
98
99 /*
100 * Common MTK_platform operations to power on/off a
101 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
102 */
plat_cluster_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)103 static void plat_cluster_pwrdwn_common(unsigned int cpu,
104 const psci_power_state_t *state, unsigned int req_pstate)
105 {
106 assert(cpu == plat_my_core_pos());
107 assert(plat_mt_pm != NULL);
108
109 if (plat_mt_pm_invoke(plat_mt_pm->pwr_cluster_dwn, cpu, state) != 0) {
110 coordinate_cluster_pwron();
111
112 /*
113 * TODO:
114 * Return on fail and add a 'return' here before
115 * adding any code following the if-block.
116 */
117 }
118 }
119
plat_cluster_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)120 static void plat_cluster_pwron_common(unsigned int cpu,
121 const psci_power_state_t *state, unsigned int req_pstate)
122 {
123 assert(cpu == plat_my_core_pos());
124 assert(plat_mt_pm != NULL);
125
126 if (plat_mt_pm_invoke(plat_mt_pm->pwr_cluster_on, cpu, state) != 0) {
127 /*
128 * TODO:
129 * return on fail and add a 'return' here before
130 * adding any code following the if-block.
131 */
132 }
133 }
134
135 /*
136 * Common MTK_platform operations to power on/off a
137 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
138 */
plat_mcusys_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)139 static void plat_mcusys_pwrdwn_common(unsigned int cpu,
140 const psci_power_state_t *state, unsigned int req_pstate)
141 {
142 assert(cpu == plat_my_core_pos());
143 assert(plat_mt_pm != NULL);
144
145 if (plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_dwn, cpu, state) != 0) {
146 return; /* return on fail */
147 }
148
149 mt_gic_distif_save();
150 gic_sgi_save_all();
151 }
152
plat_mcusys_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)153 static void plat_mcusys_pwron_common(unsigned int cpu,
154 const psci_power_state_t *state, unsigned int req_pstate)
155 {
156 assert(cpu == plat_my_core_pos());
157 assert(plat_mt_pm != NULL);
158
159 if (plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_on, cpu, state) != 0) {
160 /* return on fail */
161 return;
162 }
163
164 mt_gic_init();
165 mt_gic_distif_restore();
166 gic_sgi_restore_all();
167
168 dfd_resume();
169
170 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_on_finished, cpu, state);
171 }
172
173 /* plat_psci_ops implementation */
plat_cpu_standby(plat_local_state_t cpu_state)174 static void plat_cpu_standby(plat_local_state_t cpu_state)
175 {
176 uint64_t scr;
177
178 scr = read_scr_el3();
179 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
180
181 isb();
182 dsb();
183 wfi();
184
185 write_scr_el3(scr);
186 }
187
plat_power_domain_on(u_register_t mpidr)188 static int plat_power_domain_on(u_register_t mpidr)
189 {
190 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
191 unsigned int cluster = 0U;
192
193 if (cpu >= PLATFORM_CORE_COUNT) {
194 return PSCI_E_INVALID_PARAMS;
195 }
196
197 if (!spm_get_cluster_powerstate(cluster)) {
198 spm_poweron_cluster(cluster);
199 }
200
201 /* init CPU reset arch as AARCH64 */
202 mcucfg_init_archstate(cluster, cpu, true);
203 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
204 spm_poweron_cpu(cluster, cpu);
205
206 return PSCI_E_SUCCESS;
207 }
208
plat_power_domain_on_finish(const psci_power_state_t * state)209 static void plat_power_domain_on_finish(const psci_power_state_t *state)
210 {
211 unsigned long mpidr = read_mpidr_el1();
212 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
213
214 assert(cpu < PLATFORM_CORE_COUNT);
215
216 /* Allow IRQs to wakeup this core in IDLE flow */
217 mcucfg_enable_gic_wakeup(0U, cpu);
218
219 if (IS_CLUSTER_OFF_STATE(state)) {
220 plat_cluster_pwron_common(cpu, state, 0U);
221 }
222
223 plat_cpu_pwron_common(cpu, state, 0U);
224 }
225
plat_power_domain_off(const psci_power_state_t * state)226 static void plat_power_domain_off(const psci_power_state_t *state)
227 {
228 unsigned long mpidr = read_mpidr_el1();
229 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
230
231 assert(cpu < PLATFORM_CORE_COUNT);
232
233 plat_cpu_pwrdwn_common(cpu, state, 0U);
234 spm_poweroff_cpu(0U, cpu);
235
236 /* prevent unintended IRQs from waking up the hot-unplugged core */
237 mcucfg_disable_gic_wakeup(0U, cpu);
238
239 if (IS_CLUSTER_OFF_STATE(state)) {
240 plat_cluster_pwrdwn_common(cpu, state, 0U);
241 }
242 }
243
plat_power_domain_suspend(const psci_power_state_t * state)244 static void plat_power_domain_suspend(const psci_power_state_t *state)
245 {
246 unsigned int cpu = plat_my_core_pos();
247
248 assert(cpu < PLATFORM_CORE_COUNT);
249 assert(plat_mt_pm != NULL);
250
251 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_prompt, cpu, state);
252
253 /* Perform the common CPU specific operations */
254 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
255
256 if (IS_CLUSTER_OFF_STATE(state)) {
257 /* Perform the common cluster specific operations */
258 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
259 }
260
261 if (IS_MCUSYS_OFF_STATE(state)) {
262 /* Perform the common mcusys specific operations */
263 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
264 }
265 }
266
plat_power_domain_suspend_finish(const psci_power_state_t * state)267 static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
268 {
269 unsigned int cpu = plat_my_core_pos();
270
271 assert(cpu < PLATFORM_CORE_COUNT);
272 assert(plat_mt_pm != NULL);
273
274 if (IS_MCUSYS_OFF_STATE(state)) {
275 /* Perform the common mcusys specific operations */
276 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
277 }
278
279 if (IS_CLUSTER_OFF_STATE(state)) {
280 /* Perform the common cluster specific operations */
281 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
282 }
283
284 /* Perform the common CPU specific operations */
285 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
286
287 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_reflect, cpu, state);
288 }
289
plat_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)290 static int plat_validate_power_state(unsigned int power_state,
291 psci_power_state_t *req_state)
292 {
293 unsigned int pstate = psci_get_pstate_type(power_state);
294 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
295 unsigned int cpu = plat_my_core_pos();
296
297 if (aff_lvl > PLAT_MAX_PWR_LVL) {
298 return PSCI_E_INVALID_PARAMS;
299 }
300
301 if (pstate == PSTATE_TYPE_STANDBY) {
302 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
303 } else {
304 unsigned int i;
305 unsigned int pstate_id = psci_get_pstate_id(power_state);
306 plat_local_state_t s = MTK_LOCAL_STATE_OFF;
307
308 /* Use pstate_id to be power domain state */
309 if (pstate_id > s) {
310 s = (plat_local_state_t)pstate_id;
311 }
312
313 for (i = 0U; i <= aff_lvl; i++) {
314 req_state->pwr_domain_state[i] = s;
315 }
316 }
317
318 plat_power_state[cpu] = power_state;
319 return PSCI_E_SUCCESS;
320 }
321
plat_get_sys_suspend_power_state(psci_power_state_t * req_state)322 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
323 {
324 unsigned int lv;
325 unsigned int cpu = plat_my_core_pos();
326
327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
328 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
329 }
330
331 plat_power_state[cpu] =
332 psci_make_powerstate(
333 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
334 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
335
336 flush_dcache_range((uintptr_t)
337 &plat_power_state[cpu],
338 sizeof(plat_power_state[cpu]));
339 }
340
341 /*******************************************************************************
342 * MTK handlers to shutdown/reboot the system
343 ******************************************************************************/
plat_mtk_system_reset(void)344 static void __dead2 plat_mtk_system_reset(void)
345 {
346 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
347
348 INFO("MTK System Reset\n");
349
350 gpio_set_value(gpio_reset->index, gpio_reset->polarity);
351
352 wfi();
353 ERROR("MTK System Reset: operation not handled.\n");
354 panic();
355 }
356
plat_mtk_system_off(void)357 static void __dead2 plat_mtk_system_off(void)
358 {
359 INFO("MTK System Off\n");
360
361 rtc_power_off_sequence();
362 pmic_power_off();
363
364 wfi();
365 ERROR("MTK System Off: operation not handled.\n");
366 panic();
367 }
368
369 static const plat_psci_ops_t plat_psci_ops = {
370 .cpu_standby = plat_cpu_standby,
371 .pwr_domain_on = plat_power_domain_on,
372 .pwr_domain_on_finish = plat_power_domain_on_finish,
373 .pwr_domain_off = plat_power_domain_off,
374 .pwr_domain_suspend = plat_power_domain_suspend,
375 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
376 .validate_power_state = plat_validate_power_state,
377 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
378 .system_off = plat_mtk_system_off,
379 .system_reset = plat_mtk_system_reset,
380 };
381
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)382 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
383 const plat_psci_ops_t **psci_ops)
384 {
385 *psci_ops = &plat_psci_ops;
386 secure_entrypoint = sec_entrypoint;
387
388 /*
389 * init the warm reset config for boot CPU
390 * reset arch as AARCH64
391 * reset addr as function bl31_warm_entrypoint()
392 */
393 mcucfg_init_archstate(0U, 0U, true);
394 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
395
396 spmc_init();
397 plat_mt_pm = mt_plat_cpu_pm_init();
398
399 return 0;
400 }
401