1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCUCFG_H 8 #define MCUCFG_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdint.h> 12 #endif /* __ASSEMBLER__ */ 13 14 #include <platform_def.h> 15 16 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs)) 17 18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8)) 19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8)) 20 21 #define MP2_CPUCFG MCUCFG_REG(0x2208) 22 23 #define MP2_CPU0_STANDBYWFE BIT(4) 24 #define MP2_CPU1_STANDBYWFE BIT(5) 25 26 #define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788) 27 #define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C) 28 #define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790) 29 30 #define sw_spark_en BIT(0) 31 #define sw_no_wait_for_q_channel BIT(1) 32 #define sw_fsm_override BIT(2) 33 #define sw_logic_pre1_pdb BIT(3) 34 #define sw_logic_pre2_pdb BIT(4) 35 #define sw_logic_pdb BIT(5) 36 #define sw_iso BIT(6) 37 #define sw_sram_sleepb (U(0x3F) << 7) 38 #define sw_sram_isointb BIT(13) 39 #define sw_clk_dis BIT(14) 40 #define sw_ckiso BIT(15) 41 #define sw_pd (U(0x3F) << 16) 42 #define sw_hot_plug_reset BIT(22) 43 #define sw_pwr_on_override_en BIT(23) 44 #define sw_pwr_on BIT(24) 45 #define sw_coq_dis BIT(25) 46 #define logic_pdbo_all_off_ack BIT(26) 47 #define logic_pdbo_all_on_ack BIT(27) 48 #define logic_pre2_pdbo_all_on_ack BIT(28) 49 #define logic_pre1_pdbo_all_on_ack BIT(29) 50 51 52 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ 53 (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4) 54 55 #define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30) 56 #define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34) 57 #define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38) 58 #define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C) 59 60 #define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30) 61 #define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34) 62 #define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38) 63 #define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C) 64 65 #define cpu_sw_spark_en BIT(0) 66 #define cpu_sw_no_wait_for_q_channel BIT(1) 67 #define cpu_sw_fsm_override BIT(2) 68 #define cpu_sw_logic_pre1_pdb BIT(3) 69 #define cpu_sw_logic_pre2_pdb BIT(4) 70 #define cpu_sw_logic_pdb BIT(5) 71 #define cpu_sw_iso BIT(6) 72 #define cpu_sw_sram_sleepb BIT(7) 73 #define cpu_sw_sram_isointb BIT(8) 74 #define cpu_sw_clk_dis BIT(9) 75 #define cpu_sw_ckiso BIT(10) 76 #define cpu_sw_pd (U(0x1F) << 11) 77 #define cpu_sw_hot_plug_reset BIT(16) 78 #define cpu_sw_powr_on_override_en BIT(17) 79 #define cpu_sw_pwr_on BIT(18) 80 #define cpu_spark2ldo_allswoff BIT(19) 81 #define cpu_pdbo_all_on_ack BIT(20) 82 #define cpu_pre2_pdbo_allon_ack BIT(21) 83 #define cpu_pre1_pdbo_allon_ack BIT(22) 84 85 /* CPC related registers */ 86 #define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714) 87 #define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804) 88 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814) 89 #define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818) 90 #define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c) 91 #define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824) 92 #define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828) 93 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8) 94 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac) 95 #define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00) 96 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04) 97 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08) 98 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c) 99 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10) 100 #define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14) 101 #define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20) 102 #define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70) 103 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74) 104 #define SPARK2LDO MCUCFG_REG(0x2700) 105 /* APB module mcucfg */ 106 #define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000) 107 #define MP0_AXI_CONFIG MCUCFG_REG(0x02C) 108 #define MP0_MISC_CONFIG0 MCUCFG_REG(0x030) 109 #define MP0_MISC_CONFIG1 MCUCFG_REG(0x034) 110 #define MP0_MISC_CONFIG2 MCUCFG_REG(0x038) 111 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8)) 112 #define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C) 113 #define MP0_MISC_CONFIG9 MCUCFG_REG(0x054) 114 #define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064) 115 116 #define MP0_RW_RSVD0 MCUCFG_REG(0x06C) 117 118 119 #define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200) 120 #define MP1_AXI_CONFIG MCUCFG_REG(0x22C) 121 #define MP1_MISC_CONFIG0 MCUCFG_REG(0x230) 122 #define MP1_MISC_CONFIG1 MCUCFG_REG(0x234) 123 #define MP1_MISC_CONFIG2 MCUCFG_REG(0x238) 124 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8)) 125 #define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C) 126 #define MP1_MISC_CONFIG9 MCUCFG_REG(0x254) 127 #define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264) 128 129 #define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740) 130 #define SYNC_DCM_CONFIG MCUCFG_REG(0x744) 131 132 #define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0) 133 134 #define MP0_SPMC MCUCFG_REG(0x788) 135 #define MP1_SPMC MCUCFG_REG(0x78C) 136 #define MP2_AXI_CONFIG MCUCFG_REG(0x220C) 137 #define MP2_AXI_CONFIG_ACINACTM BIT(0) 138 #define MP2_AXI_CONFIG_AINACTS BIT(4) 139 140 #define MPx_AXI_CONFIG_ACINACTM BIT(4) 141 #define MPx_AXI_CONFIG_AINACTS BIT(5) 142 #define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28) 143 144 #define MP0_CPU0_STANDBYWFE BIT(20) 145 #define MP0_CPU1_STANDBYWFE BIT(21) 146 #define MP0_CPU2_STANDBYWFE BIT(22) 147 #define MP0_CPU3_STANDBYWFE BIT(23) 148 149 #define MP1_CPU0_STANDBYWFE BIT(20) 150 #define MP1_CPU1_STANDBYWFE BIT(21) 151 #define MP1_CPU2_STANDBYWFE BIT(22) 152 #define MP1_CPU3_STANDBYWFE BIT(23) 153 154 #define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00) 155 #define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04) 156 #define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08) 157 #define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00) 158 #define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04) 159 #define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08) 160 161 #define MP2_PWR_RST_CTL MCUCFG_REG(0x2008) 162 #define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0) 163 #define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4) 164 165 #define MP2_COQ MCUCFG_REG(0x22BC) 166 #define MP2_COQ_SW_DIS BIT(0) 167 168 #define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400) 169 #define MP2_CA15M_MON_L MCUCFG_REG(0x2404) 170 171 #define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430) 172 #define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438) 173 #define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434) 174 #define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C) 175 176 #define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068) 177 #define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268) 178 #define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C) 179 180 #define MP2_SW_RST_B BIT(0) 181 #define MP2_TOPAON_APB_MASK BIT(1) 182 183 #define B_SW_HOT_PLUG_RESET BIT(30) 184 185 #define B_SW_PD_OFFSET (18U) 186 #define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET) 187 188 #define B_SW_SRAM_SLEEPB_OFFSET (12U) 189 #define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET) 190 191 #define B_SW_SRAM_ISOINTB BIT(9) 192 #define B_SW_ISO BIT(8) 193 #define B_SW_LOGIC_PDB BIT(7) 194 #define B_SW_LOGIC_PRE2_PDB BIT(6) 195 #define B_SW_LOGIC_PRE1_PDB BIT(5) 196 #define B_SW_FSM_OVERRIDE BIT(4) 197 #define B_SW_PWR_ON BIT(3) 198 #define B_SW_PWR_ON_OVERRIDE_EN BIT(2) 199 200 #define B_FSM_STATE_OUT_OFFSET (6U) 201 #define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET) 202 #define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5) 203 #define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4) 204 #define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3) 205 #define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2) 206 207 #define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET) 208 #define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET) 209 #define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET) 210 211 #ifndef __ASSEMBLER__ 212 /* cpu boot mode */ 213 enum { 214 MP0_CPUCFG_64BIT_SHIFT = 12U, 215 MP1_CPUCFG_64BIT_SHIFT = 28U, 216 MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT, 217 MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT 218 }; 219 220 enum { 221 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U, 222 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U, 223 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U, 224 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U, 225 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U, 226 227 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 228 U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 229 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 230 U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 231 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 232 U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 233 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 234 U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 235 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 236 U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 237 }; 238 239 enum { 240 MP1_AINACTS_SHIFT = 4U, 241 MP1_AINACTS = 1U << MP1_AINACTS_SHIFT 242 }; 243 244 enum { 245 MP1_SW_CG_GEN_SHIFT = 12U, 246 MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT 247 }; 248 249 enum { 250 MP1_L2RSTDISABLE_SHIFT = 14U, 251 MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT 252 }; 253 #endif /* __ASSEMBLER__ */ 254 255 #endif /* MCUCFG_H */ 256