1 /*
2  * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MCUCFG_V1_H
8 #define MCUCFG_V1_H
9 
10 #ifndef __ASSEMBLER__
11 #include <stdint.h>
12 #endif /*__ASSEMBLER__*/
13 
14 #include <platform_def.h>
15 
16 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu)	(MCUCFG_BASE + 0x2290 + ((cpu) * 8))
17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu)	(MCUCFG_BASE + 0x2294 + ((cpu) * 8))
18 
19 #define MP2_CPUCFG				(MCUCFG_BASE + 0x2208)
20 
21 #define MP0_CPUTOP_SPMC_CTL			(MCUCFG_BASE + 0x788)
22 #define MP1_CPUTOP_SPMC_CTL			(MCUCFG_BASE + 0x78C)
23 #define MP1_CPUTOP_SPMC_SRAM_CTL		(MCUCFG_BASE + 0x790)
24 
25 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu)	(MCUCFG_BASE + 0x1C30 + \
26 						 (cluster) * 0x2000 + (cpu) * 4)
27 
28 #define CPUSYS0_CPU0_SPMC_CTL			(MCUCFG_BASE + 0x1C30)
29 #define CPUSYS0_CPU1_SPMC_CTL			(MCUCFG_BASE + 0x1C34)
30 #define CPUSYS0_CPU2_SPMC_CTL			(MCUCFG_BASE + 0x1C38)
31 #define CPUSYS0_CPU3_SPMC_CTL			(MCUCFG_BASE + 0x1C3C)
32 
33 #define CPUSYS1_CPU0_SPMC_CTL			(MCUCFG_BASE + 0x3C30)
34 #define CPUSYS1_CPU1_SPMC_CTL			(MCUCFG_BASE + 0x3C34)
35 #define CPUSYS1_CPU2_SPMC_CTL			(MCUCFG_BASE + 0x3C38)
36 #define CPUSYS1_CPU3_SPMC_CTL			(MCUCFG_BASE + 0x3C3C)
37 
38 /* CPC related registers */
39 #define CPC_MCUSYS_CPC_OFF_THRES		(MCUCFG_BASE + 0xA714)
40 #define CPC_MCUSYS_PWR_CTRL			(MCUCFG_BASE + 0xA804)
41 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG		(MCUCFG_BASE + 0xA814)
42 #define CPC_MCUSYS_LAST_CORE_REQ		(MCUCFG_BASE + 0xA818)
43 #define CPC_MCUSYS_MP_LAST_CORE_RESP		(MCUCFG_BASE + 0xA81C)
44 #define CPC_MCUSYS_LAST_CORE_RESP		(MCUCFG_BASE + 0xA824)
45 #define CPC_MCUSYS_PWR_ON_MASK			(MCUCFG_BASE + 0xA828)
46 #define CPC_SPMC_PWR_STATUS			(MCUCFG_BASE + 0xA840)
47 #define CPC_MCUSYS_CPU_ON_SW_HINT_SET		(MCUCFG_BASE + 0xA8A8)
48 #define CPC_MCUSYS_CPU_ON_SW_HINT_CLR		(MCUCFG_BASE + 0xA8AC)
49 #define CPC_MCUSYS_CPC_DBG_SETTING		(MCUCFG_BASE + 0xAB00)
50 #define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE	(MCUCFG_BASE + 0xAB04)
51 #define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE	(MCUCFG_BASE + 0xAB08)
52 #define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE	(MCUCFG_BASE + 0xAB0C)
53 #define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE	(MCUCFG_BASE + 0xAB10)
54 #define CPC_MCUSYS_TRACE_SEL			(MCUCFG_BASE + 0xAB14)
55 #define CPC_MCUSYS_TRACE_DATA			(MCUCFG_BASE + 0xAB20)
56 #define CPC_MCUSYS_CLUSTER_COUNTER		(MCUCFG_BASE + 0xAB70)
57 #define CPC_MCUSYS_CLUSTER_COUNTER_CLR		(MCUCFG_BASE + 0xAB74)
58 
59 /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG bit control */
60 #define CPC_CTRL_ENABLE				BIT(16)
61 #define SSPM_CORE_PWR_ON_EN			BIT(7) /* for cpu-hotplug */
62 #define SSPM_ALL_PWR_CTRL_EN			BIT(13) /* for cpu-hotplug */
63 #define GIC_WAKEUP_IGNORE(cpu)			BIT(21 + cpu)
64 
65 #define CPC_MCUSYS_CPC_RESET_ON_KEEP_ON		BIT(17)
66 #define CPC_MCUSYS_CPC_RESET_PWR_ON_EN		BIT(20)
67 
68 /* SPMC related registers */
69 #define SPM_MCUSYS_PWR_CON			(MCUCFG_BASE + 0xD200)
70 #define SPM_MP0_CPUTOP_PWR_CON			(MCUCFG_BASE + 0xD204)
71 #define SPM_MP0_CPU0_PWR_CON			(MCUCFG_BASE + 0xD208)
72 #define SPM_MP0_CPU1_PWR_CON			(MCUCFG_BASE + 0xD20C)
73 #define SPM_MP0_CPU2_PWR_CON			(MCUCFG_BASE + 0xD210)
74 #define SPM_MP0_CPU3_PWR_CON			(MCUCFG_BASE + 0xD214)
75 #define SPM_MP0_CPU4_PWR_CON			(MCUCFG_BASE + 0xD218)
76 #define SPM_MP0_CPU5_PWR_CON			(MCUCFG_BASE + 0xD21C)
77 #define SPM_MP0_CPU6_PWR_CON			(MCUCFG_BASE + 0xD220)
78 #define SPM_MP0_CPU7_PWR_CON			(MCUCFG_BASE + 0xD224)
79 
80 /* bit fields of SPM_*_PWR_CON */
81 #define PWR_ON_ACK				BIT(31)
82 #define VPROC_EXT_OFF				BIT(7)
83 #define DORMANT_EN				BIT(6)
84 #define RESETPWRON_CONFIG			BIT(5)
85 #define PWR_CLK_DIS				BIT(4)
86 #define PWR_ON					BIT(2)
87 #define PWR_RST_B				BIT(0)
88 
89 #define SPARK2LDO				(MCUCFG_BASE + 0x2700)
90 /* APB Module mcucfg */
91 #define MP0_CA7_CACHE_CONFIG			(MCUCFG_BASE + 0x000)
92 #define MP0_AXI_CONFIG				(MCUCFG_BASE + 0x02C)
93 #define MP0_MISC_CONFIG0			(MCUCFG_BASE + 0x030)
94 #define MP0_MISC_CONFIG1			(MCUCFG_BASE + 0x034)
95 #define MP0_MISC_CONFIG2			(MCUCFG_BASE + 0x038)
96 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu)		(MCUCFG_BASE + 0x038 + ((cpu) * 8))
97 #define MP0_MISC_CONFIG3			(MCUCFG_BASE + 0x03C)
98 #define MP0_MISC_CONFIG9			(MCUCFG_BASE + 0x054)
99 #define MP0_CA7_MISC_CONFIG			(MCUCFG_BASE + 0x064)
100 
101 #define MP0_RW_RSVD0				(MCUCFG_BASE + 0x06C)
102 #define MP1_CA7_CACHE_CONFIG			(MCUCFG_BASE + 0x200)
103 #define MP1_AXI_CONFIG				(MCUCFG_BASE + 0x22C)
104 #define MP1_MISC_CONFIG0			(MCUCFG_BASE + 0x230)
105 #define MP1_MISC_CONFIG1			(MCUCFG_BASE + 0x234)
106 #define MP1_MISC_CONFIG2			(MCUCFG_BASE + 0x238)
107 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu)		(MCUCFG_BASE + 0x238 + ((cpu) * 8))
108 #define MP1_MISC_CONFIG3			(MCUCFG_BASE + 0x23C)
109 #define MP1_MISC_CONFIG9			(MCUCFG_BASE + 0x254)
110 #define MP1_CA7_MISC_CONFIG			(MCUCFG_BASE + 0x264)
111 
112 #define CCI_ADB400_DCM_CONFIG			(MCUCFG_BASE + 0x740)
113 #define SYNC_DCM_CONFIG				(MCUCFG_BASE + 0x744)
114 
115 #define MP0_CLUSTER_CFG0			(MCUCFG_BASE + 0xC8D0)
116 
117 #define MP0_SPMC				(MCUCFG_BASE + 0x788)
118 #define MP1_SPMC				(MCUCFG_BASE + 0x78C)
119 #define MP2_AXI_CONFIG				(MCUCFG_BASE + 0x220C)
120 #define MP2_AXI_CONFIG_ACINACTM			BIT(0)
121 #define MP2_AXI_CONFIG_AINACTS			BIT(4)
122 
123 #define MPx_AXI_CONFIG_ACINACTM			BIT(4)
124 #define MPx_AXI_CONFIG_AINACTS			BIT(5)
125 
126 #define MPx_CA7_MISC_CONFIG_standbywfil2	BIT(28)
127 
128 #define MP0_CPU0_STANDBYWFE			BIT(20)
129 #define MP0_CPU1_STANDBYWFE			BIT(21)
130 #define MP0_CPU2_STANDBYWFE			BIT(22)
131 #define MP0_CPU3_STANDBYWFE			BIT(23)
132 
133 #define MP1_CPU0_STANDBYWFE			BIT(20)
134 #define MP1_CPU1_STANDBYWFE			BIT(21)
135 #define MP1_CPU2_STANDBYWFE			BIT(22)
136 #define MP1_CPU3_STANDBYWFE			BIT(23)
137 
138 #define CPUSYS0_SPARKVRETCNTRL			(MCUCFG_BASE+0x1c00)
139 #define CPUSYS0_SPARKEN				(MCUCFG_BASE+0x1c04)
140 #define CPUSYS0_AMUXSEL				(MCUCFG_BASE+0x1c08)
141 #define CPUSYS1_SPARKVRETCNTRL			(MCUCFG_BASE+0x3c00)
142 #define CPUSYS1_SPARKEN				(MCUCFG_BASE+0x3c04)
143 #define CPUSYS1_AMUXSEL				(MCUCFG_BASE+0x3c08)
144 
145 #define MP2_PWR_RST_CTL				(MCUCFG_BASE + 0x2008)
146 #define MP2_PTP3_CPUTOP_SPMC0			(MCUCFG_BASE + 0x22A0)
147 #define MP2_PTP3_CPUTOP_SPMC1			(MCUCFG_BASE + 0x22A4)
148 
149 #define MP2_COQ					(MCUCFG_BASE + 0x22BC)
150 #define MP2_COQ_SW_DIS				BIT(0)
151 
152 #define MP2_CA15M_MON_SEL			(MCUCFG_BASE + 0x2400)
153 #define MP2_CA15M_MON_L				(MCUCFG_BASE + 0x2404)
154 
155 #define CPUSYS2_CPU0_SPMC_CTL			(MCUCFG_BASE + 0x2430)
156 #define CPUSYS2_CPU1_SPMC_CTL			(MCUCFG_BASE + 0x2438)
157 #define CPUSYS2_CPU0_SPMC_STA			(MCUCFG_BASE + 0x2434)
158 #define CPUSYS2_CPU1_SPMC_STA			(MCUCFG_BASE + 0x243C)
159 
160 #define MP0_CA7L_DBG_PWR_CTRL			(MCUCFG_BASE + 0x068)
161 #define MP1_CA7L_DBG_PWR_CTRL			(MCUCFG_BASE + 0x268)
162 #define BIG_DBG_PWR_CTRL			(MCUCFG_BASE + 0x75C)
163 
164 #define MP2_SW_RST_B				BIT(0)
165 #define MP2_TOPAON_APB_MASK			BIT(1)
166 #define B_SW_HOT_PLUG_RESET			BIT(30)
167 #define B_SW_PD_OFFSET				(18)
168 #define B_SW_PD					(0x3F << B_SW_PD_OFFSET)
169 
170 #define B_SW_SRAM_SLEEPB_OFFSET			(12)
171 #define B_SW_SRAM_SLEEPB			(0x3F << B_SW_SRAM_SLEEPB_OFFSET)
172 
173 #define B_SW_SRAM_ISOINTB			BIT(9)
174 #define B_SW_ISO				BIT(8)
175 #define B_SW_LOGIC_PDB				BIT(7)
176 #define B_SW_LOGIC_PRE2_PDB			BIT(6)
177 #define B_SW_LOGIC_PRE1_PDB			BIT(5)
178 #define B_SW_FSM_OVERRIDE			BIT(4)
179 #define B_SW_PWR_ON				BIT(3)
180 #define B_SW_PWR_ON_OVERRIDE_EN			BIT(2)
181 
182 #define B_FSM_STATE_OUT_OFFSET			(6)
183 #define B_FSM_STATE_OUT_MASK			(0x1F << B_FSM_STATE_OUT_OFFSET)
184 #define B_SW_LOGIC_PDBO_ALL_OFF_ACK		BIT(5)
185 #define B_SW_LOGIC_PDBO_ALL_ON_ACK		BIT(4)
186 #define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK		BIT(3)
187 #define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK		BIT(2)
188 
189 
190 #define B_FSM_OFF				(0U << B_FSM_STATE_OUT_OFFSET)
191 #define B_FSM_ON				(1U << B_FSM_STATE_OUT_OFFSET)
192 #define B_FSM_RET				(2U << B_FSM_STATE_OUT_OFFSET)
193 
194 #ifndef __ASSEMBLER__
195 /* cpu boot mode */
196 enum mp0_coucfg_64bit_ctrl {
197 	MP0_CPUCFG_64BIT_SHIFT = 12,
198 	MP1_CPUCFG_64BIT_SHIFT = 28,
199 	MP0_CPUCFG_64BIT = 0xfu << MP0_CPUCFG_64BIT_SHIFT,
200 	MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT,
201 };
202 
203 enum mp1_dis_rgu0_ctrl {
204 	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
205 	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
206 	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
207 	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
208 	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
209 	MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
210 	MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
211 	MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
212 	MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
213 	MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 0xF << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT,
214 };
215 
216 enum mp1_ainacts_ctrl {
217 	MP1_AINACTS_SHIFT = 4,
218 	MP1_AINACTS = 1U << MP1_AINACTS_SHIFT,
219 };
220 
221 enum mp1_sw_cg_gen {
222 	MP1_SW_CG_GEN_SHIFT = 12,
223 	MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT,
224 };
225 
226 enum mp1_l2rstdisable {
227 	MP1_L2RSTDISABLE_SHIFT = 14,
228 	MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT,
229 };
230 #endif /*__ASSEMBLER__*/
231 
232 #endif  /* MCUCFG_V1_H */
233