1#
2# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
3# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8PLAT_INCLUDES		:=	\
9			-Iplat/intel/soc/stratix10/include/		\
10			-Iplat/intel/soc/common/drivers/		\
11			-Iplat/intel/soc/common/include/
12
13# Include GICv2 driver files
14include drivers/arm/gic/v2/gicv2.mk
15AGX_GICv2_SOURCES	:=	\
16			${GICV2_SOURCES}				\
17			plat/common/plat_gicv2.c
18
19
20PLAT_BL_COMMON_SOURCES	:=	\
21			${AGX_GICv2_SOURCES}				\
22			drivers/delay_timer/delay_timer.c		\
23			drivers/delay_timer/generic_delay_timer.c  	\
24			drivers/ti/uart/aarch64/16550_console.S		\
25			lib/xlat_tables/aarch64/xlat_tables.c 		\
26			lib/xlat_tables/xlat_tables_common.c 		\
27			plat/intel/soc/common/aarch64/platform_common.c \
28			plat/intel/soc/common/aarch64/plat_helpers.S	\
29			plat/intel/soc/common/socfpga_delay_timer.c	\
30			plat/intel/soc/common/soc/socfpga_firewall.c
31
32BL2_SOURCES     +=	\
33		common/desc_image_load.c				\
34		drivers/mmc/mmc.c					\
35		drivers/intel/soc/stratix10/io/s10_memmap_qspi.c	\
36		drivers/io/io_storage.c					\
37		drivers/io/io_block.c					\
38		drivers/io/io_fip.c					\
39		drivers/partition/partition.c				\
40		drivers/partition/gpt.c					\
41		drivers/synopsys/emmc/dw_mmc.c				\
42		lib/cpus/aarch64/cortex_a53.S				\
43		plat/intel/soc/stratix10/bl2_plat_setup.c		\
44		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
45		plat/intel/soc/stratix10/soc/s10_memory_controller.c	\
46		plat/intel/soc/stratix10/soc/s10_mmc.c			\
47		plat/intel/soc/stratix10/soc/s10_pinmux.c		\
48		plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
49		plat/intel/soc/common/socfpga_image_load.c		\
50		plat/intel/soc/common/socfpga_storage.c			\
51		plat/intel/soc/common/soc/socfpga_emac.c		\
52		plat/intel/soc/common/soc/socfpga_handoff.c		\
53		plat/intel/soc/common/soc/socfpga_mailbox.c		\
54		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
55		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
56		plat/intel/soc/common/drivers/ddr/ddr.c	\
57		plat/intel/soc/common/drivers/wdt/watchdog.c
58
59include lib/zlib/zlib.mk
60PLAT_INCLUDES	+=	-Ilib/zlib
61BL2_SOURCES	+=	$(ZLIB_SOURCES)
62
63BL31_SOURCES	+=	\
64		drivers/arm/cci/cci.c					\
65		lib/cpus/aarch64/aem_generic.S				\
66		lib/cpus/aarch64/cortex_a53.S				\
67		plat/common/plat_psci_common.c				\
68		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
69		plat/intel/soc/stratix10/bl31_plat_setup.c	 	\
70		plat/intel/soc/common/socfpga_psci.c			\
71		plat/intel/soc/common/socfpga_sip_svc.c			\
72		plat/intel/soc/common/socfpga_sip_svc_v2.c		\
73		plat/intel/soc/common/socfpga_topology.c		\
74		plat/intel/soc/common/sip/socfpga_sip_ecc.c		\
75		plat/intel/soc/common/sip/socfpga_sip_fcs.c		\
76		plat/intel/soc/common/soc/socfpga_mailbox.c		\
77		plat/intel/soc/common/soc/socfpga_reset_manager.c
78
79$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
80
81PROGRAMMABLE_RESET_ADDRESS	:= 0
82RESET_TO_BL2			:= 1
83USE_COHERENT_MEM		:= 1
84