1/*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <cortex_a55.h>
9
10#include <platform_def.h>
11
12	.globl	plat_is_my_cpu_primary
13	.globl	plat_my_core_pos
14	.globl	plat_calc_core_pos
15	.globl	platform_mem_init
16
17	/* ------------------------------------------------------
18	 * Helper macro that reads the part number of the current
19	 * CPU and jumps to the given label if it matches the CPU
20	 * MIDR provided.
21	 *
22	 * Clobbers x0.
23	 * ------------------------------------------------------
24	 */
25	.macro  jump_if_cpu_midr _cpu_midr, _label
26
27	mrs	x0, midr_el1
28	ubfx	x0, x0, MIDR_PN_SHIFT, #12
29	cmp     w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
30	b.eq	\_label
31
32	.endm
33
34	/* ----------------------------------------------
35	 * unsigned int plat_is_my_cpu_primary(void);
36	 * This function checks if this is the primary CPU
37	 * ----------------------------------------------
38	 */
39func plat_is_my_cpu_primary
40	mrs	x0, mpidr_el1
41	mov_imm x1, MPIDR_AFFINITY_MASK
42	and	x0, x0, x1
43	cmp	x0, #PLAT_PRIMARY_CPU
44	cset	x0, eq
45	ret
46endfunc plat_is_my_cpu_primary
47
48	/* ----------------------------------------------
49	 * unsigned int plat_my_core_pos(void)
50	 * This function uses the plat_calc_core_pos()
51	 * to get the index of the calling CPU.
52	 * ----------------------------------------------
53	 */
54func plat_my_core_pos
55	mrs	x0, mpidr_el1
56	mov	x1, #MPIDR_AFFLVL_MASK
57	and	x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
58	ret
59endfunc plat_my_core_pos
60
61	/*
62	 * unsigned int plat_calc_core_pos(uint64_t mpidr)
63	 * helper function to calculate the core position.
64	 * With this function.
65	 */
66func plat_calc_core_pos
67	mov	x1, #MPIDR_AFFLVL_MASK
68	and	x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
69	ret
70endfunc plat_calc_core_pos
71
72func platform_mem_init
73	ret
74endfunc platform_mem_init
75