1 /* 2 * Copyright 2020-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <xrdc.h> 8 9 #define SP(X) ((X) << 9) 10 #define SU(X) ((X) << 6) 11 #define NP(X) ((X) << 3) 12 #define NU(X) ((X) << 0) 13 14 #define RWX 7 15 #define RW 6 16 #define R 4 17 #define X 1 18 19 struct xrdc_mda_config imx8ulp_mda[] = { 20 { 0, 7, MDA_SA_PT }, /* A core */ 21 { 1, 1, MDA_SA_NS }, /* DMA1 */ 22 { 2, 1, MDA_SA_NS }, /* USB */ 23 { 3, 1, MDA_SA_NS }, /* PXP-> .M10 */ 24 { 4, 1, MDA_SA_NS }, /* ENET */ 25 { 5, 1, MDA_SA_PT }, /* CAAM */ 26 { 6, 1, MDA_SA_NS }, /* USDHC0 */ 27 { 7, 1, MDA_SA_NS }, /* USDHC1 */ 28 { 8, 1, MDA_SA_NS }, /* USDHC2 */ 29 { 9, 2, MDA_SA_NS }, /* HIFI4 */ 30 { 10, 3, MDA_SA_NS }, /* GPU3D */ 31 { 11, 3, MDA_SA_NS }, /* GPU2D */ 32 { 12, 3, MDA_SA_NS }, /* EPDC */ 33 { 13, 3, MDA_SA_NS }, /* DCNano */ 34 { 14, 3, MDA_SA_NS }, /* ISI */ 35 { 15, 3, MDA_SA_NS }, /* PXP->NIC_LPAV.M0 */ 36 { 16, 3, MDA_SA_NS }, /* DMA2 */ 37 }; 38 39 #ifdef SPD_opteed 40 #define TEE_SHM_SIZE 0x400000 41 #else 42 #define TEE_SHM_SIZE 0x0 43 #endif 44 45 #if defined(SPD_opteed) || defined(SPD_trusty) 46 #define DRAM_MEM_0_START (0x80000000) 47 #define DRAM_MEM_0_SIZE (BL32_BASE - 0x80000000) 48 49 #define DRAM_MEM_1_START (BL32_BASE) 50 #define DRAM_MEM_1_SIZE (BL32_SIZE - TEE_SHM_SIZE) 51 52 #ifndef SPD_trusty 53 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE) 54 #define DRAM_MEM_2_SIZE (0x80000000 - DRAM_MEM_1_SIZE - DRAM_MEM_0_SIZE) 55 #else 56 #define SECURE_HEAP_START (0xA9600000) 57 #define SECURE_HEAP_SIZE (0x6000000) 58 #define DRAM_MEM_END (0x100000000) 59 60 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE) 61 #define DRAM_MEM_2_SIZE (SECURE_HEAP_START - DRAM_MEM_2_START) 62 #define DRAM_MEM_3_START (DRAM_MEM_2_START + DRAM_MEM_2_SIZE) 63 #define DRAM_MEM_3_SIZE (SECURE_HEAP_SIZE) 64 #define DRAM_MEM_4_START (DRAM_MEM_3_START + DRAM_MEM_3_SIZE) 65 #define DRAM_MEM_4_SIZE (DRAM_MEM_END - DRAM_MEM_4_START) 66 #endif 67 #endif 68 69 struct xrdc_mrc_config imx8ulp_mrc[] = { 70 { 0, 0, 0x0, 0x30000, {0, 0, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* ROM1 */ 71 { 1, 0, 0x60000000, 0x10000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* Flexspi2 */ 72 { 2, 0, 0x22020000, 0x40000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM2 */ 73 { 3, 0, 0x22010000, 0x10000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM0 */ 74 #if defined(SPD_opteed) || defined(SPD_trusty) 75 { 4, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 76 { 4, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfc0, 0} }, /* TEE DRAM for A35, DMA1, USDHC0*/ 77 { 4, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 78 #ifdef SPD_trusty 79 { 4, 3, DRAM_MEM_3_START, DRAM_MEM_3_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfc0, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 80 { 4, 4, DRAM_MEM_4_START, DRAM_MEM_4_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 81 #endif 82 83 { 5, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 84 { 5, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfc0, 0} }, /* TEE DRAM for NIC_PER */ 85 { 5, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 86 #ifdef SPD_trusty 87 { 5, 3, DRAM_MEM_3_START, DRAM_MEM_3_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfc0, 0} }, /* DRAM for NIC_PER */ 88 { 5, 4, DRAM_MEM_4_START, DRAM_MEM_4_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 89 #endif 90 91 #ifdef SPD_trusty 92 { 6, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {1, 1, 0, 2, 1, 0, 1, 1}, {0xfff, 0x93f} }, /* DRAM for LPAV and RTD*/ 93 { 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfc0, 0} }, /* TEE DRAM for LPAV and RTD*/ 94 { 6, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {1, 1, 0, 2, 1, 0, 1, 1}, {0xfff, 0x93f} }, /* DRAM for LPAV and RTD*/ 95 { 6, 3, DRAM_MEM_3_START, DRAM_MEM_3_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfc0, 0} }, /* DRAM for LPAV and RTD*/ 96 { 6, 4, DRAM_MEM_4_START, DRAM_MEM_4_SIZE, {1, 1, 0, 2, 1, 0, 1, 1}, {0xfff, 0x93f} }, /* DRAM for LPAV and RTD*/ 97 #else 98 { 6, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 99 { 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfc0, 0} }, /* TEE DRAM for LPAV and RTD*/ 100 { 6, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 101 #endif 102 #else 103 { 4, 0, 0x80000000, 0x80000000, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 104 { 5, 0, 0x80000000, 0x80000000, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 105 { 6, 0, 0x80000000, 0x80000000, {1, 1, 0, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 106 #endif 107 { 7, 0, 0x80000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 108 { 7, 1, 0x90000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 109 { 8, 0, 0x21000000, 0x10000, {1, 1, 1, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM1 */ 110 { 9, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for HIFI4 */ 111 { 10, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for LPAV */ 112 { 11, 0, 0x21170000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {0xfff, SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 113 { 11, 1, 0x21180000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 114 { 12, 0, 0x2d400000, 0x100000, {0, 0, 0, 0, 0, 0, 0, 1}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), 0} }, /* GIC500 */ 115 }; 116 117 struct xrdc_pac_msc_config imx8ulp_pdac[] = { 118 { 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */ 119 { 0, 44, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC0 slot 44 for CGC1 */ 120 { 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */ 121 { 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */ 122 { 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */ 123 { 1, 0, {0, 7, 7, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */ 124 { 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */ 125 { 1, 7, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 7 for LPUART7 */ 126 { 1, 9, {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */ 127 { 1, 12, {0, 7, 7, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */ 128 { 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */ 129 }; 130 131 struct xrdc_pac_msc_config imx8ulp_msc[] = { 132 { 0, 0, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOE */ 133 { 0, 1, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOF */ 134 { 1, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC1 GPIOD */ 135 { 2, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC2 GPU3D/2D/DCNANO/DDR registers */ 136 }; 137