1 /*
2 * Copyright 2019 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <stdlib.h>
9 #include <stdint.h>
10 #include <services/std_svc.h>
11 #include <string.h>
12 #include <common/build_message.h>
13 #include <common/debug.h>
14 #include <common/runtime_svc.h>
15 #include <platform_def.h>
16 #include <imx_sip_svc.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <sci/sci.h>
20
21 #if defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
22 /*
23 * Defined in
24 * table 11. ROM event log buffer address location
25 * AN12853 "i.MX ROMs Log Events"
26 */
27 #define ROM_LOG_BUFFER_ADDR 0x9E0
28 #endif
29
30 #if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
31
32 #ifdef PLAT_imx8qm
33 static const int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
34 SC_R_A53, SC_R_A72,
35 };
36 #endif
37
imx_srtc_set_time(uint32_t year_mon,unsigned long day_hour,unsigned long min_sec)38 static int imx_srtc_set_time(uint32_t year_mon,
39 unsigned long day_hour,
40 unsigned long min_sec)
41 {
42 return sc_timer_set_rtc_time(ipc_handle,
43 year_mon >> 16, year_mon & 0xffff,
44 day_hour >> 16, day_hour & 0xffff,
45 min_sec >> 16, min_sec & 0xffff);
46 }
47
imx_srtc_handler(uint32_t smc_fid,void * handle,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4)48 int imx_srtc_handler(uint32_t smc_fid,
49 void *handle,
50 u_register_t x1,
51 u_register_t x2,
52 u_register_t x3,
53 u_register_t x4)
54 {
55 int ret;
56
57 switch (x1) {
58 case IMX_SIP_SRTC_SET_TIME:
59 ret = imx_srtc_set_time(x2, x3, x4);
60 break;
61 default:
62 ret = SMC_UNK;
63 }
64
65 SMC_RET1(handle, ret);
66 }
67
imx_cpufreq_set_target(uint32_t cluster_id,unsigned long freq)68 static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq)
69 {
70 sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
71
72 #ifdef PLAT_imx8qm
73 sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
74 #endif
75 #ifdef PLAT_imx8qx
76 sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
77 #endif
78 }
79
imx_cpufreq_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3)80 int imx_cpufreq_handler(uint32_t smc_fid,
81 u_register_t x1,
82 u_register_t x2,
83 u_register_t x3)
84 {
85 switch (x1) {
86 case IMX_SIP_SET_CPUFREQ:
87 imx_cpufreq_set_target(x2, x3);
88 break;
89 default:
90 return SMC_UNK;
91 }
92
93 return 0;
94 }
95
96 static bool wakeup_src_irqsteer;
97
imx_is_wakeup_src_irqsteer(void)98 bool imx_is_wakeup_src_irqsteer(void)
99 {
100 return wakeup_src_irqsteer;
101 }
102
imx_wakeup_src_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3)103 int imx_wakeup_src_handler(uint32_t smc_fid,
104 u_register_t x1,
105 u_register_t x2,
106 u_register_t x3)
107 {
108 switch (x1) {
109 case IMX_SIP_WAKEUP_SRC_IRQSTEER:
110 wakeup_src_irqsteer = true;
111 break;
112 case IMX_SIP_WAKEUP_SRC_SCU:
113 wakeup_src_irqsteer = false;
114 break;
115 default:
116 return SMC_UNK;
117 }
118
119 return SMC_OK;
120 }
121
imx_otp_handler(uint32_t smc_fid,void * handle,u_register_t x1,u_register_t x2)122 int imx_otp_handler(uint32_t smc_fid,
123 void *handle,
124 u_register_t x1,
125 u_register_t x2)
126 {
127 int ret;
128 uint32_t fuse;
129
130 switch (smc_fid) {
131 case IMX_SIP_OTP_READ:
132 ret = sc_misc_otp_fuse_read(ipc_handle, x1, &fuse);
133 SMC_RET2(handle, ret, fuse);
134 break;
135 case IMX_SIP_OTP_WRITE:
136 ret = sc_misc_otp_fuse_write(ipc_handle, x1, x2);
137 SMC_RET1(handle, ret);
138 break;
139 default:
140 ret = SMC_UNK;
141 SMC_RET1(handle, ret);
142 break;
143 }
144
145 return ret;
146 }
147
imx_misc_set_temp_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4)148 int imx_misc_set_temp_handler(uint32_t smc_fid,
149 u_register_t x1,
150 u_register_t x2,
151 u_register_t x3,
152 u_register_t x4)
153 {
154 return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4);
155 }
156
157 #endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
158
159 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
imx_src_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,void * handle)160 int imx_src_handler(uint32_t smc_fid,
161 u_register_t x1,
162 u_register_t x2,
163 u_register_t x3,
164 void *handle)
165 {
166 uint32_t val;
167
168 switch (x1) {
169 case IMX_SIP_SRC_SET_SECONDARY_BOOT:
170 if (x2 != 0U) {
171 mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
172 SRC_GPR10_PERSIST_SECONDARY_BOOT);
173 } else {
174 mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
175 SRC_GPR10_PERSIST_SECONDARY_BOOT);
176 }
177 break;
178 case IMX_SIP_SRC_IS_SECONDARY_BOOT:
179 val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
180 return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
181 default:
182 return SMC_UNK;
183
184 };
185
186 return 0;
187 }
188 #endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
189
190 #if defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
is_secondary_boot(void)191 static bool is_secondary_boot(void)
192 {
193 uint32_t *rom_log_addr = (uint32_t *)ROM_LOG_BUFFER_ADDR;
194 bool is_secondary = false;
195 uint32_t *rom_log;
196 uint8_t event_id;
197
198 /* If the ROM event log pointer is not valid. */
199 if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xB00000 ||
200 *rom_log_addr & 0x3) {
201 return false;
202 }
203
204 /* Parse the ROM event ID version 2 log */
205 rom_log = (uint32_t *)(uintptr_t)(*rom_log_addr);
206 for (size_t i = 0; i < 128; i++) {
207 event_id = rom_log[i] >> 24;
208 switch (event_id) {
209 case 0x00: /* End of list */
210 return is_secondary;
211 /* Log entries with 1 parameter, skip 1 */
212 case 0x80: /* Perform the device initialization */
213 case 0x81: /* The boot device initialization completes */
214 case 0x82: /* Execute boot device driver pre-config */
215 case 0x8F: /* The boot device initialization fails */
216 case 0x90: /* Start to read data from boot device */
217 case 0x91: /* Reading data from boot device completes */
218 case 0x9F: /* Reading data from boot device fails */
219 i += 1;
220 continue;
221 /* Log entries with 2 parameters, skip 2 */
222 case 0xA0: /* Image authentication result */
223 case 0xC0: /* Jump to the boot image soon */
224 i += 2;
225 continue;
226 /* Booted the primary boot image */
227 case 0x50:
228 is_secondary = false;
229 continue;
230 /* Booted the secondary boot image */
231 case 0x51:
232 is_secondary = true;
233 continue;
234 }
235 }
236
237 return is_secondary;
238 }
239
imx_src_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,void * handle)240 int imx_src_handler(uint32_t smc_fid,
241 u_register_t x1,
242 u_register_t x2,
243 u_register_t x3,
244 void *handle)
245 {
246 switch (x1) {
247 case IMX_SIP_SRC_SET_SECONDARY_BOOT:
248 /* we do support that on these SoCs */
249 break;
250 case IMX_SIP_SRC_IS_SECONDARY_BOOT:
251 return is_secondary_boot();
252 default:
253 return SMC_UNK;
254 };
255
256 return 0;
257 }
258 #endif /* defined(PLAT_imx8mn) || defined(PLAT_imx8mp) */
259
imx_get_commit_hash(u_register_t x2,u_register_t x3,u_register_t x4)260 static uint64_t imx_get_commit_hash(u_register_t x2,
261 u_register_t x3,
262 u_register_t x4)
263 {
264 /* Parse the version_string */
265 char *parse = (char *)build_version_string;
266 uint64_t hash = 0;
267
268 do {
269 parse = strchr(parse, '-');
270 if (parse) {
271 parse += 1;
272 if (*(parse) == 'g') {
273 /* Default is 7 hexadecimal digits */
274 memcpy((void *)&hash, (void *)(parse + 1), 7);
275 break;
276 }
277 }
278
279 } while (parse != NULL);
280
281 return hash;
282 }
283
imx_buildinfo_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4)284 uint64_t imx_buildinfo_handler(uint32_t smc_fid,
285 u_register_t x1,
286 u_register_t x2,
287 u_register_t x3,
288 u_register_t x4)
289 {
290 uint64_t ret;
291
292 switch (x1) {
293 case IMX_SIP_BUILDINFO_GET_COMMITHASH:
294 ret = imx_get_commit_hash(x2, x3, x4);
295 break;
296 default:
297 return SMC_UNK;
298 }
299
300 return ret;
301 }
302
imx_kernel_entry_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4)303 int imx_kernel_entry_handler(uint32_t smc_fid,
304 u_register_t x1,
305 u_register_t x2,
306 u_register_t x3,
307 u_register_t x4)
308 {
309 static entry_point_info_t bl33_image_ep_info;
310 entry_point_info_t *next_image_info;
311 unsigned int mode;
312
313 if (x1 < (PLAT_NS_IMAGE_OFFSET & 0xF0000000))
314 return SMC_UNK;
315
316 mode = MODE32_svc;
317
318 next_image_info = &bl33_image_ep_info;
319
320 next_image_info->pc = x1;
321
322 next_image_info->spsr = SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE,
323 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT));
324
325 next_image_info->args.arg0 = 0;
326 next_image_info->args.arg1 = 0;
327 next_image_info->args.arg2 = x3;
328
329 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
330
331 cm_init_my_context(next_image_info);
332 cm_prepare_el3_exit(NON_SECURE);
333
334 return 0;
335 }
336
337 #if defined(PLAT_imx8ulp)
imx_hifi_xrdc(uint32_t smc_fid)338 int imx_hifi_xrdc(uint32_t smc_fid)
339 {
340 mmio_setbits_32(IMX_SIM2_BASE + 0x8, BIT_32(19) | BIT_32(17) | BIT_32(18));
341 mmio_clrbits_32(IMX_SIM2_BASE + 0x8, BIT_32(16));
342
343 extern int xrdc_apply_hifi_config(void);
344 xrdc_apply_hifi_config();
345
346 return 0;
347 }
348 #endif
349