1/*
2 * Copyright (c) 2023, Aspeed Technology Inc.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <assert_macros.S>
9#include <arch.h>
10#include <cortex_a35.h>
11#include <platform_def.h>
12
13	.globl	platform_mem_init
14	.globl	plat_is_my_cpu_primary
15	.globl	plat_my_core_pos
16	.globl	plat_secondary_cold_boot_setup
17	.globl	plat_get_syscnt_freq2
18	.globl	plat_crash_console_init
19	.globl	plat_crash_console_putc
20	.globl	plat_crash_console_flush
21
22/* void platform_mem_init(void); */
23func platform_mem_init
24	/* DRAM init. is done by preceding MCU */
25	ret
26endfunc platform_mem_init
27
28/* unsigned int plat_is_my_cpu_primary(void); */
29func plat_is_my_cpu_primary
30	mrs	x0, mpidr_el1
31	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
32	cmp	x0, #PLATFORM_CORE_PRIMARY
33	cset	w0, eq
34	ret
35endfunc plat_is_my_cpu_primary
36
37/* unsigned int plat_my_core_pos(void); */
38func plat_my_core_pos
39	mrs	x0, mpidr_el1
40	mov	x2, #PLATFORM_CORE_COUNT_PER_CLUSTER
41	and	x1, x0, #MPIDR_CPU_MASK
42	and	x0, x0, #MPIDR_CLUSTER_MASK
43	madd	x0, x0, x2, x1
44	ret
45endfunc plat_my_core_pos
46
47/* void plat_secondary_cold_boot_setup (void); */
48func plat_secondary_cold_boot_setup
49	mov	x0, xzr
50	bl	plat_my_core_pos
51	mov_imm	x1, SCU_CPU_SMP_EP0
52	add	x1, x1, x0, lsl #3
53
54poll_smp_mbox_go:
55	wfe
56	ldr	x0, [x1]
57	cmp	x0, xzr
58	beq	poll_smp_mbox_go
59	br	x0
60endfunc plat_secondary_cold_boot_setup
61
62/* unsigned int plat_get_syscnt_freq2(void); */
63func plat_get_syscnt_freq2
64	mov_imm	w0, PLAT_SYSCNT_CLKIN_HZ
65	ret
66endfunc plat_get_syscnt_freq2
67
68/* int plat_crash_console_init(void); */
69func plat_crash_console_init
70	mov_imm	x0, CONSOLE_UART_BASE
71	mov_imm	x1, CONSOLE_UART_CLKIN_HZ
72	mov_imm	x2, CONSOLE_UART_BAUDRATE
73	b	console_16550_core_init
74endfunc plat_crash_console_init
75
76/* int plat_crash_console_putc(int); */
77func plat_crash_console_putc
78	mov_imm	x1, CONSOLE_UART_BASE
79	b	console_16550_core_putc
80endfunc plat_crash_console_putc
81
82/* void plat_crash_console_flush(void); */
83func plat_crash_console_flush
84	mov_imm	x0, CONSOLE_UART_BASE
85	b	console_16550_core_flush
86endfunc plat_crash_console_flush
87