1 /*
2 * Copyright (c) 2023, Aspeed Technology Inc.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch.h>
8 #include <common/debug.h>
9 #include <common/desc_image_load.h>
10 #include <drivers/arm/gicv3.h>
11 #include <drivers/console.h>
12 #include <drivers/ti/uart/uart_16550.h>
13 #include <lib/mmio.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 #include <plat/common/platform.h>
16 #include <platform_def.h>
17
18 static console_t console;
19
20 static entry_point_info_t bl32_ep_info;
21 static entry_point_info_t bl33_ep_info;
22
23 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
24
plat_mpidr_to_core_pos(u_register_t mpidr)25 static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr)
26 {
27 /* to workaround the return type mismatch */
28 return plat_core_pos_by_mpidr(mpidr);
29 }
30
31 static const gicv3_driver_data_t plat_gic_data = {
32 .gicd_base = GICD_BASE,
33 .gicr_base = GICR_BASE,
34 .rdistif_num = PLATFORM_CORE_COUNT,
35 .rdistif_base_addrs = rdistif_base_addrs,
36 .mpidr_to_core_pos = plat_mpidr_to_core_pos,
37 };
38
39 static const mmap_region_t plat_mmap[] = {
40 MAP_REGION_FLAT(GICD_BASE, GICD_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(GICR_BASE, GICR_SIZE,
43 MT_DEVICE | MT_RW | MT_SECURE),
44 MAP_REGION_FLAT(UART_BASE, PAGE_SIZE,
45 MT_DEVICE | MT_RW | MT_SECURE),
46 MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE,
47 MT_DEVICE | MT_RW | MT_SECURE),
48 { 0 }
49 };
50
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)51 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
52 u_register_t arg2, u_register_t arg3)
53 {
54 console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ,
55 CONSOLE_UART_BAUDRATE, &console);
56
57 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
58
59 SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_2, 0);
60 bl32_ep_info.pc = BL32_BASE;
61 SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE);
62
63 SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_2, 0);
64 bl33_ep_info.pc = mmio_read_64(SCU_CPU_SMP_EP0);
65 bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
66 SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE);
67 }
68
bl31_plat_arch_setup(void)69 void bl31_plat_arch_setup(void)
70 {
71 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
72 BL_CODE_END - BL_CODE_BASE,
73 MT_CODE | MT_SECURE);
74
75 mmap_add_region(BL_CODE_END, BL_CODE_END,
76 BL_END - BL_CODE_END,
77 MT_RW_DATA | MT_SECURE);
78
79 #if USE_COHERENT_MEM
80 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
81 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
82 MT_DEVICE | MT_RW | MT_SECURE);
83 #endif
84
85 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE,
86 MT_MEMORY | MT_RW);
87
88 mmap_add(plat_mmap);
89
90 init_xlat_tables();
91
92 enable_mmu_el3(0);
93 }
94
bl31_platform_setup(void)95 void bl31_platform_setup(void)
96 {
97 gicv3_driver_init(&plat_gic_data);
98 gicv3_distif_init();
99 gicv3_rdistif_init(plat_my_core_pos());
100 gicv3_cpuif_enable(plat_my_core_pos());
101 }
102
bl31_plat_get_next_image_ep_info(uint32_t type)103 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
104 {
105 entry_point_info_t *ep_info;
106
107 ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
108
109 if (!ep_info->pc) {
110 return NULL;
111 }
112
113 return ep_info;
114 }
115