1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <lib/psci/psci.h> 13 #include <plat/arm/common/plat_arm.h> 14 #include <plat/common/platform.h> 15 16 /* Allow ARM Standard platforms to override these functions */ 17 #pragma weak plat_arm_program_trusted_mailbox 18 19 #if !ARM_RECOM_STATE_ID_ENC 20 /******************************************************************************* 21 * ARM standard platform handler called to check the validity of the power state 22 * parameter. 23 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)24int arm_validate_power_state(unsigned int power_state, 25 psci_power_state_t *req_state) 26 { 27 unsigned int pstate = psci_get_pstate_type(power_state); 28 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 29 unsigned int i; 30 31 assert(req_state != NULL); 32 33 if (pwr_lvl > PLAT_MAX_PWR_LVL) 34 return PSCI_E_INVALID_PARAMS; 35 36 /* Sanity check the requested state */ 37 if (pstate == PSTATE_TYPE_STANDBY) { 38 /* 39 * It's possible to enter standby only on power level 0 40 * Ignore any other power level. 41 */ 42 if (pwr_lvl != ARM_PWR_LVL0) 43 return PSCI_E_INVALID_PARAMS; 44 45 req_state->pwr_domain_state[ARM_PWR_LVL0] = 46 ARM_LOCAL_STATE_RET; 47 } else { 48 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 49 req_state->pwr_domain_state[i] = 50 ARM_LOCAL_STATE_OFF; 51 } 52 53 /* 54 * We expect the 'state id' to be zero. 55 */ 56 if (psci_get_pstate_id(power_state) != 0U) 57 return PSCI_E_INVALID_PARAMS; 58 59 return PSCI_E_SUCCESS; 60 } 61 62 #else 63 /******************************************************************************* 64 * ARM standard platform handler called to check the validity of the power 65 * state parameter. The power state parameter has to be a composite power 66 * state. 67 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)68int arm_validate_power_state(unsigned int power_state, 69 psci_power_state_t *req_state) 70 { 71 unsigned int state_id; 72 int i; 73 74 assert(req_state != NULL); 75 76 /* 77 * Currently we are using a linear search for finding the matching 78 * entry in the idle power state array. This can be made a binary 79 * search if the number of entries justify the additional complexity. 80 */ 81 for (i = 0; !!arm_pm_idle_states[i]; i++) { 82 if ((power_state & ~ARM_LAST_AT_PLVL_MASK) == 83 arm_pm_idle_states[i]) 84 break; 85 } 86 87 /* Return error if entry not found in the idle state array */ 88 if (!arm_pm_idle_states[i]) 89 return PSCI_E_INVALID_PARAMS; 90 91 i = 0; 92 state_id = psci_get_pstate_id(power_state); 93 94 /* Parse the State ID and populate the state info parameter */ 95 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { 96 req_state->pwr_domain_state[i] = state_id & 97 ARM_LOCAL_PSTATE_MASK; 98 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 99 } 100 #if PSCI_OS_INIT_MODE 101 req_state->last_at_pwrlvl = state_id & ARM_LOCAL_PSTATE_MASK; 102 #endif /* __PSCI_OS_INIT_MODE__ */ 103 104 return PSCI_E_SUCCESS; 105 } 106 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 107 108 /******************************************************************************* 109 * ARM standard platform handler called to check the validity of the non secure 110 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 111 ******************************************************************************/ arm_validate_ns_entrypoint(uintptr_t entrypoint)112int arm_validate_ns_entrypoint(uintptr_t entrypoint) 113 { 114 /* 115 * Check if the non secure entrypoint lies within the non 116 * secure DRAM. 117 */ 118 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 119 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 120 return 0; 121 } 122 #ifdef __aarch64__ 123 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 124 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 125 return 0; 126 } 127 #endif 128 129 return -1; 130 } 131 arm_validate_psci_entrypoint(uintptr_t entrypoint)132int arm_validate_psci_entrypoint(uintptr_t entrypoint) 133 { 134 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : 135 PSCI_E_INVALID_ADDRESS; 136 } 137 138 /****************************************************************************** 139 * Helper function to save the platform state before a system suspend. Save the 140 * state of the system components which are not in the Always ON power domain. 141 *****************************************************************************/ arm_system_pwr_domain_save(void)142void arm_system_pwr_domain_save(void) 143 { 144 /* Assert system power domain is available on the platform */ 145 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 146 147 plat_arm_gic_save(); 148 149 /* 150 * Unregister console now so that it is not registered for a second 151 * time during resume. 152 */ 153 arm_console_runtime_end(); 154 155 /* 156 * All the other peripheral which are configured by ARM TF are 157 * re-initialized on resume from system suspend. Hence we 158 * don't save their state here. 159 */ 160 } 161 162 /****************************************************************************** 163 * Helper function to resume the platform from system suspend. Reinitialize 164 * the system components which are not in the Always ON power domain. 165 * TODO: Unify the platform setup when waking up from cold boot and system 166 * resume in arm_bl31_platform_setup(). 167 *****************************************************************************/ arm_system_pwr_domain_resume(void)168void arm_system_pwr_domain_resume(void) 169 { 170 /* Initialize the console */ 171 arm_console_runtime_init(); 172 173 /* Assert system power domain is available on the platform */ 174 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 175 176 plat_arm_gic_resume(); 177 178 plat_arm_security_setup(); 179 arm_configure_sys_timer(); 180 } 181 182 /******************************************************************************* 183 * ARM platform function to program the mailbox for a cpu before it is released 184 * from reset. This function assumes that the Trusted mail box base is within 185 * the ARM_SHARED_RAM region 186 ******************************************************************************/ plat_arm_program_trusted_mailbox(uintptr_t address)187void plat_arm_program_trusted_mailbox(uintptr_t address) 188 { 189 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 190 191 *mailbox = address; 192 193 /* 194 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 195 * ARM_SHARED_RAM region. 196 */ 197 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 198 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= 199 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 200 } 201 202 /******************************************************************************* 203 * The ARM Standard platform definition of platform porting API 204 * `plat_setup_psci_ops`. 205 ******************************************************************************/ plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)206int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 207 const plat_psci_ops_t **psci_ops) 208 { 209 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 210 211 /* Setup mailbox with entry point. */ 212 plat_arm_program_trusted_mailbox(sec_entrypoint); 213 return 0; 214 } 215