1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <platform_def.h>
9
10 #include <common/debug.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv3.h>
13 #include <lib/utils.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16
17 /******************************************************************************
18 * The following functions are defined as weak to allow a platform to override
19 * the way the GICv3 driver is initialised and used.
20 *****************************************************************************/
21 #pragma weak plat_arm_gic_driver_init
22 #pragma weak plat_arm_gic_init
23 #pragma weak plat_arm_gic_cpuif_enable
24 #pragma weak plat_arm_gic_cpuif_disable
25 #pragma weak plat_arm_gic_pcpu_init
26 #pragma weak plat_arm_gic_redistif_on
27 #pragma weak plat_arm_gic_redistif_off
28
29 /* The GICv3 driver only needs to be initialized in EL3 */
30 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
31
32 /* Default GICR base address to be used for GICR probe. */
33 static const uintptr_t gicr_base_addrs[2] = {
34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
35 0U /* Zero Termination */
36 };
37
38 /* List of zero terminated GICR frame addresses which CPUs will probe */
39 static const uintptr_t *gicr_frames = gicr_base_addrs;
40
41 static const interrupt_prop_t arm_interrupt_props[] = {
42 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
43 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
44 #if ENABLE_FEAT_RAS && FFH_SUPPORT
45 INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
46 GIC_INTR_CFG_LEVEL)
47 #endif
48 };
49
50 /*
51 * We save and restore the GICv3 context on system suspend. Allocate the
52 * data in the designated EL3 Secure carve-out memory. The `used` attribute
53 * is used to prevent the compiler from removing the gicv3 contexts.
54 */
55 static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used;
56 static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used;
57
58 /* Define accessor function to get reference to the GICv3 context */
59 DEFINE_LOAD_SYM_ADDR(rdist_ctx)
DEFINE_LOAD_SYM_ADDR(dist_ctx)60 DEFINE_LOAD_SYM_ADDR(dist_ctx)
61
62 /*
63 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
64 * to core position.
65 *
66 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
67 * values read from GICR_TYPER don't have an MT field. To reuse the same
68 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
69 * that read from GICR_TYPER.
70 *
71 * Assumptions:
72 *
73 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
74 * - No CPUs implemented in the system use affinity level 3.
75 */
76 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
77 {
78 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
79 return plat_arm_calc_core_pos(mpidr);
80 }
81
82 static const gicv3_driver_data_t arm_gic_data __unused = {
83 .gicd_base = PLAT_ARM_GICD_BASE,
84 .gicr_base = 0U,
85 .interrupt_props = arm_interrupt_props,
86 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
87 .rdistif_num = PLATFORM_CORE_COUNT,
88 .rdistif_base_addrs = rdistif_base_addrs,
89 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
90 };
91
92 /*
93 * By default, gicr_frames will be pointing to gicr_base_addrs. If
94 * the platform supports a non-contiguous GICR frames (GICR frames located
95 * at uneven offset), plat_arm_override_gicr_frames function can be used by
96 * such platform to override the gicr_frames.
97 */
plat_arm_override_gicr_frames(const uintptr_t * plat_gicr_frames)98 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames)
99 {
100 assert(plat_gicr_frames != NULL);
101 gicr_frames = plat_gicr_frames;
102 }
103
plat_arm_gic_driver_init(void)104 void __init plat_arm_gic_driver_init(void)
105 {
106 /*
107 * The GICv3 driver is initialized in EL3 and does not need
108 * to be initialized again in SEL1. This is because the S-EL1
109 * can use GIC system registers to manage interrupts and does
110 * not need GIC interface base addresses to be configured.
111 */
112 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
113 (defined(__aarch64__) && defined(IMAGE_BL31))
114 gicv3_driver_init(&arm_gic_data);
115
116 if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
117 ERROR("No GICR base frame found for Primary CPU\n");
118 panic();
119 }
120 #endif
121 }
122
123 /******************************************************************************
124 * ARM common helper to initialize the GIC. Only invoked by BL31
125 *****************************************************************************/
plat_arm_gic_init(void)126 void __init plat_arm_gic_init(void)
127 {
128 gicv3_distif_init();
129 gicv3_rdistif_init(plat_my_core_pos());
130 gicv3_cpuif_enable(plat_my_core_pos());
131 }
132
133 /******************************************************************************
134 * ARM common helper to enable the GIC CPU interface
135 *****************************************************************************/
plat_arm_gic_cpuif_enable(void)136 void plat_arm_gic_cpuif_enable(void)
137 {
138 gicv3_cpuif_enable(plat_my_core_pos());
139 }
140
141 /******************************************************************************
142 * ARM common helper to disable the GIC CPU interface
143 *****************************************************************************/
plat_arm_gic_cpuif_disable(void)144 void plat_arm_gic_cpuif_disable(void)
145 {
146 gicv3_cpuif_disable(plat_my_core_pos());
147 }
148
149 /******************************************************************************
150 * ARM common helper function to iterate over all GICR frames and discover the
151 * corresponding per-cpu redistributor frame as well as initialize the
152 * corresponding interface in GICv3.
153 *****************************************************************************/
plat_arm_gic_pcpu_init(void)154 void plat_arm_gic_pcpu_init(void)
155 {
156 int result;
157 const uintptr_t *plat_gicr_frames = gicr_frames;
158
159 do {
160 result = gicv3_rdistif_probe(*plat_gicr_frames);
161
162 /* If the probe is successful, no need to proceed further */
163 if (result == 0)
164 break;
165
166 plat_gicr_frames++;
167 } while (*plat_gicr_frames != 0U);
168
169 if (result == -1) {
170 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
171 panic();
172 }
173 gicv3_rdistif_init(plat_my_core_pos());
174 }
175
176 /******************************************************************************
177 * ARM common helpers to power GIC redistributor interface
178 *****************************************************************************/
plat_arm_gic_redistif_on(void)179 void plat_arm_gic_redistif_on(void)
180 {
181 gicv3_rdistif_on(plat_my_core_pos());
182 }
183
plat_arm_gic_redistif_off(void)184 void plat_arm_gic_redistif_off(void)
185 {
186 gicv3_rdistif_off(plat_my_core_pos());
187 }
188
189 /******************************************************************************
190 * ARM common helper to save & restore the GICv3 on resume from system suspend
191 *****************************************************************************/
plat_arm_gic_save(void)192 void plat_arm_gic_save(void)
193 {
194 gicv3_redist_ctx_t * const rdist_context =
195 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
196 gicv3_dist_ctx_t * const dist_context =
197 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
198
199 /*
200 * If an ITS is available, save its context before
201 * the Redistributor using:
202 * gicv3_its_save_disable(gits_base, &its_ctx[i])
203 * Additionally, an implementation-defined sequence may
204 * be required to save the whole ITS state.
205 */
206
207 /*
208 * Save the GIC Redistributors and ITS contexts before the
209 * Distributor context. As we only handle SYSTEM SUSPEND API,
210 * we only need to save the context of the CPU that is issuing
211 * the SYSTEM SUSPEND call, i.e. the current CPU.
212 */
213 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
214
215 /* Save the GIC Distributor context */
216 gicv3_distif_save(dist_context);
217
218 /*
219 * From here, all the components of the GIC can be safely powered down
220 * as long as there is an alternate way to handle wakeup interrupt
221 * sources.
222 */
223 }
224
plat_arm_gic_resume(void)225 void plat_arm_gic_resume(void)
226 {
227 const gicv3_redist_ctx_t *rdist_context =
228 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
229 const gicv3_dist_ctx_t *dist_context =
230 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
231
232 /* Restore the GIC Distributor context */
233 gicv3_distif_init_restore(dist_context);
234
235 /*
236 * Restore the GIC Redistributor and ITS contexts after the
237 * Distributor context. As we only handle SYSTEM SUSPEND API,
238 * we only need to restore the context of the CPU that issued
239 * the SYSTEM SUSPEND call.
240 */
241 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
242
243 /*
244 * If an ITS is available, restore its context after
245 * the Redistributor using:
246 * gicv3_its_restore(gits_base, &its_ctx[i])
247 * An implementation-defined sequence may be required to
248 * restore the whole ITS state. The ITS must also be
249 * re-enabled after this sequence has been executed.
250 */
251 }
252