1 /*
2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <plat/arm/common/plat_arm.h>
8 #include <plat/arm/css/common/css_pm.h>
9 #include <platform_def.h>
10
11 /******************************************************************************
12 * The power domain tree descriptor.
13 ******************************************************************************/
14 const unsigned char tc_pd_tree_desc[] = {
15 PLAT_ARM_CLUSTER_COUNT,
16 PLAT_MAX_CPUS_PER_CLUSTER,
17 };
18
19 /*******************************************************************************
20 * This function returns the topology tree information.
21 ******************************************************************************/
plat_get_power_domain_tree_desc(void)22 const unsigned char *plat_get_power_domain_tree_desc(void)
23 {
24 return tc_pd_tree_desc;
25 }
26
27 /*******************************************************************************
28 * The array mapping platform core position (implemented by plat_my_core_pos())
29 * to the SCMI power domain ID implemented by SCP.
30 ******************************************************************************/
31 const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
32 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
33 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
34 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
35 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
36 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
37 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
38 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
39 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
40 #if PLATFORM_CORE_COUNT == 14
41 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
42 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
43 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
44 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
45 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
46 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
47 #endif /* PLATFORM_CORE_COUNT == 14 */
48 };
49
50 /*******************************************************************************
51 * This function returns the core count within the cluster corresponding to
52 * `mpidr`.
53 ******************************************************************************/
plat_arm_get_cluster_core_count(u_register_t mpidr)54 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
55 {
56 return PLAT_MAX_CPUS_PER_CLUSTER;
57 }
58
59 #if ARM_PLAT_MT
60 /******************************************************************************
61 * Return the number of PE's supported by the CPU.
62 *****************************************************************************/
plat_arm_get_cpu_pe_count(u_register_t mpidr)63 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
64 {
65 return PLAT_MAX_PE_PER_CPU;
66 }
67 #endif
68
69 /******************************************************************************
70 * Return the cluster ID of current CPU
71 *****************************************************************************/
plat_cluster_id_by_mpidr(u_register_t mpidr)72 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr)
73 {
74 return MPIDR_AFFLVL2_VAL(mpidr);
75 }
76