1 /*
2 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <plat/common/platform.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/arm/ccn.h>
15 #include <drivers/arm/css/sds.h>
16 #include <lib/utils_def.h>
17 #include <plat/arm/common/plat_arm.h>
18 #include <plat/common/platform.h>
19 #include <drivers/arm/sbsa.h>
20
21 #if SPM_MM
22 #include <services/spm_mm_partition.h>
23 #endif
24
25 /*
26 * Table of regions for different BL stages to map using the MMU.
27 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
28 * arm_configure_mmu_elx() will give the available subset of that.
29 */
30 #if IMAGE_BL1
31 const mmap_region_t plat_arm_mmap[] = {
32 ARM_MAP_SHARED_RAM,
33 TC_MAP_NS_DRAM1,
34 TC_FLASH0_RO,
35 TC_MAP_DEVICE,
36 {0}
37 };
38 #endif
39 #if IMAGE_BL2
40 const mmap_region_t plat_arm_mmap[] = {
41 ARM_MAP_SHARED_RAM,
42 TC_FLASH0_RO,
43 TC_MAP_DEVICE,
44 TC_MAP_NS_DRAM1,
45 #if defined(SPD_spmd)
46 TC_MAP_TZC_DRAM1,
47 #endif
48 #if ARM_BL31_IN_DRAM
49 ARM_MAP_BL31_SEC_DRAM,
50 #endif
51 #if SPM_MM
52 ARM_SP_IMAGE_MMAP,
53 #endif
54 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
55 ARM_MAP_BL1_RW,
56 #endif
57 #ifdef SPD_opteed
58 ARM_MAP_OPTEE_CORE_MEM,
59 ARM_OPTEE_PAGEABLE_LOAD_MEM,
60 #endif
61 {0}
62 };
63 #endif
64 #if IMAGE_BL31
65 const mmap_region_t plat_arm_mmap[] = {
66 ARM_MAP_SHARED_RAM,
67 V2M_MAP_IOFPGA,
68 TC_MAP_DEVICE,
69 PLAT_DTB_DRAM_NS,
70 #if SPM_MM
71 ARM_SPM_BUF_EL3_MMAP,
72 #endif
73 {0}
74 };
75
76 #if SPM_MM && defined(IMAGE_BL31)
77 const mmap_region_t plat_arm_secure_partition_mmap[] = {
78 PLAT_ARM_SECURE_MAP_DEVICE,
79 ARM_SP_IMAGE_MMAP,
80 ARM_SP_IMAGE_NS_BUF_MMAP,
81 ARM_SP_CPER_BUF_MMAP,
82 ARM_SP_IMAGE_RW_MMAP,
83 ARM_SPM_BUF_EL0_MMAP,
84 {0}
85 };
86 #endif /* SPM_MM && defined(IMAGE_BL31) */
87 #endif
88
89 ARM_CASSERT_MMAP
90
91 #if SPM_MM && defined(IMAGE_BL31)
92 /*
93 * Boot information passed to a secure partition during initialisation. Linear
94 * indices in MP information will be filled at runtime.
95 */
96 static spm_mm_mp_info_t sp_mp_info[] = {
97 [0] = {0x81000000, 0},
98 [1] = {0x81000100, 0},
99 [2] = {0x81000200, 0},
100 [3] = {0x81000300, 0},
101 [4] = {0x81010000, 0},
102 [5] = {0x81010100, 0},
103 [6] = {0x81010200, 0},
104 [7] = {0x81010300, 0},
105 };
106
107 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
108 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
109 .h.version = VERSION_1,
110 .h.size = sizeof(spm_mm_boot_info_t),
111 .h.attr = 0,
112 .sp_mem_base = ARM_SP_IMAGE_BASE,
113 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
114 .sp_image_base = ARM_SP_IMAGE_BASE,
115 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
116 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
117 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
118 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
119 .sp_image_size = ARM_SP_IMAGE_SIZE,
120 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
121 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
122 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
123 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
124 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
125 .num_cpus = PLATFORM_CORE_COUNT,
126 .mp_info = &sp_mp_info[0],
127 };
128
plat_get_secure_partition_mmap(void * cookie)129 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
130 {
131 return plat_arm_secure_partition_mmap;
132 }
133
plat_get_secure_partition_boot_info(void * cookie)134 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
135 void *cookie)
136 {
137 return &plat_arm_secure_partition_boot_info;
138 }
139 #endif /* SPM_MM && defined(IMAGE_BL31) */
140
141 #if TRUSTED_BOARD_BOOT || MEASURED_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)142 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
143 {
144 assert(heap_addr != NULL);
145 assert(heap_size != NULL);
146
147 return arm_get_mbedtls_heap(heap_addr, heap_size);
148 }
149 #endif
150
plat_arm_secure_wdt_start(void)151 void plat_arm_secure_wdt_start(void)
152 {
153 sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT);
154 }
155
plat_arm_secure_wdt_stop(void)156 void plat_arm_secure_wdt_stop(void)
157 {
158 sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE);
159 }
160
plat_arm_secure_wdt_refresh(void)161 void plat_arm_secure_wdt_refresh(void)
162 {
163 sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE);
164 }
165
166 static sds_region_desc_t tc_sds_regions[] = {
167 { .base = PLAT_ARM_SDS_MEM_BASE },
168 { .base = PLAT_ARM_RSE_AP_SDS_MEM_BASE },
169 };
170
plat_sds_get_regions(unsigned int * region_count)171 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
172 {
173 *region_count = ARRAY_SIZE(tc_sds_regions);
174
175 return tc_sds_regions;
176 }
177