1#
2# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7
8N1SDP_BASE		:=	plat/arm/board/n1sdp
9
10INTERCONNECT_SOURCES	:=	${N1SDP_BASE}/n1sdp_interconnect.c
11
12PLAT_INCLUDES		:=	-I${N1SDP_BASE}/include
13
14
15N1SDP_CPU_SOURCES	:=	lib/cpus/aarch64/neoverse_n1.S
16
17# Neoverse N1 cores support Armv8.2 extensions
18ARM_ARCH_MAJOR := 8
19ARM_ARCH_MINOR := 2
20
21# GIC-600 configuration
22GICV3_SUPPORT_GIC600		:=	1
23GICV3_IMPL_GIC600_MULTICHIP	:=	1
24
25# Include GICv3 driver files
26include drivers/arm/gic/v3/gicv3.mk
27
28N1SDP_GIC_SOURCES	:=	${GICV3_SOURCES}			\
29				plat/common/plat_gicv3.c		\
30				plat/arm/common/arm_gicv3.c		\
31
32PLAT_BL_COMMON_SOURCES	:=	${N1SDP_BASE}/n1sdp_plat.c	        \
33				${N1SDP_BASE}/aarch64/n1sdp_helper.S
34
35BL1_SOURCES		:=	${N1SDP_CPU_SOURCES}                \
36				${INTERCONNECT_SOURCES}             \
37				${N1SDP_BASE}/n1sdp_err.c           \
38				${N1SDP_BASE}/n1sdp_trusted_boot.c  \
39				${N1SDP_BASE}/n1sdp_bl1_setup.c     \
40				drivers/arm/sbsa/sbsa.c
41
42BL2_SOURCES		:=	${N1SDP_BASE}/n1sdp_security.c      \
43				${N1SDP_BASE}/n1sdp_err.c           \
44				${N1SDP_BASE}/n1sdp_trusted_boot.c  \
45				lib/utils/mem_region.c              \
46				${N1SDP_BASE}/n1sdp_bl2_setup.c     \
47				${N1SDP_BASE}/n1sdp_image_load.c     \
48				drivers/arm/css/sds/sds.c
49
50BL31_SOURCES		:=	${N1SDP_CPU_SOURCES}			\
51				${INTERCONNECT_SOURCES}			\
52				${N1SDP_GIC_SOURCES}			\
53				${N1SDP_BASE}/n1sdp_bl31_setup.c	\
54				${N1SDP_BASE}/n1sdp_pm.c		\
55				${N1SDP_BASE}/n1sdp_topology.c	        \
56				${N1SDP_BASE}/n1sdp_security.c		\
57				drivers/arm/css/sds/sds.c
58
59FDT_SOURCES		+=	fdts/${PLAT}-single-chip.dts	\
60				fdts/${PLAT}-multi-chip.dts	\
61				${N1SDP_BASE}/fdts/n1sdp_fw_config.dts	\
62				${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts	\
63				${N1SDP_BASE}/fdts/n1sdp_nt_fw_config.dts
64
65FW_CONFIG		:=	${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb
66TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb
67NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/n1sdp_nt_fw_config.dtb
68
69# Add the FW_CONFIG to FIP and specify the same to certtool
70$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
71# Add the TB_FW_CONFIG to FIP and specify the same to certtool
72$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
73# Add the NT_FW_CONFIG to FIP and specify the same to certtool
74$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
75
76N1SDP_SPMC_MANIFEST_DTS	:=	${N1SDP_BASE}/fdts/${PLAT}_optee_spmc_manifest.dts
77FDT_SOURCES		+=	${N1SDP_SPMC_MANIFEST_DTS}
78N1SDP_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/${PLAT}_optee_spmc_manifest.dtb
79
80# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
81$(eval $(call TOOL_ADD_PAYLOAD,${N1SDP_TOS_FW_CONFIG},--tos-fw-config,${N1SDP_TOS_FW_CONFIG}))
82
83# Setting to 0 as no NVCTR in N1SDP
84N1SDP_FW_NVCTR_VAL	:=	0
85TFW_NVCTR_VAL		:=	${N1SDP_FW_NVCTR_VAL}
86NTFW_NVCTR_VAL		:=	${N1SDP_FW_NVCTR_VAL}
87
88# Add N1SDP_FW_NVCTR_VAL
89$(eval $(call add_define,N1SDP_FW_NVCTR_VAL))
90
91# TF-A not required to load the SCP Images
92override CSS_LOAD_SCP_IMAGES	  	:=	0
93
94override NEED_BL2U		  	:=	no
95
96# 32 bit mode not supported
97override CTX_INCLUDE_AARCH32_REGS 	:=	0
98
99override ARM_PLAT_MT              	:=	1
100
101# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
102# SCP during power management operations and for SCP RAM Firmware transfer.
103CSS_USE_SCMI_SDS_DRIVER		  	:=	1
104
105# System coherency is managed in hardware
106HW_ASSISTED_COHERENCY			:=	1
107
108# When building for systems with hardware-assisted coherency, there's no need to
109# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
110USE_COHERENT_MEM			:=	0
111
112# Enable the flag since N1SDP has a system level cache
113NEOVERSE_Nx_EXTERNAL_LLC		:=	1
114include plat/arm/common/arm_common.mk
115include plat/arm/css/common/css_common.mk
116include plat/arm/board/common/board_common.mk
117