1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Include GICv2 driver files 10include drivers/arm/gic/v2/gicv2.mk 11 12JUNO_GIC_SOURCES := ${GICV2_SOURCES} \ 13 plat/common/plat_gicv2.c \ 14 plat/arm/common/arm_gicv2.c 15 16JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 17 plat/arm/common/arm_cci.c 18 19JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 20 plat/arm/board/juno/juno_security.c \ 21 plat/arm/board/juno/juno_trng.c \ 22 plat/arm/common/arm_tzc400.c 23 24ifneq (${ENABLE_STACK_PROTECTOR}, 0) 25JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 26endif 27 28# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 29# SCP during power management operations and for SCP RAM Firmware transfer. 30CSS_USE_SCMI_SDS_DRIVER := 1 31 32PLAT_INCLUDES := -Iplat/arm/board/juno/include 33 34PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 35 plat/arm/board/juno/juno_common.c 36 37# Flag to enable support for AArch32 state on JUNO 38JUNO_AARCH32_EL3_RUNTIME := 0 39$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 40$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 41 42# Flag to enable support for TZMP1 on JUNO 43JUNO_TZMP1 := 0 44$(eval $(call assert_boolean,JUNO_TZMP1)) 45ifeq (${JUNO_TZMP1}, 1) 46 ifeq (${ETHOSN_NPU_TZMP1},1) 47 $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) 48 else 49 $(eval $(call add_define,JUNO_TZMP1)) 50 endif 51endif 52 53TRNG_SUPPORT := 1 54 55ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 56# Include BL32 in FIP 57NEED_BL32 := yes 58# BL31 is not required 59override BL31_SOURCES = 60 61# The BL32 needs to be built separately invoking the AARCH32 compiler and 62# be specifed via `BL32` build option. 63 ifneq (${ARCH}, aarch32) 64 override BL32_SOURCES = 65 endif 66else 67 ifeq (${ARCH}, aarch32) 68 $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) 69 endif 70endif 71 72ifeq (${ARCH},aarch64) 73BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 74 lib/cpus/aarch64/cortex_a57.S \ 75 lib/cpus/aarch64/cortex_a72.S \ 76 plat/arm/board/juno/juno_err.c \ 77 plat/arm/board/juno/juno_bl1_setup.c \ 78 drivers/arm/sp805/sp805.c \ 79 ${JUNO_INTERCONNECT_SOURCES} \ 80 ${JUNO_SECURITY_SOURCES} 81 82BL2_SOURCES += drivers/arm/sp805/sp805.c \ 83 lib/utils/mem_region.c \ 84 plat/arm/board/juno/juno_err.c \ 85 plat/arm/board/juno/juno_bl2_setup.c \ 86 plat/arm/common/arm_nor_psci_mem_protect.c \ 87 ${JUNO_SECURITY_SOURCES} 88 89BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 90 91BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 92 lib/cpus/aarch64/cortex_a53.S \ 93 lib/cpus/aarch64/cortex_a57.S \ 94 lib/cpus/aarch64/cortex_a72.S \ 95 lib/utils/mem_region.c \ 96 lib/fconf/fconf.c \ 97 lib/fconf/fconf_dyn_cfg_getter.c \ 98 plat/arm/board/juno/juno_bl31_setup.c \ 99 plat/arm/board/juno/juno_pm.c \ 100 plat/arm/board/juno/juno_topology.c \ 101 plat/arm/common/arm_nor_psci_mem_protect.c \ 102 ${JUNO_GIC_SOURCES} \ 103 ${JUNO_INTERCONNECT_SOURCES} \ 104 ${JUNO_SECURITY_SOURCES} 105 106BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 107 108ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 109BL1_SOURCES += drivers/arm/css/sds/sds.c 110endif 111 112ifeq (${TRUSTED_BOARD_BOOT}, 1) 113 # Enable Juno specific TBBR images 114 $(eval $(call add_define,PLAT_TBBR_IMG_DEF)) 115 DTC_CPPFLAGS += ${PLAT_INCLUDES} 116 117 BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 118 BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 119 120 ifeq (${COT_DESC_IN_DTB},0) 121 BL2_SOURCES += plat/arm/board/juno/juno_tbbr_cot_bl2.c 122 endif 123endif 124 125endif 126 127ifneq (${RESET_TO_BL31},0) 128 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 129 Please set RESET_TO_BL31 to 0.") 130endif 131 132ifeq ($(USE_ROMLIB),1) 133all : bl1_romlib.bin 134endif 135 136bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin 137 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 138 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 139 140# Errata workarounds for Cortex-A53: 141ERRATA_A53_819472 := 1 142ERRATA_A53_824069 := 1 143ERRATA_A53_826319 := 1 144ERRATA_A53_827319 := 1 145ERRATA_A53_835769 := 1 146ERRATA_A53_836870 := 1 147ERRATA_A53_843419 := 1 148ERRATA_A53_855873 := 1 149 150# Errata workarounds for Cortex-A57: 151ERRATA_A57_806969 := 0 152ERRATA_A57_813419 := 1 153ERRATA_A57_813420 := 1 154ERRATA_A57_814670 := 1 155ERRATA_A57_817169 := 1 156ERRATA_A57_826974 := 1 157ERRATA_A57_826977 := 1 158ERRATA_A57_828024 := 1 159ERRATA_A57_829520 := 1 160ERRATA_A57_833471 := 1 161ERRATA_A57_859972 := 0 162 163# Errata workarounds for Cortex-A72: 164ERRATA_A72_859971 := 0 165 166# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 167# power down sequence 168SKIP_A57_L1_FLUSH_PWR_DWN := 1 169 170# Do not enable SVE 171ENABLE_SVE_FOR_NS := 0 172 173# Enable the dynamic translation tables library. 174ifeq (${ARCH},aarch32) 175 ifeq (${RESET_TO_SP_MIN},1) 176 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 177 endif 178else 179 ifeq (${RESET_TO_BL31},1) 180 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 181 endif 182endif 183 184ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 185 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 186 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 187 else 188 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 189 endif 190endif 191 192BL1_CPPFLAGS += -march=armv8-a+crc 193BL2_CPPFLAGS += -march=armv8-a+crc 194BL2U_CPPFLAGS += -march=armv8-a+crc 195BL31_CPPFLAGS += -march=armv8-a+crc 196BL32_CPPFLAGS += -march=armv8-a+crc 197 198# Add the FDT_SOURCES and options for Dynamic Config 199FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 200 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 201 fdts/${PLAT}.dts 202 203FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 204TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 205HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 206 207# Add the FW_CONFIG to FIP and specify the same to certtool 208$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 209# Add the TB_FW_CONFIG to FIP and specify the same to certtool 210$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 211# Add the HW_CONFIG to FIP and specify the same to certtool 212$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 213 214include drivers/arm/ethosn/ethosn_npu.mk 215include plat/arm/board/common/board_common.mk 216include plat/arm/common/arm_common.mk 217include plat/arm/soc/common/soc_css.mk 218include plat/arm/css/common/css_common.mk 219