1# 2# Copyright (c) 2016-2024, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Debug build 67DEBUG := 0 68 69# By default disable authenticated decryption support. 70DECRYPTION_SUPPORT := none 71 72# Build platform 73DEFAULT_PLAT := fvp 74 75# Disable the generation of the binary image (ELF only). 76DISABLE_BIN_GENERATION := 0 77 78# Enable capability to disable authentication dynamically. Only meant for 79# development platforms. 80DYN_DISABLE_AUTH := 0 81 82# Enable the Maximum Power Mitigation Mechanism on supporting cores. 83ENABLE_MPMM := 0 84 85# Enable MPMM configuration via FCONF. 86ENABLE_MPMM_FCONF := 0 87 88# Flag to Enable Position Independant support (PIE) 89ENABLE_PIE := 0 90 91# Flag to enable Performance Measurement Framework 92ENABLE_PMF := 0 93 94# Flag to enable PSCI STATs functionality 95ENABLE_PSCI_STAT := 0 96 97# Flag to enable runtime instrumentation using PMF 98ENABLE_RUNTIME_INSTRUMENTATION := 0 99 100# Flag to enable stack corruption protection 101ENABLE_STACK_PROTECTOR := 0 102 103# Flag to enable exception handling in EL3 104EL3_EXCEPTION_HANDLING := 0 105 106# By default BL31 encryption disabled 107ENCRYPT_BL31 := 0 108 109# By default BL32 encryption disabled 110ENCRYPT_BL32 := 0 111 112# Default dummy firmware encryption key 113ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 114 115# Default dummy nonce for firmware encryption 116ENC_NONCE := 1234567890abcdef12345678 117 118# Build flag to treat usage of deprecated platform and framework APIs as error. 119ERROR_DEPRECATED := 0 120 121# Fault injection support 122FAULT_INJECTION_SUPPORT := 0 123 124# Flag to enable architectural features detection mechanism 125FEATURE_DETECTION := 0 126 127# Byte alignment that each component in FIP is aligned to 128FIP_ALIGN := 0 129 130# Default FIP file name 131FIP_NAME := fip.bin 132 133# Default FWU_FIP file name 134FWU_FIP_NAME := fwu_fip.bin 135 136# By default firmware encryption with SSK 137FW_ENC_STATUS := 0 138 139# For Chain of Trust 140GENERATE_COT := 0 141 142# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 143# default, they are for Secure EL1. 144GICV2_G0_FOR_EL3 := 0 145 146# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 147# by lower ELs. 148HANDLE_EA_EL3_FIRST_NS := 0 149 150# Enable Handoff protocol using transfer lists 151TRANSFER_LIST := 0 152 153# Enables support for the gcc compiler option "-mharden-sls=all". 154# By default, disables all SLS hardening. 155HARDEN_SLS := 0 156 157# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 158# The default value is sha256. 159HASH_ALG := sha256 160 161# Whether system coherency is managed in hardware, without explicit software 162# operations. 163HW_ASSISTED_COHERENCY := 0 164 165# Flag to enable trapping of implementation defined sytem registers 166IMPDEF_SYSREG_TRAP := 0 167 168# Set the default algorithm for the generation of Trusted Board Boot keys 169KEY_ALG := rsa 170 171# Set the default key size in case KEY_ALG is rsa 172ifeq ($(KEY_ALG),rsa) 173KEY_SIZE := 2048 174endif 175 176# Option to build TF with Measured Boot support 177MEASURED_BOOT := 0 178 179# Option to enable the DICE Protection Environmnet as a Measured Boot backend 180DICE_PROTECTION_ENVIRONMENT :=0 181 182# NS timer register save and restore 183NS_TIMER_SWITCH := 0 184 185# Include lib/libc in the final image 186OVERRIDE_LIBC := 0 187 188# Build PL011 UART driver in minimal generic UART mode 189PL011_GENERIC_UART := 0 190 191# By default, consider that the platform's reset address is not programmable. 192# The platform Makefile is free to override this value. 193PROGRAMMABLE_RESET_ADDRESS := 0 194 195# Flag used to choose the power state format: Extended State-ID or Original 196PSCI_EXTENDED_STATE_ID := 0 197 198# Enable PSCI OS-initiated mode support 199PSCI_OS_INIT_MODE := 0 200 201# By default, BL1 acts as the reset handler, not BL31 202RESET_TO_BL31 := 0 203 204# For Chain of Trust 205SAVE_KEYS := 0 206 207# Software Delegated Exception support 208SDEI_SUPPORT := 0 209 210# True Random Number firmware Interface support 211TRNG_SUPPORT := 0 212 213# Check to see if Errata ABI is supported 214ERRATA_ABI_SUPPORT := 0 215 216# Check to enable Errata ABI for platforms with non-arm interconnect 217ERRATA_NON_ARM_INTERCONNECT := 0 218 219# SMCCC PCI support 220SMC_PCI_SUPPORT := 0 221 222# Whether code and read-only data should be put on separate memory pages. The 223# platform Makefile is free to override this value. 224SEPARATE_CODE_AND_RODATA := 0 225 226# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 227# separate memory region, which may be discontiguous from the rest of BL31. 228SEPARATE_NOBITS_REGION := 0 229 230# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 231# region, platform Makefile is free to override this value. 232SEPARATE_BL2_NOLOAD_REGION := 0 233 234# If the BL31 image initialisation code is recalimed after use for the secondary 235# cores stack 236RECLAIM_INIT_CODE := 0 237 238# SPD choice 239SPD := none 240 241# Enable the Management Mode (MM)-based Secure Partition Manager implementation 242SPM_MM := 0 243 244# Use the FF-A SPMC implementation in EL3. 245SPMC_AT_EL3 := 0 246 247# Enable SEL0 SP when SPMC is enabled at EL3 248SPMC_AT_EL3_SEL0_SP :=0 249 250# Use SPM at S-EL2 as a default config for SPMD 251SPMD_SPM_AT_SEL2 := 1 252 253# Flag to introduce an infinite loop in BL1 just before it exits into the next 254# image. This is meant to help debugging the post-BL2 phase. 255SPIN_ON_BL1_EXIT := 0 256 257# Flags to build TF with Trusted Boot support 258TRUSTED_BOARD_BOOT := 0 259 260# Build option to choose whether Trusted Firmware uses Coherent memory or not. 261USE_COHERENT_MEM := 1 262 263# Build option to add debugfs support 264USE_DEBUGFS := 0 265 266# Build option to fconf based io 267ARM_IO_IN_DTB := 0 268 269# Build option to support SDEI through fconf 270SDEI_IN_FCONF := 0 271 272# Build option to support Secure Interrupt descriptors through fconf 273SEC_INT_DESC_IN_FCONF := 0 274 275# Build option to choose whether Trusted Firmware uses library at ROM 276USE_ROMLIB := 0 277 278# Build option to choose whether the xlat tables of BL images can be read-only. 279# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 280# which is the per BL-image option that actually enables the read-only tables 281# API. The reason for having this additional option is to have a common high 282# level makefile where we can check for incompatible features/build options. 283ALLOW_RO_XLAT_TABLES := 0 284 285# Chain of trust. 286COT := tbbr 287 288# Use tbbr_oid.h instead of platform_oid.h 289USE_TBBR_DEFS := 1 290 291# Build verbosity 292V := 0 293 294# Whether to enable D-Cache early during warm boot. This is usually 295# applicable for platforms wherein interconnect programming is not 296# required to enable cache coherency after warm reset (eg: single cluster 297# platforms). 298WARMBOOT_ENABLE_DCACHE_EARLY := 0 299 300# Default SVE vector length to maximum architected value 301SVE_VECTOR_LEN := 2048 302 303SANITIZE_UB := off 304 305# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 306# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 307# Default: disabled 308USE_SPINLOCK_CAS := 0 309 310# Enable Link Time Optimization 311ENABLE_LTO := 0 312 313# This option will include EL2 registers in cpu context save and restore during 314# EL2 firmware entry/exit. Internal flag not meant for direct setting. 315# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 316# CTX_INCLUDE_EL2_REGS. 317CTX_INCLUDE_EL2_REGS := 0 318 319# Enable Memory tag extension which is supported for architecture greater 320# than Armv8.5-A 321# By default it is set to "no" 322SUPPORT_STACK_MEMTAG := no 323 324# Select workaround for AT speculative behaviour. 325ERRATA_SPECULATIVE_AT := 0 326 327# Trap RAS error record access from Non secure 328RAS_TRAP_NS_ERR_REC_ACCESS := 0 329 330# Build option to create cot descriptors using fconf 331COT_DESC_IN_DTB := 0 332 333# Build option to provide OpenSSL directory path 334OPENSSL_DIR := /usr 335 336# Select the openssl binary provided in OPENSSL_DIR variable 337ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 338 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 339else 340 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 341endif 342 343# Build option to use the SP804 timer instead of the generic one 344USE_SP804_TIMER := 0 345 346# Build option to define number of firmware banks, used in firmware update 347# metadata structure. 348NR_OF_FW_BANKS := 2 349 350# Build option to define number of images in firmware bank, used in firmware 351# update metadata structure. 352NR_OF_IMAGES_IN_FW_BANK := 1 353 354# Disable Firmware update support by default 355PSA_FWU_SUPPORT := 0 356 357# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 358# is enabled. 359ifeq ($(PSA_FWU_SUPPORT),1) 360PSA_FWU_METADATA_FW_STORE_DESC := 1 361else 362PSA_FWU_METADATA_FW_STORE_DESC := 0 363endif 364 365# Dynamic Root of Trust for Measurement support 366DRTM_SUPPORT := 0 367 368# Check platform if cache management operations should be performed. 369# Disabled by default. 370CONDITIONAL_CMO := 0 371 372# By default, disable SPMD Logical partitions 373ENABLE_SPMD_LP := 0 374 375# By default, disable PSA crypto (use MbedTLS legacy crypto API). 376PSA_CRYPTO := 0 377 378# getc() support from the console(s). 379# Disabled by default because it constitutes an attack vector into TF-A. It 380# should only be enabled if there is a use case for it. 381ENABLE_CONSOLE_GETC := 0 382 383# Build option to disable EL2 when it is not used. 384# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 385# functions must be enabled by platforms if they require it. 386# Disabled by default. 387INIT_UNUSED_NS_EL2 := 0 388 389# Disable including MPAM EL2 registers in context by default since currently 390# it's only enabled for NS world 391CTX_INCLUDE_MPAM_REGS := 0 392 393# Enable context memory usage reporting during BL31 setup. 394PLATFORM_REPORT_CTX_MEM_USE := 0 395 396# Enable early console 397EARLY_CONSOLE := 0 398 399# Allow platforms to save/restore DSU PMU registers over a power cycle. 400# Disabled by default and must be enabled by individual platforms. 401PRESERVE_DSU_PMU_REGS := 0 402