1 /*
2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <stdbool.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <arch_features.h>
17 #include <bl31/interrupt_mgmt.h>
18 #include <common/bl_common.h>
19 #include <common/debug.h>
20 #include <context.h>
21 #include <drivers/arm/gicv3.h>
22 #include <lib/el3_runtime/context_mgmt.h>
23 #include <lib/el3_runtime/cpu_data.h>
24 #include <lib/el3_runtime/pubsub_events.h>
25 #include <lib/extensions/amu.h>
26 #include <lib/extensions/brbe.h>
27 #include <lib/extensions/mpam.h>
28 #include <lib/extensions/pmuv3.h>
29 #include <lib/extensions/sme.h>
30 #include <lib/extensions/spe.h>
31 #include <lib/extensions/sve.h>
32 #include <lib/extensions/sys_reg_trace.h>
33 #include <lib/extensions/trbe.h>
34 #include <lib/extensions/trf.h>
35 #include <lib/utils.h>
36
37 #if ENABLE_FEAT_TWED
38 /* Make sure delay value fits within the range(0-15) */
39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
40 #endif /* ENABLE_FEAT_TWED */
41
42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
43 static bool has_secure_perworld_init;
44
45 static void manage_extensions_nonsecure(cpu_context_t *ctx);
46 static void manage_extensions_secure(cpu_context_t *ctx);
47 static void manage_extensions_secure_per_world(void);
48
setup_el1_context(cpu_context_t * ctx,const struct entry_point_info * ep)49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
50 {
51 u_register_t sctlr_elx, actlr_elx;
52
53 /*
54 * Initialise SCTLR_EL1 to the reset value corresponding to the target
55 * execution state setting all fields rather than relying on the hw.
56 * Some fields have architecturally UNKNOWN reset values and these are
57 * set to zero.
58 *
59 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
60 *
61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
62 * required by PSCI specification)
63 */
64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
65 if (GET_RW(ep->spsr) == MODE_RW_64) {
66 sctlr_elx |= SCTLR_EL1_RES1;
67 } else {
68 /*
69 * If the target execution state is AArch32 then the following
70 * fields need to be set.
71 *
72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
73 * instructions are not trapped to EL1.
74 *
75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
76 * instructions are not trapped to EL1.
77 *
78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
79 * CP15DMB, CP15DSB, and CP15ISB instructions.
80 */
81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
83 }
84
85 #if ERRATA_A75_764081
86 /*
87 * If workaround of errata 764081 for Cortex-A75 is used then set
88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
89 */
90 sctlr_elx |= SCTLR_IESB_BIT;
91 #endif
92 /* Store the initialised SCTLR_EL1 value in the cpu_context */
93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
94
95 /*
96 * Base the context ACTLR_EL1 on the current value, as it is
97 * implementation defined. The context restore process will write
98 * the value from the context to the actual register and can cause
99 * problems for processor cores that don't expect certain bits to
100 * be zero.
101 */
102 actlr_elx = read_actlr_el1();
103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
104 }
105
106 /******************************************************************************
107 * This function performs initializations that are specific to SECURE state
108 * and updates the cpu context specified by 'ctx'.
109 *****************************************************************************/
setup_secure_context(cpu_context_t * ctx,const struct entry_point_info * ep)110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
111 {
112 u_register_t scr_el3;
113 el3_state_t *state;
114
115 state = get_el3state_ctx(ctx);
116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
117
118 #if defined(IMAGE_BL31) && !defined(SPD_spmd)
119 /*
120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
121 * indicated by the interrupt routing model for BL31.
122 */
123 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
124 #endif
125
126 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
127 if (is_feat_mte2_supported()) {
128 scr_el3 |= SCR_ATA_BIT;
129 }
130
131 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
132
133 /*
134 * Initialize EL1 context registers unless SPMC is running
135 * at S-EL2.
136 */
137 #if !SPMD_SPM_AT_SEL2
138 setup_el1_context(ctx, ep);
139 #endif
140
141 manage_extensions_secure(ctx);
142
143 /**
144 * manage_extensions_secure_per_world api has to be executed once,
145 * as the registers getting initialised, maintain constant value across
146 * all the cpus for the secure world.
147 * Henceforth, this check ensures that the registers are initialised once
148 * and avoids re-initialization from multiple cores.
149 */
150 if (!has_secure_perworld_init) {
151 manage_extensions_secure_per_world();
152 }
153
154 }
155
156 #if ENABLE_RME
157 /******************************************************************************
158 * This function performs initializations that are specific to REALM state
159 * and updates the cpu context specified by 'ctx'.
160 *****************************************************************************/
setup_realm_context(cpu_context_t * ctx,const struct entry_point_info * ep)161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
162 {
163 u_register_t scr_el3;
164 el3_state_t *state;
165
166 state = get_el3state_ctx(ctx);
167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
168
169 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
170
171 /* CSV2 version 2 and above */
172 if (is_feat_csv2_2_supported()) {
173 /* Enable access to the SCXTNUM_ELx registers. */
174 scr_el3 |= SCR_EnSCXT_BIT;
175 }
176
177 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
178 }
179 #endif /* ENABLE_RME */
180
181 /******************************************************************************
182 * This function performs initializations that are specific to NON-SECURE state
183 * and updates the cpu context specified by 'ctx'.
184 *****************************************************************************/
setup_ns_context(cpu_context_t * ctx,const struct entry_point_info * ep)185 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
186 {
187 u_register_t scr_el3;
188 el3_state_t *state;
189
190 state = get_el3state_ctx(ctx);
191 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
192
193 /* SCR_NS: Set the NS bit */
194 scr_el3 |= SCR_NS_BIT;
195
196 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
197 if (is_feat_mte2_supported()) {
198 scr_el3 |= SCR_ATA_BIT;
199 }
200
201 #if !CTX_INCLUDE_PAUTH_REGS
202 /*
203 * Pointer Authentication feature, if present, is always enabled by default
204 * for Non secure lower exception levels. We do not have an explicit
205 * flag to set it.
206 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
207 * exception levels of secure and realm worlds.
208 *
209 * To prevent the leakage between the worlds during world switch,
210 * we enable it only for the non-secure world.
211 *
212 * If the Secure/realm world wants to use pointer authentication,
213 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
214 * it will be enabled globally for all the contexts.
215 *
216 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
217 * other than EL3
218 *
219 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
220 * than EL3
221 */
222 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
223
224 #endif /* CTX_INCLUDE_PAUTH_REGS */
225
226 #if HANDLE_EA_EL3_FIRST_NS
227 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
228 scr_el3 |= SCR_EA_BIT;
229 #endif
230
231 #if RAS_TRAP_NS_ERR_REC_ACCESS
232 /*
233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
234 * and RAS ERX registers from EL1 and EL2(from any security state)
235 * are trapped to EL3.
236 * Set here to trap only for NS EL1/EL2
237 *
238 */
239 scr_el3 |= SCR_TERR_BIT;
240 #endif
241
242 /* CSV2 version 2 and above */
243 if (is_feat_csv2_2_supported()) {
244 /* Enable access to the SCXTNUM_ELx registers. */
245 scr_el3 |= SCR_EnSCXT_BIT;
246 }
247
248 #ifdef IMAGE_BL31
249 /*
250 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
251 * indicated by the interrupt routing model for BL31.
252 */
253 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
254 #endif
255 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
256
257 /* Initialize EL1 context registers */
258 setup_el1_context(ctx, ep);
259
260 /* Initialize EL2 context registers */
261 #if CTX_INCLUDE_EL2_REGS
262
263 /*
264 * Initialize SCTLR_EL2 context register using Endianness value
265 * taken from the entrypoint attribute.
266 */
267 u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
268 sctlr_el2_val |= SCTLR_EL2_RES1;
269 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val);
270
271
272 if (is_feat_hcx_supported()) {
273 /*
274 * Initialize register HCRX_EL2 with its init value.
275 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
276 * chance that this can lead to unexpected behavior in lower
277 * ELs that have not been updated since the introduction of
278 * this feature if not properly initialized, especially when
279 * it comes to those bits that enable/disable traps.
280 */
281 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2,
282 HCRX_EL2_INIT_VAL);
283 }
284
285 if (is_feat_fgt_supported()) {
286 /*
287 * Initialize HFG*_EL2 registers with a default value so legacy
288 * systems unaware of FEAT_FGT do not get trapped due to their lack
289 * of initialization for this feature.
290 */
291 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2,
292 HFGITR_EL2_INIT_VAL);
293 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2,
294 HFGRTR_EL2_INIT_VAL);
295 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2,
296 HFGWTR_EL2_INIT_VAL);
297 }
298
299 #endif /* CTX_INCLUDE_EL2_REGS */
300
301 manage_extensions_nonsecure(ctx);
302 }
303
304 /*******************************************************************************
305 * The following function performs initialization of the cpu_context 'ctx'
306 * for first use that is common to all security states, and sets the
307 * initial entrypoint state as specified by the entry_point_info structure.
308 *
309 * The EE and ST attributes are used to configure the endianness and secure
310 * timer availability for the new execution context.
311 ******************************************************************************/
setup_context_common(cpu_context_t * ctx,const entry_point_info_t * ep)312 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
313 {
314 u_register_t scr_el3;
315 el3_state_t *state;
316 gp_regs_t *gp_regs;
317
318 state = get_el3state_ctx(ctx);
319
320 /* Clear any residual register values from the context */
321 zeromem(ctx, sizeof(*ctx));
322
323 /*
324 * The lower-EL context is zeroed so that no stale values leak to a world.
325 * It is assumed that an all-zero lower-EL context is good enough for it
326 * to boot correctly. However, there are very few registers where this
327 * is not true and some values need to be recreated.
328 */
329 #if CTX_INCLUDE_EL2_REGS
330 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx);
331
332 /*
333 * These bits are set in the gicv3 driver. Losing them (especially the
334 * SRE bit) is problematic for all worlds. Henceforth recreate them.
335 */
336 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
337 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
338 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
339 #endif /* CTX_INCLUDE_EL2_REGS */
340
341 /* Start with a clean SCR_EL3 copy as all relevant values are set */
342 scr_el3 = SCR_RESET_VAL;
343
344 /*
345 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
346 * EL2, EL1 and EL0 are not trapped to EL3.
347 *
348 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
349 * EL2, EL1 and EL0 are not trapped to EL3.
350 *
351 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
352 * both Security states and both Execution states.
353 *
354 * SCR_EL3.SIF: Set to one to disable secure instruction execution from
355 * Non-secure memory.
356 */
357 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT);
358
359 scr_el3 |= SCR_SIF_BIT;
360
361 /*
362 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
363 * Exception level as specified by SPSR.
364 */
365 if (GET_RW(ep->spsr) == MODE_RW_64) {
366 scr_el3 |= SCR_RW_BIT;
367 }
368
369 /*
370 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
371 * Secure timer registers to EL3, from AArch64 state only, if specified
372 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
373 * bit always behaves as 1 (i.e. secure physical timer register access
374 * is not trapped)
375 */
376 if (EP_GET_ST(ep->h.attr) != 0U) {
377 scr_el3 |= SCR_ST_BIT;
378 }
379
380 /*
381 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
382 * SCR_EL3.HXEn.
383 */
384 if (is_feat_hcx_supported()) {
385 scr_el3 |= SCR_HXEn_BIT;
386 }
387
388 /*
389 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
390 * registers are trapped to EL3.
391 */
392 #if ENABLE_FEAT_RNG_TRAP
393 scr_el3 |= SCR_TRNDR_BIT;
394 #endif
395
396 #if FAULT_INJECTION_SUPPORT
397 /* Enable fault injection from lower ELs */
398 scr_el3 |= SCR_FIEN_BIT;
399 #endif
400
401 #if CTX_INCLUDE_PAUTH_REGS
402 /*
403 * Enable Pointer Authentication globally for all the worlds.
404 *
405 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
406 * other than EL3
407 *
408 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
409 * than EL3
410 */
411 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
412 #endif /* CTX_INCLUDE_PAUTH_REGS */
413
414 /*
415 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present.
416 */
417 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) {
418 scr_el3 |= SCR_TCR2EN_BIT;
419 }
420
421 /*
422 * SCR_EL3.PIEN: Enable permission indirection and overlay
423 * registers for AArch64 if present.
424 */
425 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) {
426 scr_el3 |= SCR_PIEN_BIT;
427 }
428
429 /*
430 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present.
431 */
432 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) {
433 scr_el3 |= SCR_GCSEn_BIT;
434 }
435
436 /*
437 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
438 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
439 * next mode is Hyp.
440 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
441 * same conditions as HVC instructions and when the processor supports
442 * ARMv8.6-FGT.
443 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
444 * CNTPOFF_EL2 register under the same conditions as HVC instructions
445 * and when the processor supports ECV.
446 */
447 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
448 || ((GET_RW(ep->spsr) != MODE_RW_64)
449 && (GET_M32(ep->spsr) == MODE32_hyp))) {
450 scr_el3 |= SCR_HCE_BIT;
451
452 if (is_feat_fgt_supported()) {
453 scr_el3 |= SCR_FGTEN_BIT;
454 }
455
456 if (is_feat_ecv_supported()) {
457 scr_el3 |= SCR_ECVEN_BIT;
458 }
459 }
460
461 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
462 if (is_feat_twed_supported()) {
463 /* Set delay in SCR_EL3 */
464 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
465 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
466 << SCR_TWEDEL_SHIFT);
467
468 /* Enable WFE delay */
469 scr_el3 |= SCR_TWEDEn_BIT;
470 }
471
472 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
473 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */
474 if (is_feat_sel2_supported()) {
475 scr_el3 |= SCR_EEL2_BIT;
476 }
477 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
478
479 /*
480 * Populate EL3 state so that we've the right context
481 * before doing ERET
482 */
483 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
484 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
485 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
486
487 /*
488 * Store the X0-X7 value from the entrypoint into the context
489 * Use memcpy as we are in control of the layout of the structures
490 */
491 gp_regs = get_gpregs_ctx(ctx);
492 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
493 }
494
495 /*******************************************************************************
496 * Context management library initialization routine. This library is used by
497 * runtime services to share pointers to 'cpu_context' structures for secure
498 * non-secure and realm states. Management of the structures and their associated
499 * memory is not done by the context management library e.g. the PSCI service
500 * manages the cpu context used for entry from and exit to the non-secure state.
501 * The Secure payload dispatcher service manages the context(s) corresponding to
502 * the secure state. It also uses this library to get access to the non-secure
503 * state cpu context pointers.
504 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
505 * which will be used for programming an entry into a lower EL. The same context
506 * will be used to save state upon exception entry from that EL.
507 ******************************************************************************/
cm_init(void)508 void __init cm_init(void)
509 {
510 /*
511 * The context management library has only global data to initialize, but
512 * that will be done when the BSS is zeroed out.
513 */
514 }
515
516 /*******************************************************************************
517 * This is the high-level function used to initialize the cpu_context 'ctx' for
518 * first use. It performs initializations that are common to all security states
519 * and initializations specific to the security state specified in 'ep'
520 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)521 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
522 {
523 unsigned int security_state;
524
525 assert(ctx != NULL);
526
527 /*
528 * Perform initializations that are common
529 * to all security states
530 */
531 setup_context_common(ctx, ep);
532
533 security_state = GET_SECURITY_STATE(ep->h.attr);
534
535 /* Perform security state specific initializations */
536 switch (security_state) {
537 case SECURE:
538 setup_secure_context(ctx, ep);
539 break;
540 #if ENABLE_RME
541 case REALM:
542 setup_realm_context(ctx, ep);
543 break;
544 #endif
545 case NON_SECURE:
546 setup_ns_context(ctx, ep);
547 break;
548 default:
549 ERROR("Invalid security state\n");
550 panic();
551 break;
552 }
553 }
554
555 /*******************************************************************************
556 * Enable architecture extensions for EL3 execution. This function only updates
557 * registers in-place which are expected to either never change or be
558 * overwritten by el3_exit.
559 ******************************************************************************/
560 #if IMAGE_BL31
cm_manage_extensions_el3(void)561 void cm_manage_extensions_el3(void)
562 {
563 if (is_feat_spe_supported()) {
564 spe_init_el3();
565 }
566
567 if (is_feat_amu_supported()) {
568 amu_init_el3();
569 }
570
571 if (is_feat_sme_supported()) {
572 sme_init_el3();
573 }
574
575 if (is_feat_trbe_supported()) {
576 trbe_init_el3();
577 }
578
579 if (is_feat_brbe_supported()) {
580 brbe_init_el3();
581 }
582
583 if (is_feat_trf_supported()) {
584 trf_init_el3();
585 }
586
587 pmuv3_init_el3();
588 }
589 #endif /* IMAGE_BL31 */
590
591 /******************************************************************************
592 * Function to initialise the registers with the RESET values in the context
593 * memory, which are maintained per world.
594 ******************************************************************************/
595 #if IMAGE_BL31
cm_el3_arch_init_per_world(per_world_context_t * per_world_ctx)596 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
597 {
598 /*
599 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
600 *
601 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
602 * by Advanced SIMD, floating-point or SVE instructions (if
603 * implemented) do not trap to EL3.
604 *
605 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1,
606 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3.
607 */
608 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT);
609
610 per_world_ctx->ctx_cptr_el3 = cptr_el3;
611
612 /*
613 * Initialize MPAM3_EL3 to its default reset value
614 *
615 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces
616 * all lower ELn MPAM3_EL3 register access to, trap to EL3
617 */
618
619 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
620 }
621 #endif /* IMAGE_BL31 */
622
623 /*******************************************************************************
624 * Initialise per_world_context for Non-Secure world.
625 * This function enables the architecture extensions, which have same value
626 * across the cores for the non-secure world.
627 ******************************************************************************/
628 #if IMAGE_BL31
manage_extensions_nonsecure_per_world(void)629 void manage_extensions_nonsecure_per_world(void)
630 {
631 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
632
633 if (is_feat_sme_supported()) {
634 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
635 }
636
637 if (is_feat_sve_supported()) {
638 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
639 }
640
641 if (is_feat_amu_supported()) {
642 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
643 }
644
645 if (is_feat_sys_reg_trace_supported()) {
646 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
647 }
648
649 if (is_feat_mpam_supported()) {
650 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
651 }
652 }
653 #endif /* IMAGE_BL31 */
654
655 /*******************************************************************************
656 * Initialise per_world_context for Secure world.
657 * This function enables the architecture extensions, which have same value
658 * across the cores for the secure world.
659 ******************************************************************************/
manage_extensions_secure_per_world(void)660 static void manage_extensions_secure_per_world(void)
661 {
662 #if IMAGE_BL31
663 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
664
665 if (is_feat_sme_supported()) {
666
667 if (ENABLE_SME_FOR_SWD) {
668 /*
669 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
670 * SME, SVE, and FPU/SIMD context properly managed.
671 */
672 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
673 } else {
674 /*
675 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
676 * world can safely use the associated registers.
677 */
678 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
679 }
680 }
681 if (is_feat_sve_supported()) {
682 if (ENABLE_SVE_FOR_SWD) {
683 /*
684 * Enable SVE and FPU in secure context, SPM must ensure
685 * that the SVE and FPU register contexts are properly managed.
686 */
687 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
688 } else {
689 /*
690 * Disable SVE and FPU in secure context so non-secure world
691 * can safely use them.
692 */
693 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
694 }
695 }
696
697 /* NS can access this but Secure shouldn't */
698 if (is_feat_sys_reg_trace_supported()) {
699 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
700 }
701
702 has_secure_perworld_init = true;
703 #endif /* IMAGE_BL31 */
704 }
705
706 /*******************************************************************************
707 * Enable architecture extensions on first entry to Non-secure world.
708 ******************************************************************************/
manage_extensions_nonsecure(cpu_context_t * ctx)709 static void manage_extensions_nonsecure(cpu_context_t *ctx)
710 {
711 #if IMAGE_BL31
712 if (is_feat_amu_supported()) {
713 amu_enable(ctx);
714 }
715
716 if (is_feat_sme_supported()) {
717 sme_enable(ctx);
718 }
719
720 pmuv3_enable(ctx);
721 #endif /* IMAGE_BL31 */
722 }
723
724 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */
enable_pauth_el2(void)725 static __unused void enable_pauth_el2(void)
726 {
727 u_register_t hcr_el2 = read_hcr_el2();
728 /*
729 * For Armv8.3 pointer authentication feature, disable traps to EL2 when
730 * accessing key registers or using pointer authentication instructions
731 * from lower ELs.
732 */
733 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
734
735 write_hcr_el2(hcr_el2);
736 }
737
738 #if INIT_UNUSED_NS_EL2
739 /*******************************************************************************
740 * Enable architecture extensions in-place at EL2 on first entry to Non-secure
741 * world when EL2 is empty and unused.
742 ******************************************************************************/
manage_extensions_nonsecure_el2_unused(void)743 static void manage_extensions_nonsecure_el2_unused(void)
744 {
745 #if IMAGE_BL31
746 if (is_feat_spe_supported()) {
747 spe_init_el2_unused();
748 }
749
750 if (is_feat_amu_supported()) {
751 amu_init_el2_unused();
752 }
753
754 if (is_feat_mpam_supported()) {
755 mpam_init_el2_unused();
756 }
757
758 if (is_feat_trbe_supported()) {
759 trbe_init_el2_unused();
760 }
761
762 if (is_feat_sys_reg_trace_supported()) {
763 sys_reg_trace_init_el2_unused();
764 }
765
766 if (is_feat_trf_supported()) {
767 trf_init_el2_unused();
768 }
769
770 pmuv3_init_el2_unused();
771
772 if (is_feat_sve_supported()) {
773 sve_init_el2_unused();
774 }
775
776 if (is_feat_sme_supported()) {
777 sme_init_el2_unused();
778 }
779
780 if (is_feat_hcx_supported()) {
781 write_hcrx_el2(HCRX_EL2_INIT_VAL | HCRX_EL2_MSCEn_BIT);
782 }
783
784 #if ENABLE_PAUTH
785 enable_pauth_el2();
786 #endif /* ENABLE_PAUTH */
787 #endif /* IMAGE_BL31 */
788 }
789 #endif /* INIT_UNUSED_NS_EL2 */
790
791 /*******************************************************************************
792 * Enable architecture extensions on first entry to Secure world.
793 ******************************************************************************/
manage_extensions_secure(cpu_context_t * ctx)794 static void manage_extensions_secure(cpu_context_t *ctx)
795 {
796 #if IMAGE_BL31
797 if (is_feat_sme_supported()) {
798 if (ENABLE_SME_FOR_SWD) {
799 /*
800 * Enable SME, SVE, FPU/SIMD in secure context, secure manager
801 * must ensure SME, SVE, and FPU/SIMD context properly managed.
802 */
803 sme_init_el3();
804 sme_enable(ctx);
805 } else {
806 /*
807 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
808 * world can safely use the associated registers.
809 */
810 sme_disable(ctx);
811 }
812 }
813 #endif /* IMAGE_BL31 */
814 }
815
816 #if !IMAGE_BL1
817 /*******************************************************************************
818 * The following function initializes the cpu_context for a CPU specified by
819 * its `cpu_idx` for first use, and sets the initial entrypoint state as
820 * specified by the entry_point_info structure.
821 ******************************************************************************/
cm_init_context_by_index(unsigned int cpu_idx,const entry_point_info_t * ep)822 void cm_init_context_by_index(unsigned int cpu_idx,
823 const entry_point_info_t *ep)
824 {
825 cpu_context_t *ctx;
826 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
827 cm_setup_context(ctx, ep);
828 }
829 #endif /* !IMAGE_BL1 */
830
831 /*******************************************************************************
832 * The following function initializes the cpu_context for the current CPU
833 * for first use, and sets the initial entrypoint state as specified by the
834 * entry_point_info structure.
835 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)836 void cm_init_my_context(const entry_point_info_t *ep)
837 {
838 cpu_context_t *ctx;
839 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
840 cm_setup_context(ctx, ep);
841 }
842
843 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
init_nonsecure_el2_unused(cpu_context_t * ctx)844 static void init_nonsecure_el2_unused(cpu_context_t *ctx)
845 {
846 #if INIT_UNUSED_NS_EL2
847 u_register_t hcr_el2 = HCR_RESET_VAL;
848 u_register_t mdcr_el2;
849 u_register_t scr_el3;
850
851 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
852
853 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
854 if ((scr_el3 & SCR_RW_BIT) != 0U) {
855 hcr_el2 |= HCR_RW_BIT;
856 }
857
858 write_hcr_el2(hcr_el2);
859
860 /*
861 * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
862 * All fields have architecturally UNKNOWN reset values.
863 */
864 write_cptr_el2(CPTR_EL2_RESET_VAL);
865
866 /*
867 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
868 * reset and are set to zero except for field(s) listed below.
869 *
870 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
871 * Non-secure EL0 and EL1 accesses to the physical timer registers.
872 *
873 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
874 * Non-secure EL0 and EL1 accesses to the physical counter registers.
875 */
876 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
877
878 /*
879 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
880 * UNKNOWN value.
881 */
882 write_cntvoff_el2(0);
883
884 /*
885 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
886 * respectively.
887 */
888 write_vpidr_el2(read_midr_el1());
889 write_vmpidr_el2(read_mpidr_el1());
890
891 /*
892 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
893 *
894 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
895 * translation is disabled, cache maintenance operations depend on the
896 * VMID.
897 *
898 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
899 * disabled.
900 */
901 write_vttbr_el2(VTTBR_RESET_VAL &
902 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
903 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
904
905 /*
906 * Initialise MDCR_EL2, setting all fields rather than relying on hw.
907 * Some fields are architecturally UNKNOWN on reset.
908 *
909 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
910 * register accesses to the Debug ROM registers are not trapped to EL2.
911 *
912 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
913 * accesses to the powerdown debug registers are not trapped to EL2.
914 *
915 * MDCR_EL2.TDA: Set to zero so that System register accesses to the
916 * debug registers do not trap to EL2.
917 *
918 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
919 * EL2.
920 */
921 mdcr_el2 = MDCR_EL2_RESET_VAL &
922 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
923 MDCR_EL2_TDE_BIT);
924
925 write_mdcr_el2(mdcr_el2);
926
927 /*
928 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
929 *
930 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
931 * EL1 accesses to System registers do not trap to EL2.
932 */
933 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
934
935 /*
936 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
937 * reset.
938 *
939 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
940 * and prevent timer interrupts.
941 */
942 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
943
944 manage_extensions_nonsecure_el2_unused();
945 #endif /* INIT_UNUSED_NS_EL2 */
946 }
947
948 /*******************************************************************************
949 * Prepare the CPU system registers for first entry into realm, secure, or
950 * normal world.
951 *
952 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
953 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
954 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
955 * For all entries, the EL1 registers are initialized from the cpu_context
956 ******************************************************************************/
cm_prepare_el3_exit(uint32_t security_state)957 void cm_prepare_el3_exit(uint32_t security_state)
958 {
959 u_register_t sctlr_elx, scr_el3;
960 cpu_context_t *ctx = cm_get_context(security_state);
961
962 assert(ctx != NULL);
963
964 if (security_state == NON_SECURE) {
965 uint64_t el2_implemented = el_implemented(2);
966
967 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
968 CTX_SCR_EL3);
969
970 if (el2_implemented != EL_IMPL_NONE) {
971
972 /*
973 * If context is not being used for EL2, initialize
974 * HCRX_EL2 with its init value here.
975 */
976 if (is_feat_hcx_supported()) {
977 write_hcrx_el2(HCRX_EL2_INIT_VAL);
978 }
979
980 /*
981 * Initialize Fine-grained trap registers introduced
982 * by FEAT_FGT so all traps are initially disabled when
983 * switching to EL2 or a lower EL, preventing undesired
984 * behavior.
985 */
986 if (is_feat_fgt_supported()) {
987 /*
988 * Initialize HFG*_EL2 registers with a default
989 * value so legacy systems unaware of FEAT_FGT
990 * do not get trapped due to their lack of
991 * initialization for this feature.
992 */
993 write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
994 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
995 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
996 }
997
998 /* Condition to ensure EL2 is being used. */
999 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
1000 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
1001 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
1002 CTX_SCTLR_EL1);
1003 sctlr_elx &= SCTLR_EE_BIT;
1004 sctlr_elx |= SCTLR_EL2_RES1;
1005 #if ERRATA_A75_764081
1006 /*
1007 * If workaround of errata 764081 for Cortex-A75
1008 * is used then set SCTLR_EL2.IESB to enable
1009 * Implicit Error Synchronization Barrier.
1010 */
1011 sctlr_elx |= SCTLR_IESB_BIT;
1012 #endif /* ERRATA_A75_764081 */
1013 write_sctlr_el2(sctlr_elx);
1014 } else {
1015 /*
1016 * (scr_el3 & SCR_HCE_BIT==0)
1017 * EL2 implemented but unused.
1018 */
1019 init_nonsecure_el2_unused(ctx);
1020 }
1021 }
1022 }
1023 cm_el1_sysregs_context_restore(security_state);
1024 cm_set_next_eret_context(security_state);
1025 }
1026
1027 #if CTX_INCLUDE_EL2_REGS
1028
el2_sysregs_context_save_fgt(el2_sysregs_t * ctx)1029 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
1030 {
1031 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2());
1032 if (is_feat_amu_supported()) {
1033 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2());
1034 }
1035 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2());
1036 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2());
1037 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2());
1038 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2());
1039 }
1040
el2_sysregs_context_restore_fgt(el2_sysregs_t * ctx)1041 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
1042 {
1043 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2));
1044 if (is_feat_amu_supported()) {
1045 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2));
1046 }
1047 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2));
1048 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2));
1049 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2));
1050 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2));
1051 }
1052
1053 #if CTX_INCLUDE_MPAM_REGS
1054
el2_sysregs_context_save_mpam(mpam_t * ctx)1055 static void el2_sysregs_context_save_mpam(mpam_t *ctx)
1056 {
1057 u_register_t mpam_idr = read_mpamidr_el1();
1058
1059 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2());
1060
1061 /*
1062 * The context registers that we intend to save would be part of the
1063 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1.
1064 */
1065 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1066 return;
1067 }
1068
1069 /*
1070 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if
1071 * MPAMIDR_HAS_HCR_BIT == 1.
1072 */
1073 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2());
1074 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2());
1075 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2());
1076
1077 /*
1078 * The number of MPAMVPM registers is implementation defined, their
1079 * number is stored in the MPAMIDR_EL1 register.
1080 */
1081 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1082 case 7:
1083 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2());
1084 __fallthrough;
1085 case 6:
1086 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2());
1087 __fallthrough;
1088 case 5:
1089 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2());
1090 __fallthrough;
1091 case 4:
1092 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2());
1093 __fallthrough;
1094 case 3:
1095 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2());
1096 __fallthrough;
1097 case 2:
1098 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2());
1099 __fallthrough;
1100 case 1:
1101 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2());
1102 break;
1103 }
1104 }
1105
1106 #endif /* CTX_INCLUDE_MPAM_REGS */
1107
1108 #if CTX_INCLUDE_MPAM_REGS
el2_sysregs_context_restore_mpam(mpam_t * ctx)1109 static void el2_sysregs_context_restore_mpam(mpam_t *ctx)
1110 {
1111 u_register_t mpam_idr = read_mpamidr_el1();
1112
1113 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2));
1114
1115 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1116 return;
1117 }
1118
1119 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2));
1120 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2));
1121 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2));
1122
1123 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1124 case 7:
1125 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2));
1126 __fallthrough;
1127 case 6:
1128 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2));
1129 __fallthrough;
1130 case 5:
1131 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2));
1132 __fallthrough;
1133 case 4:
1134 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2));
1135 __fallthrough;
1136 case 3:
1137 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2));
1138 __fallthrough;
1139 case 2:
1140 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2));
1141 __fallthrough;
1142 case 1:
1143 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2));
1144 break;
1145 }
1146 }
1147 #endif /* CTX_INCLUDE_MPAM_REGS */
1148
1149 /* ---------------------------------------------------------------------------
1150 * The following registers are not added:
1151 * ICH_AP0R<n>_EL2
1152 * ICH_AP1R<n>_EL2
1153 * ICH_LR<n>_EL2
1154 *
1155 * NOTE: For a system with S-EL2 present but not enabled, accessing
1156 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the
1157 * SCR_EL3.NS = 1 before accessing this register.
1158 * ---------------------------------------------------------------------------
1159 */
el2_sysregs_context_save_gic(el2_sysregs_t * ctx)1160 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx)
1161 {
1162 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1163 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1164 #else
1165 u_register_t scr_el3 = read_scr_el3();
1166 write_scr_el3(scr_el3 | SCR_NS_BIT);
1167 isb();
1168
1169 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1170
1171 write_scr_el3(scr_el3);
1172 isb();
1173 #endif
1174 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2());
1175 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2());
1176 }
1177
el2_sysregs_context_restore_gic(el2_sysregs_t * ctx)1178 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx)
1179 {
1180 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1181 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1182 #else
1183 u_register_t scr_el3 = read_scr_el3();
1184 write_scr_el3(scr_el3 | SCR_NS_BIT);
1185 isb();
1186
1187 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1188
1189 write_scr_el3(scr_el3);
1190 isb();
1191 #endif
1192 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2));
1193 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2));
1194 }
1195
1196 /* -----------------------------------------------------
1197 * The following registers are not added:
1198 * AMEVCNTVOFF0<n>_EL2
1199 * AMEVCNTVOFF1<n>_EL2
1200 * -----------------------------------------------------
1201 */
el2_sysregs_context_save_common(el2_sysregs_t * ctx)1202 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
1203 {
1204 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2());
1205 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2());
1206 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2());
1207 write_el2_ctx_common(ctx, amair_el2, read_amair_el2());
1208 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2());
1209 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2());
1210 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2());
1211 if (CTX_INCLUDE_AARCH32_REGS) {
1212 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2());
1213 }
1214 write_el2_ctx_common(ctx, elr_el2, read_elr_el2());
1215 write_el2_ctx_common(ctx, esr_el2, read_esr_el2());
1216 write_el2_ctx_common(ctx, far_el2, read_far_el2());
1217 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2());
1218 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2());
1219 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2());
1220 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2());
1221 write_el2_ctx_common(ctx, mair_el2, read_mair_el2());
1222 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2());
1223 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2());
1224 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2());
1225 write_el2_ctx_common(ctx, sp_el2, read_sp_el2());
1226 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2());
1227 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2());
1228 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2());
1229 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2());
1230 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2());
1231 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2());
1232 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2());
1233 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2());
1234 }
1235
el2_sysregs_context_restore_common(el2_sysregs_t * ctx)1236 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
1237 {
1238 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2));
1239 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2));
1240 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2));
1241 write_amair_el2(read_el2_ctx_common(ctx, amair_el2));
1242 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2));
1243 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2));
1244 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2));
1245 if (CTX_INCLUDE_AARCH32_REGS) {
1246 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2));
1247 }
1248 write_elr_el2(read_el2_ctx_common(ctx, elr_el2));
1249 write_esr_el2(read_el2_ctx_common(ctx, esr_el2));
1250 write_far_el2(read_el2_ctx_common(ctx, far_el2));
1251 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2));
1252 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2));
1253 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2));
1254 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2));
1255 write_mair_el2(read_el2_ctx_common(ctx, mair_el2));
1256 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2));
1257 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2));
1258 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2));
1259 write_sp_el2(read_el2_ctx_common(ctx, sp_el2));
1260 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2));
1261 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2));
1262 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2));
1263 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2));
1264 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2));
1265 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2));
1266 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2));
1267 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2));
1268 }
1269
1270 /*******************************************************************************
1271 * Save EL2 sysreg context
1272 ******************************************************************************/
cm_el2_sysregs_context_save(uint32_t security_state)1273 void cm_el2_sysregs_context_save(uint32_t security_state)
1274 {
1275 cpu_context_t *ctx;
1276 el2_sysregs_t *el2_sysregs_ctx;
1277
1278 ctx = cm_get_context(security_state);
1279 assert(ctx != NULL);
1280
1281 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1282
1283 el2_sysregs_context_save_common(el2_sysregs_ctx);
1284 el2_sysregs_context_save_gic(el2_sysregs_ctx);
1285
1286 if (is_feat_mte2_supported()) {
1287 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
1288 }
1289
1290 #if CTX_INCLUDE_MPAM_REGS
1291 if (is_feat_mpam_supported()) {
1292 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1293 el2_sysregs_context_save_mpam(mpam_ctx);
1294 }
1295 #endif
1296
1297 if (is_feat_fgt_supported()) {
1298 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
1299 }
1300
1301 if (is_feat_ecv_v2_supported()) {
1302 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2());
1303 }
1304
1305 if (is_feat_vhe_supported()) {
1306 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2,
1307 read_contextidr_el2());
1308 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2());
1309 }
1310
1311 if (is_feat_ras_supported()) {
1312 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2());
1313 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2());
1314 }
1315
1316 if (is_feat_nv2_supported()) {
1317 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2());
1318 }
1319
1320 if (is_feat_trf_supported()) {
1321 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2());
1322 }
1323
1324 if (is_feat_csv2_2_supported()) {
1325 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2,
1326 read_scxtnum_el2());
1327 }
1328
1329 if (is_feat_hcx_supported()) {
1330 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2());
1331 }
1332
1333 if (is_feat_tcr2_supported()) {
1334 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2());
1335 }
1336
1337 if (is_feat_sxpie_supported()) {
1338 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2());
1339 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2());
1340 }
1341
1342 if (is_feat_sxpoe_supported()) {
1343 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2());
1344 }
1345
1346 if (is_feat_s2pie_supported()) {
1347 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2());
1348 }
1349
1350 if (is_feat_gcs_supported()) {
1351 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
1352 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
1353 }
1354 }
1355
1356 /*******************************************************************************
1357 * Restore EL2 sysreg context
1358 ******************************************************************************/
cm_el2_sysregs_context_restore(uint32_t security_state)1359 void cm_el2_sysregs_context_restore(uint32_t security_state)
1360 {
1361 cpu_context_t *ctx;
1362 el2_sysregs_t *el2_sysregs_ctx;
1363
1364 ctx = cm_get_context(security_state);
1365 assert(ctx != NULL);
1366
1367 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1368
1369 el2_sysregs_context_restore_common(el2_sysregs_ctx);
1370 el2_sysregs_context_restore_gic(el2_sysregs_ctx);
1371
1372 if (is_feat_mte2_supported()) {
1373 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2));
1374 }
1375
1376 #if CTX_INCLUDE_MPAM_REGS
1377 if (is_feat_mpam_supported()) {
1378 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1379 el2_sysregs_context_restore_mpam(mpam_ctx);
1380 }
1381 #endif
1382
1383 if (is_feat_fgt_supported()) {
1384 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
1385 }
1386
1387 if (is_feat_ecv_v2_supported()) {
1388 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2));
1389 }
1390
1391 if (is_feat_vhe_supported()) {
1392 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx,
1393 contextidr_el2));
1394 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2));
1395 }
1396
1397 if (is_feat_ras_supported()) {
1398 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2));
1399 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2));
1400 }
1401
1402 if (is_feat_nv2_supported()) {
1403 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2));
1404 }
1405
1406 if (is_feat_trf_supported()) {
1407 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2));
1408 }
1409
1410 if (is_feat_csv2_2_supported()) {
1411 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx,
1412 scxtnum_el2));
1413 }
1414
1415 if (is_feat_hcx_supported()) {
1416 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2));
1417 }
1418
1419 if (is_feat_tcr2_supported()) {
1420 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2));
1421 }
1422
1423 if (is_feat_sxpie_supported()) {
1424 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2));
1425 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2));
1426 }
1427
1428 if (is_feat_sxpoe_supported()) {
1429 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2));
1430 }
1431
1432 if (is_feat_s2pie_supported()) {
1433 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2));
1434 }
1435
1436 if (is_feat_gcs_supported()) {
1437 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
1438 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
1439 }
1440 }
1441 #endif /* CTX_INCLUDE_EL2_REGS */
1442
1443 /*******************************************************************************
1444 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1445 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1446 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1447 * cm_prepare_el3_exit function.
1448 ******************************************************************************/
cm_prepare_el3_exit_ns(void)1449 void cm_prepare_el3_exit_ns(void)
1450 {
1451 #if CTX_INCLUDE_EL2_REGS
1452 #if ENABLE_ASSERTIONS
1453 cpu_context_t *ctx = cm_get_context(NON_SECURE);
1454 assert(ctx != NULL);
1455
1456 /* Assert that EL2 is used. */
1457 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1458 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1459 (el_implemented(2U) != EL_IMPL_NONE));
1460 #endif /* ENABLE_ASSERTIONS */
1461
1462 /* Restore EL2 and EL1 sysreg contexts */
1463 cm_el2_sysregs_context_restore(NON_SECURE);
1464 cm_el1_sysregs_context_restore(NON_SECURE);
1465 cm_set_next_eret_context(NON_SECURE);
1466 #else
1467 cm_prepare_el3_exit(NON_SECURE);
1468 #endif /* CTX_INCLUDE_EL2_REGS */
1469 }
1470
el1_sysregs_context_save(el1_sysregs_t * ctx)1471 static void el1_sysregs_context_save(el1_sysregs_t *ctx)
1472 {
1473 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1());
1474 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1());
1475
1476 #if !ERRATA_SPECULATIVE_AT
1477 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1());
1478 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1());
1479 #endif /* (!ERRATA_SPECULATIVE_AT) */
1480
1481 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1());
1482 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1());
1483 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1());
1484 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1());
1485 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1());
1486 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1());
1487 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1());
1488 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1());
1489 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1());
1490 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1());
1491 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0());
1492 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0());
1493 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1());
1494 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1());
1495 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1());
1496 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1());
1497 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1());
1498 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1());
1499 write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1());
1500 write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1());
1501
1502 #if CTX_INCLUDE_AARCH32_REGS
1503 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt());
1504 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und());
1505 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq());
1506 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq());
1507 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2());
1508 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2());
1509 #endif /* CTX_INCLUDE_AARCH32_REGS */
1510
1511 #if NS_TIMER_SWITCH
1512 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0());
1513 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0());
1514 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0());
1515 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0());
1516 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1());
1517 #endif /* NS_TIMER_SWITCH */
1518
1519 #if ENABLE_FEAT_MTE2
1520 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1());
1521 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1());
1522 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1());
1523 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
1524 #endif /* ENABLE_FEAT_MTE2 */
1525
1526 #if ENABLE_FEAT_RAS
1527 if (is_feat_ras_supported()) {
1528 write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1());
1529 }
1530 #endif
1531
1532 #if ENABLE_FEAT_S1PIE
1533 if (is_feat_s1pie_supported()) {
1534 write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1());
1535 write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1());
1536 }
1537 #endif
1538
1539 #if ENABLE_FEAT_S1POE
1540 if (is_feat_s1poe_supported()) {
1541 write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1());
1542 }
1543 #endif
1544
1545 #if ENABLE_FEAT_S2POE
1546 if (is_feat_s2poe_supported()) {
1547 write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1());
1548 }
1549 #endif
1550
1551 #if ENABLE_FEAT_TCR2
1552 if (is_feat_tcr2_supported()) {
1553 write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
1554 }
1555 #endif
1556
1557 #if ENABLE_TRF_FOR_NS
1558 if (is_feat_trf_supported()) {
1559 write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
1560 }
1561 #endif
1562
1563 #if ENABLE_FEAT_CSV2_2
1564 if (is_feat_csv2_2_supported()) {
1565 write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
1566 write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
1567 }
1568 #endif
1569
1570 #if ENABLE_FEAT_GCS
1571 if (is_feat_gcs_supported()) {
1572 write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
1573 write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
1574 write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
1575 write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
1576 }
1577 #endif
1578 }
1579
el1_sysregs_context_restore(el1_sysregs_t * ctx)1580 static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
1581 {
1582 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1));
1583 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1));
1584
1585 #if !ERRATA_SPECULATIVE_AT
1586 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1));
1587 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1));
1588 #endif /* (!ERRATA_SPECULATIVE_AT) */
1589
1590 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1));
1591 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1));
1592 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1));
1593 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1));
1594 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1));
1595 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1));
1596 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1));
1597 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1));
1598 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1));
1599 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1));
1600 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0));
1601 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0));
1602 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1));
1603 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1));
1604 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1));
1605 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1));
1606 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1));
1607 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1));
1608 write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1));
1609 write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1));
1610
1611 #if CTX_INCLUDE_AARCH32_REGS
1612 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT));
1613 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND));
1614 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ));
1615 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ));
1616 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2));
1617 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2));
1618 #endif /* CTX_INCLUDE_AARCH32_REGS */
1619
1620 #if NS_TIMER_SWITCH
1621 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0));
1622 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0));
1623 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0));
1624 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0));
1625 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1));
1626 #endif /* NS_TIMER_SWITCH */
1627
1628 #if ENABLE_FEAT_MTE2
1629 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1));
1630 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1));
1631 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1));
1632 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
1633 #endif /* ENABLE_FEAT_MTE2 */
1634
1635 #if ENABLE_FEAT_RAS
1636 if (is_feat_ras_supported()) {
1637 write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1));
1638 }
1639 #endif
1640
1641 #if ENABLE_FEAT_S1PIE
1642 if (is_feat_s1pie_supported()) {
1643 write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1));
1644 write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1));
1645 }
1646 #endif
1647
1648 #if ENABLE_FEAT_S1POE
1649 if (is_feat_s1poe_supported()) {
1650 write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1));
1651 }
1652 #endif
1653
1654 #if ENABLE_FEAT_S2POE
1655 if (is_feat_s2poe_supported()) {
1656 write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1));
1657 }
1658 #endif
1659
1660 #if ENABLE_FEAT_TCR2
1661 if (is_feat_tcr2_supported()) {
1662 write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
1663 }
1664 #endif
1665
1666 #if ENABLE_TRF_FOR_NS
1667 if (is_feat_trf_supported()) {
1668 write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
1669 }
1670 #endif
1671
1672 #if ENABLE_FEAT_CSV2_2
1673 if (is_feat_csv2_2_supported()) {
1674 write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
1675 write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
1676 }
1677 #endif
1678
1679 #if ENABLE_FEAT_GCS
1680 if (is_feat_gcs_supported()) {
1681 write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
1682 write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
1683 write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
1684 write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
1685 }
1686 #endif
1687 }
1688
1689 /*******************************************************************************
1690 * The next four functions are used by runtime services to save and restore
1691 * EL1 context on the 'cpu_context' structure for the specified security
1692 * state.
1693 ******************************************************************************/
cm_el1_sysregs_context_save(uint32_t security_state)1694 void cm_el1_sysregs_context_save(uint32_t security_state)
1695 {
1696 cpu_context_t *ctx;
1697
1698 ctx = cm_get_context(security_state);
1699 assert(ctx != NULL);
1700
1701 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
1702
1703 #if IMAGE_BL31
1704 if (security_state == SECURE)
1705 PUBLISH_EVENT(cm_exited_secure_world);
1706 else
1707 PUBLISH_EVENT(cm_exited_normal_world);
1708 #endif
1709 }
1710
cm_el1_sysregs_context_restore(uint32_t security_state)1711 void cm_el1_sysregs_context_restore(uint32_t security_state)
1712 {
1713 cpu_context_t *ctx;
1714
1715 ctx = cm_get_context(security_state);
1716 assert(ctx != NULL);
1717
1718 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
1719
1720 #if IMAGE_BL31
1721 if (security_state == SECURE)
1722 PUBLISH_EVENT(cm_entering_secure_world);
1723 else
1724 PUBLISH_EVENT(cm_entering_normal_world);
1725 #endif
1726 }
1727
1728 /*******************************************************************************
1729 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1730 * given security state with the given entrypoint
1731 ******************************************************************************/
cm_set_elr_el3(uint32_t security_state,uintptr_t entrypoint)1732 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
1733 {
1734 cpu_context_t *ctx;
1735 el3_state_t *state;
1736
1737 ctx = cm_get_context(security_state);
1738 assert(ctx != NULL);
1739
1740 /* Populate EL3 state so that ERET jumps to the correct entry */
1741 state = get_el3state_ctx(ctx);
1742 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1743 }
1744
1745 /*******************************************************************************
1746 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
1747 * pertaining to the given security state
1748 ******************************************************************************/
cm_set_elr_spsr_el3(uint32_t security_state,uintptr_t entrypoint,uint32_t spsr)1749 void cm_set_elr_spsr_el3(uint32_t security_state,
1750 uintptr_t entrypoint, uint32_t spsr)
1751 {
1752 cpu_context_t *ctx;
1753 el3_state_t *state;
1754
1755 ctx = cm_get_context(security_state);
1756 assert(ctx != NULL);
1757
1758 /* Populate EL3 state so that ERET jumps to the correct entry */
1759 state = get_el3state_ctx(ctx);
1760 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1761 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
1762 }
1763
1764 /*******************************************************************************
1765 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
1766 * pertaining to the given security state using the value and bit position
1767 * specified in the parameters. It preserves all other bits.
1768 ******************************************************************************/
cm_write_scr_el3_bit(uint32_t security_state,uint32_t bit_pos,uint32_t value)1769 void cm_write_scr_el3_bit(uint32_t security_state,
1770 uint32_t bit_pos,
1771 uint32_t value)
1772 {
1773 cpu_context_t *ctx;
1774 el3_state_t *state;
1775 u_register_t scr_el3;
1776
1777 ctx = cm_get_context(security_state);
1778 assert(ctx != NULL);
1779
1780 /* Ensure that the bit position is a valid one */
1781 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
1782
1783 /* Ensure that the 'value' is only a bit wide */
1784 assert(value <= 1U);
1785
1786 /*
1787 * Get the SCR_EL3 value from the cpu context, clear the desired bit
1788 * and set it to its new value.
1789 */
1790 state = get_el3state_ctx(ctx);
1791 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
1792 scr_el3 &= ~(1UL << bit_pos);
1793 scr_el3 |= (u_register_t)value << bit_pos;
1794 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1795 }
1796
1797 /*******************************************************************************
1798 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
1799 * given security state.
1800 ******************************************************************************/
cm_get_scr_el3(uint32_t security_state)1801 u_register_t cm_get_scr_el3(uint32_t security_state)
1802 {
1803 cpu_context_t *ctx;
1804 el3_state_t *state;
1805
1806 ctx = cm_get_context(security_state);
1807 assert(ctx != NULL);
1808
1809 /* Populate EL3 state so that ERET jumps to the correct entry */
1810 state = get_el3state_ctx(ctx);
1811 return read_ctx_reg(state, CTX_SCR_EL3);
1812 }
1813
1814 /*******************************************************************************
1815 * This function is used to program the context that's used for exception
1816 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
1817 * the required security state
1818 ******************************************************************************/
cm_set_next_eret_context(uint32_t security_state)1819 void cm_set_next_eret_context(uint32_t security_state)
1820 {
1821 cpu_context_t *ctx;
1822
1823 ctx = cm_get_context(security_state);
1824 assert(ctx != NULL);
1825
1826 cm_set_next_context(ctx);
1827 }
1828