1/*
2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_v3.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
30#if IMAGE_BL31
31	/*
32	 * The Neoverse V3 generic vectors are overridden to apply errata
33         * mitigation on exception entry from lower ELs.
34	 */
35	override_vector_table wa_cve_vbar_neoverse_v3
36
37#endif /* IMAGE_BL31 */
38workaround_reset_end neoverse_v3, CVE(2022,23960)
39
40check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
41
42	/* ---------------------------------------------
43	 * HW will do the cache maintenance while powering down
44	 * ---------------------------------------------
45	 */
46func neoverse_v3_core_pwr_dwn
47	/* ---------------------------------------------
48	 * Enable CPU power down bit in power control register
49	 * ---------------------------------------------
50	 */
51	sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
52		NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
53
54	isb
55	ret
56endfunc neoverse_v3_core_pwr_dwn
57
58cpu_reset_func_start neoverse_v3
59	/* Disable speculative loads */
60	msr	SSBS, xzr
61cpu_reset_func_end neoverse_v3
62
63errata_report_shim neoverse_v3
64
65	/* ---------------------------------------------
66	 * This function provides Neoverse V3 specific
67	 * register information for crash reporting.
68	 * It needs to return with x6 pointing to
69	 * a list of register names in ascii and
70	 * x8 - x15 having values of registers to be
71	 * reported.
72	 * ---------------------------------------------
73	 */
74.section .rodata.neoverse_v3_regs, "aS"
75neoverse_v3_regs:  /* The ascii list of register names to be reported */
76	.asciz	"cpuectlr_el1", ""
77
78func neoverse_v3_cpu_reg_dump
79	adr	x6, neoverse_v3_regs
80	mrs	x8, NEOVERSE_V3_CPUECTLR_EL1
81	ret
82endfunc neoverse_v3_cpu_reg_dump
83
84declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
85	neoverse_v3_reset_func, \
86	neoverse_v3_core_pwr_dwn
87
88declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
89	neoverse_v3_reset_func, \
90	neoverse_v3_core_pwr_dwn
91