1/*
2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_v2.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
26	sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
27		NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
28workaround_reset_end neoverse_v2, ERRATUM(2331132)
29
30check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
31
32workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597
33        /* Disable retention control for WFI and WFE. */
34        mrs     x0, NEOVERSE_V2_CPUPWRCTLR_EL1
35        bfi     x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \
36		#NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH
37        bfi     x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \
38		#NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH
39        msr     NEOVERSE_V2_CPUPWRCTLR_EL1, x0
40workaround_reset_end neoverse_v2, ERRATUM(2618597)
41
42check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1)
43
44workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553
45	sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \
46		NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH
47workaround_reset_end neoverse_v2, ERRATUM(2662553)
48
49check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1)
50
51workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
52	sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
53workaround_reset_end neoverse_v2, ERRATUM(2719105)
54
55check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
56
57workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011
58	sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55
59	sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56
60workaround_reset_end neoverse_v2, ERRATUM(2743011)
61
62check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1)
63
64workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
65	sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
66workaround_reset_end neoverse_v2, ERRATUM(2779510)
67
68check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
69
70workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
71	/* dsb before isb of power down sequence */
72	dsb	sy
73workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
74
75check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
76
77workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
78#if IMAGE_BL31
79	/*
80	 * The Neoverse-V2 generic vectors are overridden to apply errata
81         * mitigation on exception entry from lower ELs.
82	 */
83	override_vector_table wa_cve_vbar_neoverse_v2
84#endif /* IMAGE_BL31 */
85workaround_reset_end neoverse_v2, CVE(2022,23960)
86
87check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
88
89#if WORKAROUND_CVE_2022_23960
90	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
91#endif /* WORKAROUND_CVE_2022_23960 */
92
93	/* ----------------------------------------------------
94	 * HW will do the cache maintenance while powering down
95	 * ----------------------------------------------------
96	 */
97func neoverse_v2_core_pwr_dwn
98	/* ---------------------------------------------------
99	 * Enable CPU power down bit in power control register
100	 * ---------------------------------------------------
101	 */
102	sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
103	apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
104
105	isb
106	ret
107endfunc neoverse_v2_core_pwr_dwn
108
109cpu_reset_func_start neoverse_v2
110	/* Disable speculative loads */
111	msr	SSBS, xzr
112
113#if NEOVERSE_Vx_EXTERNAL_LLC
114	/* Some systems may have External LLC, core needs to be made aware */
115	sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT
116#endif
117cpu_reset_func_end neoverse_v2
118
119errata_report_shim neoverse_v2
120	/* ---------------------------------------------
121	 * This function provides Neoverse V2-
122	 * specific register information for crash
123	 * reporting. It needs to return with x6
124	 * pointing to a list of register names in ascii
125	 * and x8 - x15 having values of registers to be
126	 * reported.
127	 * ---------------------------------------------
128	 */
129.section .rodata.neoverse_v2_regs, "aS"
130neoverse_v2_regs:  /* The ascii list of register names to be reported */
131	.asciz	"cpuectlr_el1", ""
132
133func neoverse_v2_cpu_reg_dump
134	adr	x6, neoverse_v2_regs
135	mrs	x8, NEOVERSE_V2_CPUECTLR_EL1
136	ret
137endfunc neoverse_v2_cpu_reg_dump
138
139declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
140	neoverse_v2_reset_func, \
141	neoverse_v2_core_pwr_dwn
142