1/*
2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_v1.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
30	/* Inserts a DMB SY before and after MRS PAR_EL1 */
31	ldr	x0, =0x0
32	msr	NEOVERSE_V1_CPUPSELR_EL3, x0
33	ldr	x0, = 0xEE070F14
34	msr	NEOVERSE_V1_CPUPOR_EL3, x0
35	ldr	x0, = 0xFFFF0FFF
36	msr	NEOVERSE_V1_CPUPMR_EL3, x0
37	ldr	x0, =0x4005027FF
38	msr	NEOVERSE_V1_CPUPCR_EL3, x0
39
40	/* Inserts a DMB SY before STREX imm offset */
41	ldr	x0, =0x1
42	msr	NEOVERSE_V1_CPUPSELR_EL3, x0
43	ldr	x0, =0x00e8400000
44	msr	NEOVERSE_V1_CPUPOR_EL3, x0
45	ldr	x0, =0x00fff00000
46	msr	NEOVERSE_V1_CPUPMR_EL3, x0
47	ldr	x0, = 0x4001027FF
48	msr	NEOVERSE_V1_CPUPCR_EL3, x0
49
50	/* Inserts a DMB SY before STREX[BHD}/STLEX* */
51	ldr	x0, =0x2
52	msr	NEOVERSE_V1_CPUPSELR_EL3, x0
53	ldr	x0, =0x00e8c00040
54	msr	NEOVERSE_V1_CPUPOR_EL3, x0
55	ldr	x0, =0x00fff00040
56	msr	NEOVERSE_V1_CPUPMR_EL3, x0
57	ldr	x0, = 0x4001027FF
58	msr	NEOVERSE_V1_CPUPCR_EL3, x0
59
60	/* Inserts a DMB SY after STREX imm offset */
61	ldr	x0, =0x3
62	msr	NEOVERSE_V1_CPUPSELR_EL3, x0
63	ldr	x0, =0x00e8400000
64	msr	NEOVERSE_V1_CPUPOR_EL3, x0
65	ldr	x0, =0x00fff00000
66	msr	NEOVERSE_V1_CPUPMR_EL3, x0
67	ldr	x0, = 0x4004027FF
68	msr	NEOVERSE_V1_CPUPCR_EL3, x0
69
70	/* Inserts a DMB SY after STREX[BHD}/STLEX* */
71	ldr	x0, =0x4
72	msr	NEOVERSE_V1_CPUPSELR_EL3, x0
73	ldr	x0, =0x00e8c00040
74	msr	NEOVERSE_V1_CPUPOR_EL3, x0
75	ldr	x0, =0x00fff00040
76	msr	NEOVERSE_V1_CPUPMR_EL3, x0
77	ldr	x0, = 0x4004027FF
78	msr	NEOVERSE_V1_CPUPCR_EL3, x0
79
80workaround_reset_end neoverse_v1, ERRATUM(1618635)
81
82check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
83
84workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
85	/* Set bit 53 in CPUECTLR_EL1 */
86	sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
87workaround_reset_end neoverse_v1, ERRATUM(1774420)
88
89check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
90
91workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
92	/* Set bit 2 in ACTLR2_EL1 */
93	sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
94workaround_reset_end neoverse_v1, ERRATUM(1791573)
95
96check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
97
98workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
99	/* Set bit 28 in ACTLR2_EL1 */
100	sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
101workaround_reset_end neoverse_v1, ERRATUM(1852267)
102
103check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
104
105workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
106	/* Set bit 8 in CPUECTLR_EL1 */
107	sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
108workaround_reset_end neoverse_v1, ERRATUM(1925756)
109
110check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
111
112workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
113	mov	x0, #0
114	msr	S3_6_C15_C8_0, x0
115	ldr	x0, =0x10E3900002
116	msr	S3_6_C15_C8_2, x0
117	ldr	x0, =0x10FFF00083
118	msr	S3_6_C15_C8_3, x0
119	ldr	x0, =0x2001003FF
120	msr	S3_6_C15_C8_1, x0
121
122	mov	x0, #1
123	msr	S3_6_C15_C8_0, x0
124	ldr	x0, =0x10E3800082
125	msr	S3_6_C15_C8_2, x0
126	ldr	x0, =0x10FFF00083
127	msr	S3_6_C15_C8_3, x0
128	ldr	x0, =0x2001003FF
129	msr	S3_6_C15_C8_1, x0
130
131	mov	x0, #2
132	msr	S3_6_C15_C8_0, x0
133	ldr	x0, =0x10E3800200
134	msr	S3_6_C15_C8_2, x0
135	ldr	x0, =0x10FFF003E0
136	msr	S3_6_C15_C8_3, x0
137	ldr	x0, =0x2001003FF
138	msr	S3_6_C15_C8_1, x0
139
140workaround_reset_end neoverse_v1, ERRATUM(1940577)
141
142check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
143
144workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
145	mov	x0, #0x3
146	msr	S3_6_C15_C8_0, x0
147	ldr	x0, =0xEE010F12
148	msr	S3_6_C15_C8_2, x0
149	ldr	x0, =0xFFFF0FFF
150	msr	S3_6_C15_C8_3, x0
151	ldr	x0, =0x80000000003FF
152	msr	S3_6_C15_C8_1, x0
153workaround_reset_end neoverse_v1, ERRATUM(1966096)
154
155check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
156
157workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
158	mrs	x1, NEOVERSE_V1_CPUECTLR_EL1
159	mov	x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
160	bfi	x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
161	msr	NEOVERSE_V1_CPUECTLR_EL1, x1
162workaround_reset_end neoverse_v1, ERRATUM(2108267)
163
164check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2)
165
166workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
167	mov	x0, #0x3
168	msr	S3_6_C15_C8_0, x0
169	ldr	x0, =0xEE720F14
170	msr	S3_6_C15_C8_2, x0
171	ldr	x0, =0xFFFF0FDF
172	msr	S3_6_C15_C8_3, x0
173	ldr	x0, =0x40000005003FF
174	msr	S3_6_C15_C8_1, x0
175workaround_reset_end neoverse_v1, ERRATUM(2139242)
176
177check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
178
179workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
180	ldr	x0, =0x5
181	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
182	ldr	x0, =0x10F600E000
183	msr	S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
184	ldr	x0, =0x10FF80E000
185	msr	S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
186	ldr	x0, =0x80000000003FF
187	msr	S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
188workaround_reset_end neoverse_v1, ERRATUM(2216392)
189
190check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
191
192workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
193	/* Set bit 0 in ACTLR2_EL1 */
194	sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
195workaround_reset_end neoverse_v1, ERRATUM(2294912)
196
197check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2)
198
199workaround_runtime_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377
200	/* Set bit 61 in CPUACTLR5_EL1 */
201	sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61
202workaround_runtime_end neoverse_v1, ERRATUM(2348377)
203
204check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1)
205
206workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
207	/* Set bit 40 in ACTLR2_EL1 */
208	sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
209workaround_reset_end neoverse_v1, ERRATUM(2372203)
210
211check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
212
213workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
214	/* dsb before isb of power down sequence */
215	dsb	sy
216workaround_runtime_end neoverse_v1, ERRATUM(2743093)
217
218check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
219
220workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
221	sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
222	sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
223workaround_reset_end neoverse_v1, ERRATUM(2743233)
224
225check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
226
227workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
228	sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
229workaround_reset_end neoverse_v1, ERRATUM(2779461)
230
231check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
232
233
234workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
235#if IMAGE_BL31
236	/*
237	 * The Neoverse-V1 generic vectors are overridden to apply errata
238         * mitigation on exception entry from lower ELs.
239	 */
240	override_vector_table wa_cve_vbar_neoverse_v1
241#endif /* IMAGE_BL31 */
242workaround_reset_end neoverse_v1, CVE(2022,23960)
243
244check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
245
246	/* ---------------------------------------------
247	 * HW will do the cache maintenance while powering down
248	 * ---------------------------------------------
249	 */
250func neoverse_v1_core_pwr_dwn
251	/* ---------------------------------------------
252	 * Enable CPU power down bit in power control register
253	 * ---------------------------------------------
254	 */
255	sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
256	apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
257
258	isb
259	ret
260endfunc neoverse_v1_core_pwr_dwn
261
262errata_report_shim neoverse_v1
263
264cpu_reset_func_start neoverse_v1
265	/* Disable speculative loads */
266	msr	SSBS, xzr
267cpu_reset_func_end neoverse_v1
268
269	/* ---------------------------------------------
270	 * This function provides Neoverse-V1 specific
271	 * register information for crash reporting.
272	 * It needs to return with x6 pointing to
273	 * a list of register names in ascii and
274	 * x8 - x15 having values of registers to be
275	 * reported.
276	 * ---------------------------------------------
277	 */
278.section .rodata.neoverse_v1_regs, "aS"
279neoverse_v1_regs:  /* The ascii list of register names to be reported */
280	.asciz	"cpuectlr_el1", ""
281
282func neoverse_v1_cpu_reg_dump
283	adr	x6, neoverse_v1_regs
284	mrs	x8, NEOVERSE_V1_CPUECTLR_EL1
285	ret
286endfunc neoverse_v1_cpu_reg_dump
287
288declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
289	neoverse_v1_reset_func, \
290	neoverse_v1_core_pwr_dwn
291