1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cpuamu.h>
10#include <cpu_macros.S>
11#include <neoverse_n1.h>
12#include "wa_cve_2022_23960_bhb_vector.S"
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24	.global neoverse_n1_errata_ic_trap_handler
25
26#if WORKAROUND_CVE_2022_23960
27	wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
28#endif /* WORKAROUND_CVE_2022_23960 */
29
30/*
31 * ERRATA_DSU_936184:
32 * The errata is defined in dsu_helpers.S and applies to Neoverse N1.
33 * Henceforth creating symbolic names to the already existing errata
34 * workaround functions to get them registered under the Errata Framework.
35 */
36.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
37.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
38add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
39
40workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
41	/* Apply instruction patching sequence */
42	ldr	x0, =0x0
43	msr	CPUPSELR_EL3, x0
44	ldr	x0, =0xF3BF8F2F
45	msr	CPUPOR_EL3, x0
46	ldr	x0, =0xFFFFFFFF
47	msr	CPUPMR_EL3, x0
48	ldr	x0, =0x800200071
49	msr	CPUPCR_EL3, x0
50workaround_reset_end neoverse_n1, ERRATUM(1043202)
51
52check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
53
54workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
55	sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
56workaround_reset_end neoverse_n1, ERRATUM(1073348)
57
58check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
59
60workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
61	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
62workaround_reset_end neoverse_n1, ERRATUM(1130799)
63
64check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
65
66workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
67	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
68	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
69workaround_reset_end neoverse_n1, ERRATUM(1165347)
70
71check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
72
73workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
74	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
75workaround_reset_end neoverse_n1, ERRATUM(1207823)
76
77check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
78
79workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
80	sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
81workaround_reset_end neoverse_n1, ERRATUM(1220197)
82
83check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
84
85workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
86	sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
87workaround_reset_end neoverse_n1, ERRATUM(1257314)
88
89check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
90
91workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
92	sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
93workaround_reset_end neoverse_n1, ERRATUM(1262606)
94
95check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
96
97workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
98	sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
99workaround_reset_end neoverse_n1, ERRATUM(1262888)
100
101check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
102
103workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
104	sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
105workaround_reset_end neoverse_n1, ERRATUM(1275112)
106
107check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
108
109workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
110	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
111workaround_reset_end neoverse_n1, ERRATUM(1315703)
112
113check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
114
115workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
116	/* Apply instruction patching sequence */
117	ldr	x0, =0x0
118	msr	CPUPSELR_EL3, x0
119	ldr	x0, =0xEE670D35
120	msr	CPUPOR_EL3, x0
121	ldr	x0, =0xFFFF0FFF
122	msr	CPUPMR_EL3, x0
123	ldr	x0, =0x08000020007D
124	msr	CPUPCR_EL3, x0
125	isb
126workaround_reset_end neoverse_n1, ERRATUM(1542419)
127
128check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
129
130workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
131	sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
132workaround_reset_end neoverse_n1, ERRATUM(1868343)
133
134check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
135
136workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
137	mov	x0, #3
138	msr	S3_6_C15_C8_0, x0
139	ldr	x0, =0x10E3900002
140	msr	S3_6_C15_C8_2, x0
141	ldr	x0, =0x10FFF00083
142	msr	S3_6_C15_C8_3, x0
143	ldr	x0, =0x2001003FF
144	msr	S3_6_C15_C8_1, x0
145	mov	x0, #4
146	msr	S3_6_C15_C8_0, x0
147	ldr	x0, =0x10E3800082
148	msr	S3_6_C15_C8_2, x0
149	ldr	x0, =0x10FFF00083
150	msr	S3_6_C15_C8_3, x0
151	ldr	x0, =0x2001003FF
152	msr	S3_6_C15_C8_1, x0
153	mov	x0, #5
154	msr	S3_6_C15_C8_0, x0
155	ldr	x0, =0x10E3800200
156	msr	S3_6_C15_C8_2, x0
157	ldr	x0, =0x10FFF003E0
158	msr	S3_6_C15_C8_3, x0
159	ldr	x0, =0x2001003FF
160	msr	S3_6_C15_C8_1, x0
161	isb
162workaround_reset_end neoverse_n1, ERRATUM(1946160)
163
164check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
165
166workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
167	/* dsb before isb of power down sequence */
168	dsb	sy
169workaround_runtime_end neoverse_n1, ERRATUM(2743102)
170
171check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
172
173workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
174#if IMAGE_BL31
175	/*
176	 * The Neoverse-N1 generic vectors are overridden to apply errata
177	 * mitigation on exception entry from lower ELs.
178	 */
179	override_vector_table wa_cve_vbar_neoverse_n1
180#endif /* IMAGE_BL31 */
181workaround_reset_end neoverse_n1, CVE(2022, 23960)
182
183check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
184
185/* --------------------------------------------------
186 * Disable speculative loads if Neoverse N1 supports
187 * SSBS.
188 *
189 * Shall clobber: x0.
190 * --------------------------------------------------
191 */
192func neoverse_n1_disable_speculative_loads
193	/* Check if the PE implements SSBS */
194	mrs	x0, id_aa64pfr1_el1
195	tst	x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
196	b.eq	1f
197
198	/* Disable speculative loads */
199	msr	SSBS, xzr
200
2011:
202	ret
203endfunc neoverse_n1_disable_speculative_loads
204
205cpu_reset_func_start neoverse_n1
206	bl neoverse_n1_disable_speculative_loads
207
208	/* Forces all cacheable atomic instructions to be near */
209	sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
210	isb
211
212#if ENABLE_FEAT_AMU
213	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
214	sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
215	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
216	sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
217	/* Enable group0 counters */
218	mov	x0, #NEOVERSE_N1_AMU_GROUP0_MASK
219	msr	CPUAMCNTENSET_EL0, x0
220#endif
221
222#if NEOVERSE_Nx_EXTERNAL_LLC
223	/* Some system may have External LLC, core needs to be made aware */
224	sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
225#endif
226cpu_reset_func_end neoverse_n1
227
228	/* ---------------------------------------------
229	 * HW will do the cache maintenance while powering down
230	 * ---------------------------------------------
231	 */
232func neoverse_n1_core_pwr_dwn
233	/* ---------------------------------------------
234	 * Enable CPU power down bit in power control register
235	 * ---------------------------------------------
236	 */
237	sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
238
239	apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
240
241	isb
242	ret
243endfunc neoverse_n1_core_pwr_dwn
244
245errata_report_shim neoverse_n1
246
247/*
248 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
249 * inner-shareable invalidation to an arbitrary address followed by a DSB.
250 *
251 * x1: Exception Syndrome
252 */
253func neoverse_n1_errata_ic_trap_handler
254	cmp	x1, #NEOVERSE_N1_EC_IC_TRAP
255	b.ne	1f
256	tlbi	vae3is, xzr
257	dsb	sy
258
259	# Skip the IC instruction itself
260	mrs     x3, elr_el3
261	add     x3, x3, #4
262	msr     elr_el3, x3
263
264	ldp	x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
265	ldp	x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
266	ldp	x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
267	ldr	x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
268
269	/*
270	 * Issue Error Synchronization Barrier to synchronize SErrors before
271	 * exiting EL3. We're running with EAs unmasked, so any synchronized
272	 * errors would be taken immediately; therefore no need to inspect
273	 * DISR_EL1 register.
274	 */
275	esb
276	exception_return
2771:
278	ret
279endfunc neoverse_n1_errata_ic_trap_handler
280
281	/* ---------------------------------------------
282	 * This function provides neoverse_n1 specific
283	 * register information for crash reporting.
284	 * It needs to return with x6 pointing to
285	 * a list of register names in ascii and
286	 * x8 - x15 having values of registers to be
287	 * reported.
288	 * ---------------------------------------------
289	 */
290.section .rodata.neoverse_n1_regs, "aS"
291neoverse_n1_regs:  /* The ascii list of register names to be reported */
292	.asciz	"cpuectlr_el1", ""
293
294func neoverse_n1_cpu_reg_dump
295	adr	x6, neoverse_n1_regs
296	mrs	x8, NEOVERSE_N1_CPUECTLR_EL1
297	ret
298endfunc neoverse_n1_cpu_reg_dump
299
300declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
301	neoverse_n1_reset_func, \
302	neoverse_n1_errata_ic_trap_handler, \
303	neoverse_n1_core_pwr_dwn
304