1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL2_H 8 #define CONTEXT_EL2_H 9 10 #ifndef __ASSEMBLER__ 11 /******************************************************************************* 12 * EL2 Registers: 13 * AArch64 EL2 system register context structure for preserving the 14 * architectural state during world switches. 15 ******************************************************************************/ 16 #if CTX_INCLUDE_EL2_REGS 17 typedef struct el2_common_regs { 18 uint64_t actlr_el2; 19 uint64_t afsr0_el2; 20 uint64_t afsr1_el2; 21 uint64_t amair_el2; 22 uint64_t cnthctl_el2; 23 uint64_t cntvoff_el2; 24 uint64_t cptr_el2; 25 uint64_t dbgvcr32_el2; 26 uint64_t elr_el2; 27 uint64_t esr_el2; 28 uint64_t far_el2; 29 uint64_t hacr_el2; 30 uint64_t hcr_el2; 31 uint64_t hpfar_el2; 32 uint64_t hstr_el2; 33 uint64_t icc_sre_el2; 34 uint64_t ich_hcr_el2; 35 uint64_t ich_vmcr_el2; 36 uint64_t mair_el2; 37 uint64_t mdcr_el2; 38 uint64_t pmscr_el2; 39 uint64_t sctlr_el2; 40 uint64_t spsr_el2; 41 uint64_t sp_el2; 42 uint64_t tcr_el2; 43 uint64_t tpidr_el2; 44 uint64_t ttbr0_el2; 45 uint64_t vbar_el2; 46 uint64_t vmpidr_el2; 47 uint64_t vpidr_el2; 48 uint64_t vtcr_el2; 49 uint64_t vttbr_el2; 50 } el2_common_regs_t; 51 52 typedef struct el2_mte2_regs { 53 uint64_t tfsr_el2; 54 } el2_mte2_regs_t; 55 56 typedef struct el2_fgt_regs { 57 uint64_t hdfgrtr_el2; 58 uint64_t hafgrtr_el2; 59 uint64_t hdfgwtr_el2; 60 uint64_t hfgitr_el2; 61 uint64_t hfgrtr_el2; 62 uint64_t hfgwtr_el2; 63 } el2_fgt_regs_t; 64 65 typedef struct el2_ecv_regs { 66 uint64_t cntpoff_el2; 67 } el2_ecv_regs_t; 68 69 typedef struct el2_vhe_regs { 70 uint64_t contextidr_el2; 71 uint64_t ttbr1_el2; 72 } el2_vhe_regs_t; 73 74 typedef struct el2_ras_regs { 75 uint64_t vdisr_el2; 76 uint64_t vsesr_el2; 77 } el2_ras_regs_t; 78 79 typedef struct el2_neve_regs { 80 uint64_t vncr_el2; 81 } el2_neve_regs_t; 82 83 typedef struct el2_trf_regs { 84 uint64_t trfcr_el2; 85 } el2_trf_regs_t; 86 87 typedef struct el2_csv2_regs { 88 uint64_t scxtnum_el2; 89 } el2_csv2_regs_t; 90 91 typedef struct el2_hcx_regs { 92 uint64_t hcrx_el2; 93 } el2_hcx_regs_t; 94 95 typedef struct el2_tcr2_regs { 96 uint64_t tcr2_el2; 97 } el2_tcr2_regs_t; 98 99 typedef struct el2_sxpoe_regs { 100 uint64_t por_el2; 101 } el2_sxpoe_regs_t; 102 103 typedef struct el2_sxpie_regs { 104 uint64_t pire0_el2; 105 uint64_t pir_el2; 106 } el2_sxpie_regs_t; 107 108 typedef struct el2_s2pie_regs { 109 uint64_t s2pir_el2; 110 } el2_s2pie_regs_t; 111 112 typedef struct el2_gcs_regs { 113 uint64_t gcscr_el2; 114 uint64_t gcspr_el2; 115 } el2_gcs_regs_t; 116 117 typedef struct el2_sysregs { 118 119 el2_common_regs_t common; 120 121 #if ENABLE_FEAT_MTE2 122 el2_mte2_regs_t mte2; 123 #endif 124 125 #if ENABLE_FEAT_FGT 126 el2_fgt_regs_t fgt; 127 #endif 128 129 #if ENABLE_FEAT_ECV 130 el2_ecv_regs_t ecv; 131 #endif 132 133 #if ENABLE_FEAT_VHE 134 el2_vhe_regs_t vhe; 135 #endif 136 137 #if ENABLE_FEAT_RAS 138 el2_ras_regs_t ras; 139 #endif 140 141 #if CTX_INCLUDE_NEVE_REGS 142 el2_neve_regs_t neve; 143 #endif 144 145 #if ENABLE_TRF_FOR_NS 146 el2_trf_regs_t trf; 147 #endif 148 149 #if ENABLE_FEAT_CSV2_2 150 el2_csv2_regs_t csv2; 151 #endif 152 153 #if ENABLE_FEAT_HCX 154 el2_hcx_regs_t hcx; 155 #endif 156 157 #if ENABLE_FEAT_TCR2 158 el2_tcr2_regs_t tcr2; 159 #endif 160 161 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 162 el2_sxpoe_regs_t sxpoe; 163 #endif 164 165 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 166 el2_sxpie_regs_t sxpie; 167 #endif 168 169 #if ENABLE_FEAT_S2PIE 170 el2_s2pie_regs_t s2pie; 171 #endif 172 173 #if ENABLE_FEAT_GCS 174 el2_gcs_regs_t gcs; 175 #endif 176 177 } el2_sysregs_t; 178 179 /* 180 * Macros to access members related to individual features of the el2_sysregs_t 181 * structures. 182 */ 183 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) 184 185 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 186 = (uint64_t) (val)) 187 188 #if ENABLE_FEAT_MTE2 189 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 190 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 191 = (uint64_t) (val)) 192 #else 193 #define read_el2_ctx_mte2(ctx, reg) ULL(0) 194 #define write_el2_ctx_mte2(ctx, reg, val) 195 #endif /* ENABLE_FEAT_MTE2 */ 196 197 #if ENABLE_FEAT_FGT 198 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) 199 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ 200 = (uint64_t) (val)) 201 #else 202 #define read_el2_ctx_fgt(ctx, reg) ULL(0) 203 #define write_el2_ctx_fgt(ctx, reg, val) 204 #endif /* ENABLE_FEAT_FGT */ 205 206 #if ENABLE_FEAT_ECV 207 #define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) 208 #define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ 209 = (uint64_t) (val)) 210 #else 211 #define read_el2_ctx_ecv(ctx, reg) ULL(0) 212 #define write_el2_ctx_ecv(ctx, reg, val) 213 #endif /* ENABLE_FEAT_ECV */ 214 215 #if ENABLE_FEAT_VHE 216 #define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) 217 #define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ 218 = (uint64_t) (val)) 219 #else 220 #define read_el2_ctx_vhe(ctx, reg) ULL(0) 221 #define write_el2_ctx_vhe(ctx, reg, val) 222 #endif /* ENABLE_FEAT_VHE */ 223 224 #if ENABLE_FEAT_RAS 225 #define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) 226 #define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 227 = (uint64_t) (val)) 228 #else 229 #define read_el2_ctx_ras(ctx, reg) ULL(0) 230 #define write_el2_ctx_ras(ctx, reg, val) 231 #endif /* ENABLE_FEAT_RAS */ 232 233 #if CTX_INCLUDE_NEVE_REGS 234 #define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) 235 #define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ 236 = (uint64_t) (val)) 237 #else 238 #define read_el2_ctx_neve(ctx, reg) ULL(0) 239 #define write_el2_ctx_neve(ctx, reg, val) 240 #endif /* CTX_INCLUDE_NEVE_REGS */ 241 242 #if ENABLE_TRF_FOR_NS 243 #define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) 244 #define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 245 = (uint64_t) (val)) 246 #else 247 #define read_el2_ctx_trf(ctx, reg) ULL(0) 248 #define write_el2_ctx_trf(ctx, reg, val) 249 #endif /* ENABLE_TRF_FOR_NS */ 250 251 #if ENABLE_FEAT_CSV2_2 252 #define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) 253 #define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ 254 = (uint64_t) (val)) 255 #else 256 #define read_el2_ctx_csv2_2(ctx, reg) ULL(0) 257 #define write_el2_ctx_csv2_2(ctx, reg, val) 258 #endif /* ENABLE_FEAT_CSV2_2 */ 259 260 #if ENABLE_FEAT_HCX 261 #define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) 262 #define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ 263 = (uint64_t) (val)) 264 #else 265 #define read_el2_ctx_hcx(ctx, reg) ULL(0) 266 #define write_el2_ctx_hcx(ctx, reg, val) 267 #endif /* ENABLE_FEAT_HCX */ 268 269 #if ENABLE_FEAT_TCR2 270 #define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 271 #define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 272 = (uint64_t) (val)) 273 #else 274 #define read_el2_ctx_tcr2(ctx, reg) ULL(0) 275 #define write_el2_ctx_tcr2(ctx, reg, val) 276 #endif /* ENABLE_FEAT_TCR2 */ 277 278 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 279 #define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) 280 #define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ 281 = (uint64_t) (val)) 282 #else 283 #define read_el2_ctx_sxpoe(ctx, reg) ULL(0) 284 #define write_el2_ctx_sxpoe(ctx, reg, val) 285 #endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ 286 287 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 288 #define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) 289 #define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ 290 = (uint64_t) (val)) 291 #else 292 #define read_el2_ctx_sxpie(ctx, reg) ULL(0) 293 #define write_el2_ctx_sxpie(ctx, reg, val) 294 #endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ 295 296 #if ENABLE_FEAT_S2PIE 297 #define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) 298 #define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ 299 = (uint64_t) (val)) 300 #else 301 #define read_el2_ctx_s2pie(ctx, reg) ULL(0) 302 #define write_el2_ctx_s2pie(ctx, reg, val) 303 #endif /* ENABLE_FEAT_S2PIE */ 304 305 #if ENABLE_FEAT_GCS 306 #define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 307 #define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 308 = (uint64_t) (val)) 309 #else 310 #define read_el2_ctx_gcs(ctx, reg) ULL(0) 311 #define write_el2_ctx_gcs(ctx, reg, val) 312 #endif /* ENABLE_FEAT_GCS */ 313 314 #endif /* CTX_INCLUDE_EL2_REGS */ 315 /******************************************************************************/ 316 317 #endif /* __ASSEMBLER__ */ 318 319 #endif /* CONTEXT_EL2_H */ 320