1 /*
2  * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_V3_H
8 #define NEOVERSE_V3_H
9 
10 
11 #define NEOVERSE_V3_VNAE_MIDR				U(0x410FD830)
12 #define NEOVERSE_V3_MIDR				U(0x410FD840)
13 
14 /* Neoverse V3 loop count for CVE-2022-23960 mitigation */
15 #define NEOVERSE_V3_BHB_LOOP_COUNT			U(132)
16 
17 /*******************************************************************************
18  * CPU Extended Control register specific definitions.
19  ******************************************************************************/
20 #define NEOVERSE_V3_CPUECTLR_EL1				S3_0_C15_C1_4
21 
22 /*******************************************************************************
23  * CPU Power Control register specific definitions
24  ******************************************************************************/
25 #define NEOVERSE_V3_CPUPWRCTLR_EL1			S3_0_C15_C2_7
26 #define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		U(1)
27 
28 #endif /* NEOVERSE_V3_H */
29