1 /*
2  * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef NEOVERSE_N3_H
8 #define NEOVERSE_N3_H
9 
10 #define NEOVERSE_N3_MIDR				U(0x410FD8E0)
11 
12 /*******************************************************************************
13  * CPU Extended Control register specific definitions
14  ******************************************************************************/
15 #define NEOVERSE_N3_CPUECTLR_EL1			S3_0_C15_C1_4
16 #define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT		(ULL(1) << 0)
17 
18 /*******************************************************************************
19  * CPU Power Control register specific definitions
20  ******************************************************************************/
21 #define NEOVERSE_N3_CPUPWRCTLR_EL1			S3_0_C15_C2_7
22 #define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
23 
24 #endif /* NEOVERSE_N3_H */
25