1 /* 2 * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N2_H 8 #define NEOVERSE_N2_H 9 10 /* Neoverse N2 ID register for revision r0p0 */ 11 #define NEOVERSE_N2_MIDR U(0x410FD490) 12 13 /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 14 #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Power control register 18 ******************************************************************************/ 19 #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 20 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 26 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 27 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 33 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 34 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 35 36 /******************************************************************************* 37 * CPU Auxiliary Control register 2 specific definitions. 38 ******************************************************************************/ 39 #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 40 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 41 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 42 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) 43 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 44 45 /******************************************************************************* 46 * CPU Auxiliary Control register 3 specific definitions. 47 ******************************************************************************/ 48 #define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 49 #define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) 50 51 /******************************************************************************* 52 * CPU Auxiliary Control register 5 specific definitions. 53 ******************************************************************************/ 54 #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 55 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) 56 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) 57 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 58 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 59 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 60 61 /******************************************************************************* 62 * CPU Auxiliary Control register specific definitions. 63 ******************************************************************************/ 64 #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 65 #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 66 #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 67 #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 68 #define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) 69 #define CPUECTLR2_EL1_TXREQ_LSB U(0) 70 #define CPUECTLR2_EL1_TXREQ_WIDTH U(3) 71 72 #endif /* NEOVERSE_N2_H */ 73