1 /* 2 * Copyright (C) 2022-2023 Nuvoton Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __NPCM845x_GCR_H_ 8 #define __NPCM845x_GCR_H_ 9 10 struct npcm845x_gcr { 11 unsigned int pdid; 12 unsigned int pwron; 13 unsigned int swstrps; 14 unsigned int rsvd1[2]; 15 unsigned int miscpe; 16 unsigned int spldcnt; 17 unsigned int rsvd2[1]; 18 unsigned int flockr2; 19 unsigned int flockr3; 20 unsigned int rsvd3[3]; 21 unsigned int a35_mode; 22 unsigned int spswc; 23 unsigned int intcr; 24 unsigned int intsr; 25 unsigned int obscr1; 26 unsigned int obsdr1; 27 unsigned int rsvd4[1]; 28 unsigned int hifcr; 29 unsigned int rsvd5[3]; 30 unsigned int intcr2; 31 unsigned int rsvd6[1]; 32 unsigned int srcnt; 33 unsigned int ressr; 34 unsigned int rlockr1; 35 unsigned int flockr1; 36 unsigned int dscnt; 37 unsigned int mdlr; 38 unsigned int scrpad_c; 39 unsigned int scrpad_b; 40 unsigned int rsvd7[4]; 41 unsigned int daclvlr; 42 unsigned int intcr3; 43 unsigned int pcirctl; 44 unsigned int rsvd8[2]; 45 unsigned int vsintr; 46 unsigned int rsvd9[1]; 47 unsigned int sd2sur1; 48 unsigned int sd2sur2; 49 unsigned int sd2irv3; 50 unsigned int intcr4; 51 unsigned int obscr2; 52 unsigned int obsdr2; 53 unsigned int rsvd10[5]; 54 unsigned int i2csegsel; 55 unsigned int i2csegctl; 56 unsigned int vsrcr; 57 unsigned int mlockr; 58 unsigned int rsvd11[8]; 59 unsigned int etsr; 60 unsigned int dft1r; 61 unsigned int dft2r; 62 unsigned int dft3r; 63 unsigned int edffsr; 64 unsigned int rsvd12[1]; 65 unsigned int intcrpce3; 66 unsigned int intcrpce2; 67 unsigned int intcrpce0; 68 unsigned int intcrpce1; 69 unsigned int dactest; 70 unsigned int scrpad; 71 unsigned int usb1phyctl; 72 unsigned int usb2phyctl; 73 unsigned int usb3phyctl; 74 unsigned int intsr2; 75 unsigned int intcrpce2b; 76 unsigned int intcrpce0b; 77 unsigned int intcrpce1b; 78 unsigned int intcrpce3b; 79 unsigned int rsvd13[4]; 80 unsigned int intcrpce2c; 81 unsigned int intcrpce0c; 82 unsigned int intcrpce1c; 83 unsigned int intcrpce3c; 84 unsigned int rsvd14[40]; 85 unsigned int sd2irv4; 86 unsigned int sd2irv5; 87 unsigned int sd2irv6; 88 unsigned int sd2irv7; 89 unsigned int sd2irv8; 90 unsigned int sd2irv9; 91 unsigned int sd2irv10; 92 unsigned int sd2irv11; 93 unsigned int rsvd15[8]; 94 unsigned int mfsel1; 95 unsigned int mfsel2; 96 unsigned int mfsel3; 97 unsigned int mfsel4; 98 unsigned int mfsel5; 99 unsigned int mfsel6; 100 unsigned int mfsel7; 101 unsigned int rsvd16[1]; 102 unsigned int mfsel_lk1; 103 unsigned int mfsel_lk2; 104 unsigned int mfsel_lk3; 105 unsigned int mfsel_lk4; 106 unsigned int mfsel_lk5; 107 unsigned int mfsel_lk6; 108 unsigned int mfsel_lk7; 109 unsigned int rsvd17[1]; 110 unsigned int mfsel_set1; 111 unsigned int mfsel_set2; 112 unsigned int mfsel_set3; 113 unsigned int mfsel_set4; 114 unsigned int mfsel_set5; 115 unsigned int mfsel_set6; 116 unsigned int mfsel_set7; 117 unsigned int rsvd18[1]; 118 unsigned int mfsel_clr1; 119 unsigned int mfsel_clr2; 120 unsigned int mfsel_clr3; 121 unsigned int mfsel_clr4; 122 unsigned int mfsel_clr5; 123 unsigned int mfsel_clr6; 124 unsigned int mfsel_clr7; 125 }; 126 127 #endif 128