1 /* 2 * Copyright (c) 2017 - 2021, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8 #ifndef USBH_XHCI_REGS_H 9 #define USBH_XHCI_REGS_H 10 11 #include <lib/mmio.h> 12 #include <platform_def.h> 13 14 #define XHCI_LEN (8096U) 15 16 #define XHC_CPLIVER_OFFSET 0x000U 17 #define XHC_SPARAMS1_OFFSET 0x004U 18 #define XHC_SPARAMS2_OFFSET 0x008U 19 #define XHC_SPARAMS3_OFFSET 0x00cU 20 #define XHC_CPARAMS1_OFFSET 0x010U 21 #define XHC_DBOFF_OFFSET 0x014U 22 #define XHC_RTOFF_OFFSET 0x018U 23 #define XHC_CPARAMS2_OFFSET 0x01cU 24 #define XHC_USBCMD_OFFSET 0x020U 25 #define XHC_USBSTS_OFFSET 0x024U 26 #define XHC_PAGESIZE_OFFSET 0x028U 27 #define XHC_DNCTRL_OFFSET 0x034U 28 #define XHC_CRCRL_OFFSET 0x038U 29 #define XHC_CRCRH_OFFSET 0x03cU 30 #define XHC_DCBAAPL_OFFSET 0x050U 31 #define XHC_DCBAAPH_OFFSET 0x054U 32 #define XHC_CONFIG_OFFSET 0x058U 33 #define XHC_PORTSC1_OFFSET 0x420U 34 #define XHC_PORTPM1_OFFSET 0x424U 35 #define XHC_PORTLC1_OFFSET 0x428U 36 #define XHC_PORTSC2_OFFSET 0x430U 37 #define XHC_PORTPM2_OFFSET 0x434U 38 #define XHC_PORTLC2_OFFSET 0x43cU 39 #define XHC_PORTSC3_OFFSET 0x440U 40 #define XHC_PORTPM3_OFFSET 0x444U 41 #define XHC_PORTLI3_OFFSET 0x44cU 42 #define XHC_MFINDEX_OFFSET 0x4a0U 43 #define XHC_IMAN0_OFFSET 0x4c0U 44 #define XHC_IMOD0_OFFSET 0x4c4U 45 #define XHC_ERSTSZ0_OFFSET 0x4c8U 46 #define XHC_ERSTBAL0_OFFSET 0x4d0U 47 #define XHC_ERSTBAH0_OFFSET 0x4d4U 48 #define XHC_ERDPL0_OFFSET 0x4d8U 49 #define XHC_ERDPH0_OFFSET 0x4dcU 50 #define XHC_IMAN1_OFFSET 0x4e0U 51 #define XHC_IMOD1_OFFSET 0x4e4U 52 #define XHC_ERSTSZ1_OFFSET 0x4e8U 53 #define XHC_ERSTBAL1_OFFSET 0x4f0U 54 #define XHC_ERSTBAH1_OFFSET 0x4f4U 55 #define XHC_ERDPL1_OFFSET 0x4f8U 56 #define XHC_ERDPH1_OFFSET 0x4fcU 57 #define XHC_DBLCMD_OFFSET 0x8c0U 58 #define XHC_DBLDVX1_OFFSET 0x8c4U 59 #define XHC_DBLDVX2_OFFSET 0x8c8U 60 #define XHC_DBLDVX3_OFFSET 0x8ccU 61 #define XHC_DBLDVX4_OFFSET 0x8d0U 62 #define XHC_DBLDVX5_OFFSET 0x8d4U 63 #define XHC_DBLDVX6_OFFSET 0x8d8U 64 #define XHC_DBLDVX7_OFFSET 0x8dcU 65 #define XHC_DBLDVX8_OFFSET 0x8e0U 66 #define XHC_DBLDVX9_OFFSET 0x8e4U 67 #define XHC_DBLDVX10_OFFSET 0x8e8U 68 #define XHC_DBLDVX11_OFFSET 0x8ecU 69 #define XHC_DBLDVX12_OFFSET 0x8f0U 70 #define XHC_DBLDVX13_OFFSET 0x8f4U 71 #define XHC_DBLDVX14_OFFSET 0x8f8U 72 #define XHC_DBLDVX15_OFFSET 0x8fcU 73 #define XHC_DBLDVX16_OFFSET 0x900U 74 #define XHC_ECHSPT3_OFFSET 0x940U 75 #define XHC_PNSTR3_OFFSET 0x944U 76 #define XHC_PSUM3_OFFSET 0x948U 77 #define XHC_PTSLTYP3_OFFSET 0x94cU 78 #define XHC_ECHSPT2_OFFSET 0x950U 79 #define XHC_PNSTR2_OFFSET 0x954U 80 #define XHC_PSUM2_OFFSET 0x958U 81 #define XHC_PTSLTYP2_OFFSET 0x95cU 82 #define XHC_ECHRSVP_OFFSET 0x960U 83 #define XHC_ECHRSVI_OFFSET 0x968U 84 #define XHC_ECHRSVM_OFFSET 0xae8U 85 #define XHC_ECHRSVD_OFFSET 0xaf8U 86 #define XHC_ECHRSVO_OFFSET 0xb38U 87 #define XHC_ECHCTT_OFFSET 0xbf0U 88 #define XHC_CTTMTS0_OFFSET 0xbf8U 89 #define XHC_CTTMTS1_OFFSET 0xbfcU 90 #define XHC_ECHBIU_OFFSET 0xc00U 91 #define XHC_BIUSPC_OFFSET 0xc04U 92 #define XHC_AXIWRA_OFFSET 0xc08U 93 #define XHC_AXIRDA_OFFSET 0xc0cU 94 #define XHC_AXILPM_OFFSET 0xc10U 95 #define XHC_AXIQOS_OFFSET 0xc14U 96 #define XHC_ECHCSR_OFFSET 0xc20U 97 #define XHC_CSRSPC_OFFSET 0xc24U 98 #define XHC_ECHAIU_OFFSET 0xc30U 99 #define XHC_AIUDMA_OFFSET 0xc34U 100 #define XHC_AIUFLA_OFFSET 0xc38U 101 #define XHC_AIUCFG_OFFSET 0xc3cU 102 #define XHC_ECHFSC_OFFSET 0xc40U 103 #define XHC_FSCPOC_OFFSET 0xc54U 104 #define XHC_FSCGOC_OFFSET 0xc58U 105 #define XHC_FSCNOC_OFFSET 0xc5cU 106 #define XHC_FSCAIC_OFFSET 0xc60U 107 #define XHC_FSCPIC_OFFSET 0xc64U 108 #define XHC_FSCGIC_OFFSET 0xc68U 109 #define XHC_FSCNIC_OFFSET 0xc6cU 110 #define XHC_ECHPRT_OFFSET 0xc70U 111 #define XHC_PRTHSC_OFFSET 0xc78U 112 #define XHC_PRTHSR_OFFSET 0xc7cU 113 #define XHC_ECHRHS_OFFSET 0xc80U 114 #define XHC_RHSDES_OFFSET 0xc84U 115 #define XHC_RHSHSC0_OFFSET 0xc90U 116 #define XHC_RHSHSR0_OFFSET 0xc94U 117 #define XHC_RHSHSC1_OFFSET 0xc98U 118 #define XHC_RHSHSR1_OFFSET 0xc9cU 119 #define XHC_RHSHSC2_OFFSET 0xca0U 120 #define XHC_RHSHSR2_OFFSET 0xca4U 121 #define XHC_RHSHSC3_OFFSET 0xca8U 122 #define XHC_RHSHSR3_OFFSET 0xcacU 123 #define XHC_ECHSSP_OFFSET 0xcb0U 124 #define XHC_SSPVER_OFFSET 0xcb4U 125 #define XHC_SSPMGN_OFFSET 0xcb8U 126 #define XHC_ECHFSC2_OFFSET 0xcc0U 127 #define XHC_FSC2POC_OFFSET 0xcd4U 128 #define XHC_FSC2GOC_OFFSET 0xcd8U 129 #define XHC_FSC2NOC_OFFSET 0xcdcU 130 #define XHC_FSC2AIC_OFFSET 0xce0U 131 #define XHC_FSC2PIC_OFFSET 0xce4U 132 #define XHC_FSC2GIC_OFFSET 0xce8U 133 #define XHC_FSC2NIC_OFFSET 0xcecU 134 #define XHC_ECHPRT2_OFFSET 0xcf0U 135 #define XHC_PRT2HSC_OFFSET 0xcf8U 136 #define XHC_PRT2HSR_OFFSET 0xcfcU 137 #define XHC_ECHRH2_OFFSET 0xd00U 138 #define XHC_RH2DES_OFFSET 0xd04U 139 #define XHC_RH2HSC0_OFFSET 0xd10U 140 #define XHC_RH2HSR0_OFFSET 0xd14U 141 #define XHC_RH2HSC1_OFFSET 0xd18U 142 #define XHC_RH2HSR1_OFFSET 0xd1cU 143 #define XHC_RH2HSC2_OFFSET 0xd20U 144 #define XHC_RH2HSR2_OFFSET 0xd24U 145 #define XHC_RH2HSC3_OFFSET 0xd28U 146 #define XHC_RH2HSR3_OFFSET 0xd2cU 147 #define XHC_ECHU2P_OFFSET 0xd30U 148 #define XHC_U2PVER_OFFSET 0xd34U 149 #define XHC_U2PMGN_OFFSET 0xd38U 150 #define XHC_ECHRSV2_OFFSET 0xd40U 151 #define XHC_ECHIRA_OFFSET 0xf90U 152 #define XHC_IRAADR_OFFSET 0xf98U 153 #define XHC_IRADAT_OFFSET 0xf9cU 154 #define XHC_ECHHST_OFFSET 0xfa0U 155 #define XHC_HSTDBG_OFFSET 0xfa4U 156 #define XHC_HSTNPL_OFFSET 0xfa8U 157 #define XHC_HSTNPH_OFFSET 0xfacU 158 #define XHC_ECHRBV_OFFSET 0xfb0U 159 #define XHC_RBVPDT_OFFSET 0xfb4U 160 #define XHC_RBVMGN_OFFSET 0xfbcU 161 162 #define XHC_CPLIVER_BASE 0x000U 163 #define XHC_CPLIVER__IVH_L 31U 164 #define XHC_CPLIVER__IVH_R 24U 165 #define XHC_CPLIVER__IVH_WIDTH 8U 166 #define XHC_CPLIVER__IVH_RESETVALUE 0x01U 167 #define XHC_CPLIVER__IVL_L 23U 168 #define XHC_CPLIVER__IVL_R 16U 169 #define XHC_CPLIVER__IVL_WIDTH 8U 170 #define XHC_CPLIVER__IVL_RESETVALUE 0x10U 171 #define XHC_CPLIVER__reserved_L 15U 172 #define XHC_CPLIVER__reserved_R 8U 173 #define XHC_CPLIVER__reserved_WIDTH 8U 174 #define XHC_CPLIVER__reserved_RESETVALUE 0x00U 175 #define XHC_CPLIVER__CPL_L 7U 176 #define XHC_CPLIVER__CPL_R 0U 177 #define XHC_CPLIVER__CPL_WIDTH 8U 178 #define XHC_CPLIVER__CPL_RESETVALUE 0x00U 179 #define XHC_CPLIVER_WIDTH 32U 180 #define XHC_CPLIVER__WIDTH 32U 181 #define XHC_CPLIVER_ALL_L 31U 182 #define XHC_CPLIVER_ALL_R 0U 183 #define XHC_CPLIVER__ALL_L 31U 184 #define XHC_CPLIVER__ALL_R 0U 185 #define XHC_CPLIVER_DATAMASK 0xffffffffU 186 #define XHC_CPLIVER_RDWRMASK 0x00000000U 187 #define XHC_CPLIVER_RESETVALUE 0x01100000U 188 189 #define XHC_SPARAMS1_OFFSET 0x004U 190 #define XHC_SPARAMS1_BASE 0x004U 191 #define XHC_SPARAMS1__NPTS_L 31U 192 #define XHC_SPARAMS1__NPTS_R 24U 193 #define XHC_SPARAMS1__NPTS_WIDTH 8U 194 #define XHC_SPARAMS1__NPTS_RESETVALUE 0x00U 195 #define XHC_SPARAMS1__reserved_L 23U 196 #define XHC_SPARAMS1__reserved_R 19U 197 #define XHC_SPARAMS1__reserved_WIDTH 5U 198 #define XHC_SPARAMS1__reserved_RESETVALUE 0x0U 199 #define XHC_SPARAMS1__MITS_L 18U 200 #define XHC_SPARAMS1__MITS_R 8U 201 #define XHC_SPARAMS1__MITS_WIDTH 11U 202 #define XHC_SPARAMS1__MITS_RESETVALUE 0x1U 203 #define XHC_SPARAMS1__MSLS_L 7U 204 #define XHC_SPARAMS1__MSLS_R 0U 205 #define XHC_SPARAMS1__MSLS_WIDTH 8U 206 #define XHC_SPARAMS1__MSLS_RESETVALUE 0x00U 207 #define XHC_SPARAMS1_WIDTH 32U 208 #define XHC_SPARAMS1__WIDTH 32U 209 #define XHC_SPARAMS1_ALL_L 31U 210 #define XHC_SPARAMS1_ALL_R 0U 211 #define XHC_SPARAMS1__ALL_L 31U 212 #define XHC_SPARAMS1__ALL_R 0U 213 #define XHC_SPARAMS1_DATAMASK 0xffffffffU 214 #define XHC_SPARAMS1_RDWRMASK 0x00000000U 215 #define XHC_SPARAMS1_RESETVALUE 0x00000100U 216 217 #define XHC_SPARAMS2_OFFSET 0x008U 218 #define XHC_SPARAMS2_BASE 0x008U 219 #define XHC_SPARAMS2__MSPBSL_L 31U 220 #define XHC_SPARAMS2__MSPBSL_R 27U 221 #define XHC_SPARAMS2__MSPBSL_WIDTH 5U 222 #define XHC_SPARAMS2__MSPBSL_RESETVALUE 0x0U 223 #define XHC_SPARAMS2__SPR 26U 224 #define XHC_SPARAMS2__SPR_L 26U 225 #define XHC_SPARAMS2__SPR_R 26U 226 #define XHC_SPARAMS2__SPR_WIDTH 1U 227 #define XHC_SPARAMS2__SPR_RESETVALUE 0x1U 228 #define XHC_SPARAMS2__MSPBSH_L 25U 229 #define XHC_SPARAMS2__MSPBSH_R 21U 230 #define XHC_SPARAMS2__MSPBSH_WIDTH 5U 231 #define XHC_SPARAMS2__MSPBSH_RESETVALUE 0x0U 232 #define XHC_SPARAMS2__reserved_L 20U 233 #define XHC_SPARAMS2__reserved_R 8U 234 #define XHC_SPARAMS2__reserved_WIDTH 13U 235 #define XHC_SPARAMS2__reserved_RESETVALUE 0x0U 236 #define XHC_SPARAMS2__MERST_L 7U 237 #define XHC_SPARAMS2__MERST_R 4U 238 #define XHC_SPARAMS2__MERST_WIDTH 4U 239 #define XHC_SPARAMS2__MERST_RESETVALUE 0x0U 240 #define XHC_SPARAMS2__IST_L 3U 241 #define XHC_SPARAMS2__IST_R 0U 242 #define XHC_SPARAMS2__IST_WIDTH 4U 243 #define XHC_SPARAMS2__IST_RESETVALUE 0x0U 244 #define XHC_SPARAMS2_WIDTH 32U 245 #define XHC_SPARAMS2__WIDTH 32U 246 #define XHC_SPARAMS2_ALL_L 31U 247 #define XHC_SPARAMS2_ALL_R 0U 248 #define XHC_SPARAMS2__ALL_L 31U 249 #define XHC_SPARAMS2__ALL_R 0U 250 #define XHC_SPARAMS2_DATAMASK 0xffffffffU 251 #define XHC_SPARAMS2_RDWRMASK 0x00000000U 252 #define XHC_SPARAMS2_RESETVALUE 0x04000000U 253 254 #define XHC_SPARAMS3_OFFSET 0x00cU 255 #define XHC_SPARAMS3_BASE 0x00cU 256 #define XHC_SPARAMS3__U2L_L 31U 257 #define XHC_SPARAMS3__U2L_R 16U 258 #define XHC_SPARAMS3__U2L_WIDTH 16U 259 #define XHC_SPARAMS3__U2L_RESETVALUE 0x0000U 260 #define XHC_SPARAMS3__reserved_L 15U 261 #define XHC_SPARAMS3__reserved_R 8U 262 #define XHC_SPARAMS3__reserved_WIDTH 8U 263 #define XHC_SPARAMS3__reserved_RESETVALUE 0x00U 264 #define XHC_SPARAMS3__U1L_L 7U 265 #define XHC_SPARAMS3__U1L_R 0U 266 #define XHC_SPARAMS3__U1L_WIDTH 8U 267 #define XHC_SPARAMS3__U1L_RESETVALUE 0x00U 268 #define XHC_SPARAMS3_WIDTH 32U 269 #define XHC_SPARAMS3__WIDTH 32U 270 #define XHC_SPARAMS3_ALL_L 31U 271 #define XHC_SPARAMS3_ALL_R 0U 272 #define XHC_SPARAMS3__ALL_L 31U 273 #define XHC_SPARAMS3__ALL_R 0U 274 #define XHC_SPARAMS3_DATAMASK 0xffffffffU 275 #define XHC_SPARAMS3_RDWRMASK 0x00000000U 276 #define XHC_SPARAMS3_RESETVALUE 0x00000000U 277 278 #define XHC_CPARAMS1_OFFSET 0x010U 279 #define XHC_CPARAMS1_BASE 0x010U 280 #define XHC_CPARAMS1__XECP_L 31U 281 #define XHC_CPARAMS1__XECP_R 16U 282 #define XHC_CPARAMS1__XECP_WIDTH 16U 283 #define XHC_CPARAMS1__XECP_RESETVALUE 0x0000U 284 #define XHC_CPARAMS1__MPSA_L 15U 285 #define XHC_CPARAMS1__MPSA_R 12U 286 #define XHC_CPARAMS1__MPSA_WIDTH 4U 287 #define XHC_CPARAMS1__MPSA_RESETVALUE 0x0U 288 #define XHC_CPARAMS1__CFC 11U 289 #define XHC_CPARAMS1__CFC_L 11U 290 #define XHC_CPARAMS1__CFC_R 11U 291 #define XHC_CPARAMS1__CFC_WIDTH 1U 292 #define XHC_CPARAMS1__CFC_RESETVALUE 0x0U 293 #define XHC_CPARAMS1__SEC 10U 294 #define XHC_CPARAMS1__SEC_L 10U 295 #define XHC_CPARAMS1__SEC_R 10U 296 #define XHC_CPARAMS1__SEC_WIDTH 1U 297 #define XHC_CPARAMS1__SEC_RESETVALUE 0x0U 298 #define XHC_CPARAMS1__SPC 9U 299 #define XHC_CPARAMS1__SPC_L 9U 300 #define XHC_CPARAMS1__SPC_R 9U 301 #define XHC_CPARAMS1__SPC_WIDTH 1U 302 #define XHC_CPARAMS1__SPC_RESETVALUE 0x0U 303 #define XHC_CPARAMS1__PAE 8U 304 #define XHC_CPARAMS1__PAE_L 8U 305 #define XHC_CPARAMS1__PAE_R 8U 306 #define XHC_CPARAMS1__PAE_WIDTH 1U 307 #define XHC_CPARAMS1__PAE_RESETVALUE 0x1U 308 #define XHC_CPARAMS1__NSS 7U 309 #define XHC_CPARAMS1__NSS_L 7U 310 #define XHC_CPARAMS1__NSS_R 7U 311 #define XHC_CPARAMS1__NSS_WIDTH 1U 312 #define XHC_CPARAMS1__NSS_RESETVALUE 0x0U 313 #define XHC_CPARAMS1__LTC 6U 314 #define XHC_CPARAMS1__LTC_L 6U 315 #define XHC_CPARAMS1__LTC_R 6U 316 #define XHC_CPARAMS1__LTC_WIDTH 1U 317 #define XHC_CPARAMS1__LTC_RESETVALUE 0x1U 318 #define XHC_CPARAMS1__LRC 5U 319 #define XHC_CPARAMS1__LRC_L 5U 320 #define XHC_CPARAMS1__LRC_R 5U 321 #define XHC_CPARAMS1__LRC_WIDTH 1U 322 #define XHC_CPARAMS1__LRC_RESETVALUE 0x0U 323 #define XHC_CPARAMS1__PIND 4U 324 #define XHC_CPARAMS1__PIND_L 4U 325 #define XHC_CPARAMS1__PIND_R 4U 326 #define XHC_CPARAMS1__PIND_WIDTH 1U 327 #define XHC_CPARAMS1__PIND_RESETVALUE 0x0U 328 329 #define XHC_CPARAMS1__PPC_L 3U 330 #define XHC_CPARAMS1__PPC_R 3U 331 #define XHC_CPARAMS1__PPC_WIDTH 1U 332 #define XHC_CPARAMS1__PPC_RESETVALUE 0x0U 333 #define XHC_CPARAMS1__CSZ 2U 334 #define XHC_CPARAMS1__CSZ_L 2U 335 #define XHC_CPARAMS1__CSZ_R 2U 336 #define XHC_CPARAMS1__CSZ_WIDTH 1U 337 #define XHC_CPARAMS1__CSZ_RESETVALUE 0x1U 338 #define XHC_CPARAMS1__BNC 1U 339 #define XHC_CPARAMS1__BNC_L 1U 340 #define XHC_CPARAMS1__BNC_R 1U 341 #define XHC_CPARAMS1__BNC_WIDTH 1U 342 #define XHC_CPARAMS1__BNC_RESETVALUE 0x0U 343 #define XHC_CPARAMS1__AC64 0U 344 #define XHC_CPARAMS1__AC64_L 0U 345 #define XHC_CPARAMS1__AC64_R 0U 346 #define XHC_CPARAMS1__AC64_WIDTH 1U 347 #define XHC_CPARAMS1__AC64_RESETVALUE 0x0U 348 #define XHC_CPARAMS1_WIDTH 32U 349 #define XHC_CPARAMS1__WIDTH 32U 350 #define XHC_CPARAMS1_ALL_L 31U 351 #define XHC_CPARAMS1_ALL_R 0U 352 #define XHC_CPARAMS1__ALL_L 31U 353 #define XHC_CPARAMS1__ALL_R 0U 354 #define XHC_CPARAMS1_DATAMASK 0xffffffffU 355 #define XHC_CPARAMS1_RDWRMASK 0x00000000U 356 #define XHC_CPARAMS1_RESETVALUE 0x00000144U 357 358 #define XHC_DBOFF_OFFSET 0x014U 359 #define XHC_DBOFF_BASE 0x014U 360 #define XHC_DBOFF__DBO_L 15U 361 #define XHC_DBOFF__DBO_R 2U 362 #define XHC_DBOFF__DBO_WIDTH 14U 363 #define XHC_DBOFF__DBO_RESETVALUE 0x0U 364 #define XHC_DBOFF__reserved_L 1U 365 #define XHC_DBOFF__reserved_R 0U 366 #define XHC_DBOFF__reserved_WIDTH 2U 367 #define XHC_DBOFF__reserved_RESETVALUE 0x0U 368 #define XHC_DBOFF__RESERVED_L 31U 369 #define XHC_DBOFF__RESERVED_R 16U 370 #define XHC_DBOFF_WIDTH 16U 371 #define XHC_DBOFF__WIDTH 16U 372 #define XHC_DBOFF_ALL_L 15U 373 #define XHC_DBOFF_ALL_R 0U 374 #define XHC_DBOFF__ALL_L 15U 375 #define XHC_DBOFF__ALL_R 0U 376 #define XHC_DBOFF_DATAMASK 0x0000ffffU 377 #define XHC_DBOFF_RDWRMASK 0xffff0000U 378 #define XHC_DBOFF_RESETVALUE 0x0000U 379 380 #define XHC_RTOFF_OFFSET 0x018U 381 #define XHC_RTOFF_BASE 0x018U 382 #define XHC_RTOFF__RTO_L 15U 383 #define XHC_RTOFF__RTO_R 5U 384 #define XHC_RTOFF__RTO_WIDTH 11U 385 #define XHC_RTOFF__RTO_RESETVALUE 0x0U 386 #define XHC_RTOFF__reserved_L 4U 387 #define XHC_RTOFF__reserved_R 0U 388 #define XHC_RTOFF__reserved_WIDTH 5U 389 #define XHC_RTOFF__reserved_RESETVALUE 0x0U 390 #define XHC_RTOFF__RESERVED_L 31U 391 #define XHC_RTOFF__RESERVED_R 16U 392 #define XHC_RTOFF_WIDTH 16U 393 #define XHC_RTOFF__WIDTH 16U 394 #define XHC_RTOFF_ALL_L 15U 395 #define XHC_RTOFF_ALL_R 0U 396 #define XHC_RTOFF__ALL_L 15U 397 #define XHC_RTOFF__ALL_R 0U 398 #define XHC_RTOFF_DATAMASK 0x0000ffffU 399 #define XHC_RTOFF_RDWRMASK 0xffff0000U 400 #define XHC_RTOFF_RESETVALUE 0x0000U 401 402 #define XHC_CPARAMS2_OFFSET 0x01cU 403 #define XHC_CPARAMS2_BASE 0x01cU 404 #define XHC_CPARAMS2__reserved_L 31U 405 #define XHC_CPARAMS2__reserved_R 6U 406 #define XHC_CPARAMS2__reserved_WIDTH 26U 407 #define XHC_CPARAMS2__reserved_RESETVALUE 0x0U 408 #define XHC_CPARAMS2__CIC 5U 409 #define XHC_CPARAMS2__CIC_L 5U 410 #define XHC_CPARAMS2__CIC_R 5U 411 #define XHC_CPARAMS2__CIC_WIDTH 1U 412 #define XHC_CPARAMS2__CIC_RESETVALUE 0x0U 413 #define XHC_CPARAMS2__LEC 4U 414 #define XHC_CPARAMS2__LEC_L 4U 415 #define XHC_CPARAMS2__LEC_R 4U 416 #define XHC_CPARAMS2__LEC_WIDTH 1U 417 #define XHC_CPARAMS2__LEC_RESETVALUE 0x0U 418 #define XHC_CPARAMS2__CTC 3U 419 #define XHC_CPARAMS2__CTC_L 3U 420 #define XHC_CPARAMS2__CTC_R 3U 421 #define XHC_CPARAMS2__CTC_WIDTH 1U 422 #define XHC_CPARAMS2__CTC_RESETVALUE 0x0U 423 #define XHC_CPARAMS2__FSC 2U 424 #define XHC_CPARAMS2__FSC_L 2U 425 #define XHC_CPARAMS2__FSC_R 2U 426 #define XHC_CPARAMS2__FSC_WIDTH 1U 427 #define XHC_CPARAMS2__FSC_RESETVALUE 0x0U 428 #define XHC_CPARAMS2__CMC 1U 429 #define XHC_CPARAMS2__CMC_L 1U 430 #define XHC_CPARAMS2__CMC_R 1U 431 #define XHC_CPARAMS2__CMC_WIDTH 1U 432 #define XHC_CPARAMS2__CMC_RESETVALUE 0x0U 433 #define XHC_CPARAMS2__U3C 0U 434 #define XHC_CPARAMS2__U3C_L 0U 435 #define XHC_CPARAMS2__U3C_R 0U 436 #define XHC_CPARAMS2__U3C_WIDTH 1U 437 #define XHC_CPARAMS2__U3C_RESETVALUE 0x0U 438 #define XHC_CPARAMS2_WIDTH 32U 439 #define XHC_CPARAMS2__WIDTH 32U 440 #define XHC_CPARAMS2_ALL_L 31U 441 #define XHC_CPARAMS2_ALL_R 0U 442 #define XHC_CPARAMS2__ALL_L 31U 443 #define XHC_CPARAMS2__ALL_R 0U 444 #define XHC_CPARAMS2_DATAMASK 0xffffffffU 445 #define XHC_CPARAMS2_RDWRMASK 0x00000000U 446 #define XHC_CPARAMS2_RESETVALUE 0x00000000U 447 448 #define XHC_USBCMD_OFFSET 0x020U 449 #define XHC_USBCMD_BASE 0x020U 450 #define XHC_USBCMD__CME 13U 451 #define XHC_USBCMD__CME_L 13U 452 #define XHC_USBCMD__CME_R 13U 453 #define XHC_USBCMD__CME_WIDTH 1U 454 #define XHC_USBCMD__CME_RESETVALUE 0x0U 455 #define XHC_USBCMD__SPE 12U 456 #define XHC_USBCMD__SPE_L 12U 457 #define XHC_USBCMD__SPE_R 12U 458 #define XHC_USBCMD__SPE_WIDTH 1U 459 #define XHC_USBCMD__SPE_RESETVALUE 0x0U 460 #define XHC_USBCMD__EU3S 11U 461 #define XHC_USBCMD__EU3S_L 11U 462 #define XHC_USBCMD__EU3S_R 11U 463 #define XHC_USBCMD__EU3S_WIDTH 1U 464 #define XHC_USBCMD__EU3S_RESETVALUE 0x0U 465 #define XHC_USBCMD__EWE 10U 466 #define XHC_USBCMD__EWE_L 10U 467 #define XHC_USBCMD__EWE_R 10U 468 #define XHC_USBCMD__EWE_WIDTH 1U 469 #define XHC_USBCMD__EWE_RESETVALUE 0x0U 470 #define XHC_USBCMD__CRS 9U 471 #define XHC_USBCMD__CRS_L 9U 472 #define XHC_USBCMD__CRS_R 9U 473 #define XHC_USBCMD__CRS_WIDTH 1U 474 #define XHC_USBCMD__CRS_RESETVALUE 0x0U 475 #define XHC_USBCMD__CSS 8U 476 #define XHC_USBCMD__CSS_L 8U 477 #define XHC_USBCMD__CSS_R 8U 478 #define XHC_USBCMD__CSS_WIDTH 1U 479 #define XHC_USBCMD__CSS_RESETVALUE 0x0U 480 #define XHC_USBCMD__LRST 7U 481 #define XHC_USBCMD__LRST_L 7U 482 #define XHC_USBCMD__LRST_R 7U 483 #define XHC_USBCMD__LRST_WIDTH 1U 484 #define XHC_USBCMD__LRST_RESETVALUE 0x0U 485 #define XHC_USBCMD__reserved_L 6U 486 #define XHC_USBCMD__reserved_R 4U 487 #define XHC_USBCMD__reserved_WIDTH 3U 488 #define XHC_USBCMD__reserved_RESETVALUE 0x0U 489 #define XHC_USBCMD__HSEE 3U 490 #define XHC_USBCMD__HSEE_L 3U 491 #define XHC_USBCMD__HSEE_R 3U 492 #define XHC_USBCMD__HSEE_WIDTH 1U 493 #define XHC_USBCMD__HSEE_RESETVALUE 0x0U 494 #define XHC_USBCMD__INTE 2U 495 #define XHC_USBCMD__INTE_L 2U 496 #define XHC_USBCMD__INTE_R 2U 497 #define XHC_USBCMD__INTE_WIDTH 1U 498 #define XHC_USBCMD__INTE_RESETVALUE 0x0U 499 #define XHC_USBCMD__RST 1U 500 #define XHC_USBCMD__RST_L 1U 501 #define XHC_USBCMD__RST_R 1U 502 #define XHC_USBCMD__RST_WIDTH 1U 503 #define XHC_USBCMD__RST_RESETVALUE 0x0U 504 #define XHC_USBCMD__RS 0U 505 #define XHC_USBCMD__RS_L 0U 506 #define XHC_USBCMD__RS_R 0U 507 #define XHC_USBCMD__RS_WIDTH 1U 508 #define XHC_USBCMD__RS_RESETVALUE 0x0U 509 #define XHC_USBCMD__RESERVED_L 31U 510 #define XHC_USBCMD__RESERVED_R 14U 511 #define XHC_USBCMD_WIDTH 14U 512 #define XHC_USBCMD__WIDTH 14U 513 #define XHC_USBCMD_ALL_L 13U 514 #define XHC_USBCMD_ALL_R 0U 515 #define XHC_USBCMD__ALL_L 13U 516 #define XHC_USBCMD__ALL_R 0U 517 #define XHC_USBCMD_DATAMASK 0x00003fffU 518 #define XHC_USBCMD_RDWRMASK 0xffffc000U 519 #define XHC_USBCMD_RESETVALUE 0x0000U 520 521 #define XHC_USBSTS_OFFSET 0x024U 522 #define XHC_USBSTS_BASE 0x024U 523 #define XHC_USBSTS__CE 12U 524 #define XHC_USBSTS__CE_L 12U 525 #define XHC_USBSTS__CE_R 12U 526 #define XHC_USBSTS__CE_WIDTH 1U 527 #define XHC_USBSTS__CE_RESETVALUE 0x0U 528 #define XHC_USBSTS__CNR 11U 529 #define XHC_USBSTS__CNR_L 11U 530 #define XHC_USBSTS__CNR_R 11U 531 #define XHC_USBSTS__CNR_WIDTH 1U 532 #define XHC_USBSTS__CNR_RESETVALUE 0x1U 533 534 #define XHC_USBSTS__SRE 10U 535 #define XHC_USBSTS__SRE_L 10U 536 #define XHC_USBSTS__SRE_R 10U 537 #define XHC_USBSTS__SRE_WIDTH 1U 538 #define XHC_USBSTS__SRE_RESETVALUE 0x0U 539 #define XHC_USBSTS__RSS 9U 540 #define XHC_USBSTS__RSS_L 9U 541 #define XHC_USBSTS__RSS_R 9U 542 #define XHC_USBSTS__RSS_WIDTH 1U 543 #define XHC_USBSTS__RSS_RESETVALUE 0x0U 544 #define XHC_USBSTS__SSS 8U 545 #define XHC_USBSTS__SSS_L 8U 546 #define XHC_USBSTS__SSS_R 8U 547 #define XHC_USBSTS__SSS_WIDTH 1U 548 #define XHC_USBSTS__SSS_RESETVALUE 0x0U 549 #define XHC_USBSTS__PCD 4U 550 #define XHC_USBSTS__PCD_L 4U 551 #define XHC_USBSTS__PCD_R 4U 552 #define XHC_USBSTS__PCD_WIDTH 1U 553 #define XHC_USBSTS__PCD_RESETVALUE 0x0U 554 #define XHC_USBSTS__EINT 3U 555 #define XHC_USBSTS__EINT_L 3U 556 #define XHC_USBSTS__EINT_R 3U 557 #define XHC_USBSTS__EINT_WIDTH 1U 558 #define XHC_USBSTS__EINT_RESETVALUE 0x0U 559 #define XHC_USBSTS__HSE 2U 560 #define XHC_USBSTS__HSE_L 2U 561 #define XHC_USBSTS__HSE_R 2U 562 #define XHC_USBSTS__HSE_WIDTH 1U 563 #define XHC_USBSTS__HSE_RESETVALUE 0x0U 564 #define XHC_USBSTS__reserved 1U 565 #define XHC_USBSTS__reserved_L 1U 566 #define XHC_USBSTS__reserved_R 1U 567 #define XHC_USBSTS__reserved_WIDTH 1U 568 #define XHC_USBSTS__reserved_RESETVALUE 0x0U 569 570 #define XHC_USBSTS__CH_L 0U 571 #define XHC_USBSTS__CH_R 0U 572 #define XHC_USBSTS__CH_WIDTH 1U 573 #define XHC_USBSTS__CH_RESETVALUE 0x1U 574 #define XHC_USBSTS__RESERVED_L 31U 575 #define XHC_USBSTS__RESERVED_R 13U 576 #define XHC_USBSTS_WIDTH 13U 577 #define XHC_USBSTS__WIDTH 13U 578 #define XHC_USBSTS_ALL_L 12U 579 #define XHC_USBSTS_ALL_R 0U 580 #define XHC_USBSTS__ALL_L 12U 581 #define XHC_USBSTS__ALL_R 0U 582 #define XHC_USBSTS_DATAMASK 0x00001f1fU 583 #define XHC_USBSTS_RDWRMASK 0xffffe0e0U 584 #define XHC_USBSTS_RESETVALUE 0x0801U 585 586 #define XHC_PAGESIZE_OFFSET 0x028U 587 #define XHC_PAGESIZE_BASE 0x028U 588 #define XHC_PAGESIZE__reserved_L 31U 589 #define XHC_PAGESIZE__reserved_R 16U 590 #define XHC_PAGESIZE__reserved_WIDTH 16U 591 #define XHC_PAGESIZE__reserved_RESETVALUE 0x0000U 592 #define XHC_PAGESIZE__PS_L 15U 593 #define XHC_PAGESIZE__PS_R 0U 594 #define XHC_PAGESIZE__PS_WIDTH 16U 595 #define XHC_PAGESIZE__PS_RESETVALUE 0x0000U 596 #define XHC_PAGESIZE_WIDTH 32U 597 #define XHC_PAGESIZE__WIDTH 32U 598 #define XHC_PAGESIZE_ALL_L 31U 599 #define XHC_PAGESIZE_ALL_R 0U 600 #define XHC_PAGESIZE__ALL_L 31U 601 #define XHC_PAGESIZE__ALL_R 0U 602 #define XHC_PAGESIZE_DATAMASK 0xffffffffU 603 #define XHC_PAGESIZE_RDWRMASK 0x00000000U 604 #define XHC_PAGESIZE_RESETVALUE 0x00000000U 605 606 #define XHC_DNCTRL_OFFSET 0x034U 607 #define XHC_DNCTRL_BASE 0x034U 608 #define XHC_DNCTRL__reserved_L 31U 609 #define XHC_DNCTRL__reserved_R 16U 610 #define XHC_DNCTRL__reserved_WIDTH 16U 611 #define XHC_DNCTRL__reserved_RESETVALUE 0x0000U 612 #define XHC_DNCTRL__DNE_L 15U 613 #define XHC_DNCTRL__DNE_R 0U 614 #define XHC_DNCTRL__DNE_WIDTH 16U 615 #define XHC_DNCTRL__DNE_RESETVALUE 0x0000U 616 #define XHC_DNCTRL_WIDTH 32U 617 #define XHC_DNCTRL__WIDTH 32U 618 #define XHC_DNCTRL_ALL_L 31U 619 #define XHC_DNCTRL_ALL_R 0U 620 #define XHC_DNCTRL__ALL_L 31U 621 #define XHC_DNCTRL__ALL_R 0U 622 #define XHC_DNCTRL_DATAMASK 0xffffffffU 623 #define XHC_DNCTRL_RDWRMASK 0x00000000U 624 #define XHC_DNCTRL_RESETVALUE 0x00000000U 625 626 #define XHC_CRCRL_OFFSET 0x038U 627 #define XHC_CRCRL_BASE 0x038U 628 #define XHC_CRCRL__CRPL_L 31U 629 #define XHC_CRCRL__CRPL_R 6U 630 #define XHC_CRCRL__CRPL_WIDTH 26U 631 #define XHC_CRCRL__CRPL_RESETVALUE 0x0U 632 #define XHC_CRCRL__reserved_L 5U 633 #define XHC_CRCRL__reserved_R 4U 634 #define XHC_CRCRL__reserved_WIDTH 2U 635 #define XHC_CRCRL__reserved_RESETVALUE 0x0U 636 #define XHC_CRCRL__CRR 3U 637 #define XHC_CRCRL__CRR_L 3U 638 #define XHC_CRCRL__CRR_R 3U 639 #define XHC_CRCRL__CRR_WIDTH 1U 640 #define XHC_CRCRL__CRR_RESETVALUE 0x0U 641 #define XHC_CRCRL__CA 2U 642 #define XHC_CRCRL__CA_L 2U 643 #define XHC_CRCRL__CA_R 2U 644 #define XHC_CRCRL__CA_WIDTH 1U 645 #define XHC_CRCRL__CA_RESETVALUE 0x0U 646 #define XHC_CRCRL__CS 1U 647 #define XHC_CRCRL__CS_L 1U 648 #define XHC_CRCRL__CS_R 1U 649 #define XHC_CRCRL__CS_WIDTH 1U 650 #define XHC_CRCRL__CS_RESETVALUE 0x0U 651 #define XHC_CRCRL__RCS 0U 652 #define XHC_CRCRL__RCS_L 0U 653 #define XHC_CRCRL__RCS_R 0U 654 #define XHC_CRCRL__RCS_WIDTH 1U 655 #define XHC_CRCRL__RCS_RESETVALUE 0x0U 656 #define XHC_CRCRL_WIDTH 32U 657 #define XHC_CRCRL__WIDTH 32U 658 #define XHC_CRCRL_ALL_L 31U 659 #define XHC_CRCRL_ALL_R 0U 660 #define XHC_CRCRL__ALL_L 31U 661 #define XHC_CRCRL__ALL_R 0U 662 #define XHC_CRCRL_DATAMASK 0xffffffffU 663 #define XHC_CRCRL_RDWRMASK 0x00000000U 664 #define XHC_CRCRL_RESETVALUE 0x00000000U 665 666 #define XHC_CRCRH_OFFSET 0x03cU 667 #define XHC_CRCRH_BASE 0x03cU 668 #define XHC_CRCRH__CRPH_L 31U 669 #define XHC_CRCRH__CRPH_R 0U 670 #define XHC_CRCRH__CRPH_WIDTH 32U 671 #define XHC_CRCRH__CRPH_RESETVALUE 0x00000000U 672 #define XHC_CRCRH_WIDTH 32U 673 #define XHC_CRCRH__WIDTH 32U 674 #define XHC_CRCRH_ALL_L 31U 675 #define XHC_CRCRH_ALL_R 0U 676 #define XHC_CRCRH__ALL_L 31U 677 #define XHC_CRCRH__ALL_R 0U 678 #define XHC_CRCRH_DATAMASK 0xffffffffU 679 #define XHC_CRCRH_RDWRMASK 0x00000000U 680 #define XHC_CRCRH_RESETVALUE 0x00000000U 681 682 #define XHC_DCBAAPL_OFFSET 0x050U 683 #define XHC_DCBAAPL_BASE 0x050U 684 #define XHC_DCBAAPL__DCAL_L 31U 685 #define XHC_DCBAAPL__DCAL_R 6U 686 #define XHC_DCBAAPL__DCAL_WIDTH 26U 687 #define XHC_DCBAAPL__DCAL_RESETVALUE 0x0U 688 689 #define XHC_DCBAAPL__reserved_L 5U 690 #define XHC_DCBAAPL__reserved_R 0U 691 #define XHC_DCBAAPL__reserved_WIDTH 6U 692 #define XHC_DCBAAPL__reserved_RESETVALUE 0x0U 693 #define XHC_DCBAAPL_WIDTH 32U 694 #define XHC_DCBAAPL__WIDTH 32U 695 #define XHC_DCBAAPL_ALL_L 31U 696 #define XHC_DCBAAPL_ALL_R 0U 697 #define XHC_DCBAAPL__ALL_L 31U 698 #define XHC_DCBAAPL__ALL_R 0U 699 #define XHC_DCBAAPL_DATAMASK 0xffffffffU 700 #define XHC_DCBAAPL_RDWRMASK 0x00000000U 701 #define XHC_DCBAAPL_RESETVALUE 0x00000000U 702 703 #define XHC_DCBAAPH_OFFSET 0x054U 704 #define XHC_DCBAAPH_BASE 0x054U 705 #define XHC_DCBAAPH__DCAH_L 31U 706 #define XHC_DCBAAPH__DCAH_R 0U 707 #define XHC_DCBAAPH__DCAH_WIDTH 32U 708 #define XHC_DCBAAPH__DCAH_RESETVALUE 0x00000000U 709 #define XHC_DCBAAPH_WIDTH 32U 710 #define XHC_DCBAAPH__WIDTH 32U 711 #define XHC_DCBAAPH_ALL_L 31U 712 #define XHC_DCBAAPH_ALL_R 0U 713 #define XHC_DCBAAPH__ALL_L 31U 714 #define XHC_DCBAAPH__ALL_R 0U 715 #define XHC_DCBAAPH_DATAMASK 0xffffffffU 716 #define XHC_DCBAAPH_RDWRMASK 0x00000000U 717 #define XHC_DCBAAPH_RESETVALUE 0x00000000U 718 719 #define XHC_CONFIG_OFFSET 0x058U 720 #define XHC_CONFIG_BASE 0x058U 721 #define XHC_CONFIG__reserved_L 31U 722 #define XHC_CONFIG__reserved_R 10U 723 #define XHC_CONFIG__reserved_WIDTH 22U 724 #define XHC_CONFIG__reserved_RESETVALUE 0x0U 725 #define XHC_CONFIG__CIE 9U 726 #define XHC_CONFIG__CIE_L 9U 727 #define XHC_CONFIG__CIE_R 9U 728 #define XHC_CONFIG__CIE_WIDTH 1U 729 #define XHC_CONFIG__CIE_RESETVALUE 0x0U 730 #define XHC_CONFIG__U3E 8U 731 #define XHC_CONFIG__U3E_L 8U 732 #define XHC_CONFIG__U3E_R 8U 733 #define XHC_CONFIG__U3E_WIDTH 1U 734 #define XHC_CONFIG__U3E_RESETVALUE 0x0U 735 #define XHC_CONFIG__MSE_L 7U 736 #define XHC_CONFIG__MSE_R 0U 737 #define XHC_CONFIG__MSE_WIDTH 8U 738 #define XHC_CONFIG__MSE_RESETVALUE 0x00U 739 #define XHC_CONFIG_WIDTH 32U 740 #define XHC_CONFIG__WIDTH 32U 741 #define XHC_CONFIG_ALL_L 31U 742 #define XHC_CONFIG_ALL_R 0U 743 #define XHC_CONFIG__ALL_L 31U 744 #define XHC_CONFIG__ALL_R 0U 745 #define XHC_CONFIG_DATAMASK 0xffffffffU 746 #define XHC_CONFIG_RDWRMASK 0x00000000U 747 #define XHC_CONFIG_RESETVALUE 0x00000000U 748 749 #define XHC_PORTSC1_OFFSET 0x420U 750 #define XHC_PORTSC1_BASE 0x420U 751 752 #define XHC_PORTSC1__WPR_L 31U 753 #define XHC_PORTSC1__WPR_R 31U 754 #define XHC_PORTSC1__WPR_WIDTH 1U 755 #define XHC_PORTSC1__WPR_RESETVALUE 0x0U 756 757 #define XHC_PORTSC1__DNR_L 30U 758 #define XHC_PORTSC1__DNR_R 30U 759 #define XHC_PORTSC1__DNR_WIDTH 1U 760 #define XHC_PORTSC1__DNR_RESETVALUE 0x0U 761 762 #define XHC_PORTSC1__WOE_L 27U 763 #define XHC_PORTSC1__WOE_R 27U 764 #define XHC_PORTSC1__WOE_WIDTH 1U 765 #define XHC_PORTSC1__WOE_RESETVALUE 0x0U 766 767 #define XHC_PORTSC1__WDE_L 26U 768 #define XHC_PORTSC1__WDE_R 26U 769 #define XHC_PORTSC1__WDE_WIDTH 1U 770 #define XHC_PORTSC1__WDE_RESETVALUE 0x0U 771 772 #define XHC_PORTSC1__WCE_L 25U 773 #define XHC_PORTSC1__WCE_R 25U 774 #define XHC_PORTSC1__WCE_WIDTH 1U 775 #define XHC_PORTSC1__WCE_RESETVALUE 0x0U 776 777 #define XHC_PORTSC1__CAS_L 24U 778 #define XHC_PORTSC1__CAS_R 24U 779 #define XHC_PORTSC1__CAS_WIDTH 1U 780 #define XHC_PORTSC1__CAS_RESETVALUE 0x0U 781 782 #define XHC_PORTSC1__CEC_L 23U 783 #define XHC_PORTSC1__CEC_R 23U 784 #define XHC_PORTSC1__CEC_WIDTH 1U 785 #define XHC_PORTSC1__CEC_RESETVALUE 0x0U 786 787 #define XHC_PORTSC1__PLC_L 22U 788 #define XHC_PORTSC1__PLC_R 22U 789 #define XHC_PORTSC1__PLC_WIDTH 1U 790 #define XHC_PORTSC1__PLC_RESETVALUE 0x0U 791 792 #define XHC_PORTSC1__PRC_L 21U 793 #define XHC_PORTSC1__PRC_R 21U 794 #define XHC_PORTSC1__PRC_WIDTH 1U 795 #define XHC_PORTSC1__PRC_RESETVALUE 0x0U 796 797 #define XHC_PORTSC1__OCC_L 20U 798 #define XHC_PORTSC1__OCC_R 20U 799 #define XHC_PORTSC1__OCC_WIDTH 1U 800 #define XHC_PORTSC1__OCC_RESETVALUE 0x0U 801 802 #define XHC_PORTSC1__WRC_L 19U 803 #define XHC_PORTSC1__WRC_R 19U 804 #define XHC_PORTSC1__WRC_WIDTH 1U 805 #define XHC_PORTSC1__WRC_RESETVALUE 0x0U 806 807 #define XHC_PORTSC1__PEC_L 18U 808 #define XHC_PORTSC1__PEC_R 18U 809 #define XHC_PORTSC1__PEC_WIDTH 1U 810 #define XHC_PORTSC1__PEC_RESETVALUE 0x0U 811 812 #define XHC_PORTSC1__CSC_L 17U 813 #define XHC_PORTSC1__CSC_R 17U 814 #define XHC_PORTSC1__CSC_WIDTH 1U 815 #define XHC_PORTSC1__CSC_RESETVALUE 0x0U 816 817 #define XHC_PORTSC1__LWS_L 16U 818 #define XHC_PORTSC1__LWS_R 16U 819 #define XHC_PORTSC1__LWS_WIDTH 1U 820 #define XHC_PORTSC1__LWS_RESETVALUE 0x0U 821 #define XHC_PORTSC1__PIC_L 15U 822 #define XHC_PORTSC1__PIC_R 14U 823 #define XHC_PORTSC1__PIC_WIDTH 2U 824 #define XHC_PORTSC1__PIC_RESETVALUE 0x0U 825 #define XHC_PORTSC1__PS_L 13U 826 #define XHC_PORTSC1__PS_R 10U 827 #define XHC_PORTSC1__PS_WIDTH 4U 828 #define XHC_PORTSC1__PS_RESETVALUE 0x0U 829 830 #define XHC_PORTSC1__PP_L 9U 831 #define XHC_PORTSC1__PP_R 9U 832 #define XHC_PORTSC1__PP_WIDTH 1U 833 #define XHC_PORTSC1__PP_RESETVALUE 0x0U 834 #define XHC_PORTSC1__PLS_L 8U 835 #define XHC_PORTSC1__PLS_R 5U 836 #define XHC_PORTSC1__PLS_WIDTH 4U 837 #define XHC_PORTSC1__PLS_RESETVALUE 0x5U 838 839 #define XHC_PORTSC1__PRST_L 4U 840 #define XHC_PORTSC1__PRST_R 4U 841 #define XHC_PORTSC1__PRST_WIDTH 1U 842 #define XHC_PORTSC1__PRST_RESETVALUE 0x0U 843 844 #define XHC_PORTSC1__OCA_L 3U 845 #define XHC_PORTSC1__OCA_R 3U 846 #define XHC_PORTSC1__OCA_WIDTH 1U 847 #define XHC_PORTSC1__OCA_RESETVALUE 0x0U 848 #define XHC_PORTSC1__reserved 2U 849 #define XHC_PORTSC1__reserved_L 2U 850 #define XHC_PORTSC1__reserved_R 2U 851 #define XHC_PORTSC1__reserved_WIDTH 1U 852 #define XHC_PORTSC1__reserved_RESETVALUE 0x0U 853 854 #define XHC_PORTSC1__PED_L 1U 855 #define XHC_PORTSC1__PED_R 1U 856 #define XHC_PORTSC1__PED_WIDTH 1U 857 #define XHC_PORTSC1__PED_RESETVALUE 0x0U 858 859 #define XHC_PORTSC1__CCS_L 0U 860 #define XHC_PORTSC1__CCS_R 0U 861 #define XHC_PORTSC1__CCS_WIDTH 1U 862 #define XHC_PORTSC1__CCS_RESETVALUE 0x0U 863 #define XHC_PORTSC1__RESERVED_L 29U 864 #define XHC_PORTSC1__RESERVED_R 28U 865 #define XHC_PORTSC1_WIDTH 32U 866 #define XHC_PORTSC1__WIDTH 32U 867 #define XHC_PORTSC1_ALL_L 31U 868 #define XHC_PORTSC1_ALL_R 0U 869 #define XHC_PORTSC1__ALL_L 31U 870 #define XHC_PORTSC1__ALL_R 0U 871 #define XHC_PORTSC1_DATAMASK 0xcfffffffU 872 #define XHC_PORTSC1_RDWRMASK 0x30000000U 873 #define XHC_PORTSC1_RESETVALUE 0x000000a0U 874 875 #define XHC_PORTPM1_OFFSET 0x424U 876 #define XHC_PORTPM1_BASE 0x424U 877 #define XHC_PORTPM1__reserved_L 31U 878 #define XHC_PORTPM1__reserved_R 17U 879 #define XHC_PORTPM1__reserved_WIDTH 15U 880 #define XHC_PORTPM1__reserved_RESETVALUE 0x0U 881 #define XHC_PORTPM1__FLA 16U 882 #define XHC_PORTPM1__FLA_L 16U 883 #define XHC_PORTPM1__FLA_R 16U 884 #define XHC_PORTPM1__FLA_WIDTH 1U 885 #define XHC_PORTPM1__FLA_RESETVALUE 0x0U 886 #define XHC_PORTPM1__U2T_L 15U 887 #define XHC_PORTPM1__U2T_R 8U 888 #define XHC_PORTPM1__U2T_WIDTH 8U 889 #define XHC_PORTPM1__U2T_RESETVALUE 0x00U 890 #define XHC_PORTPM1__U1T_L 7U 891 #define XHC_PORTPM1__U1T_R 0U 892 #define XHC_PORTPM1__U1T_WIDTH 8U 893 #define XHC_PORTPM1__U1T_RESETVALUE 0x00U 894 #define XHC_PORTPM1_WIDTH 32U 895 #define XHC_PORTPM1__WIDTH 32U 896 #define XHC_PORTPM1_ALL_L 31U 897 #define XHC_PORTPM1_ALL_R 0U 898 #define XHC_PORTPM1__ALL_L 31U 899 #define XHC_PORTPM1__ALL_R 0U 900 #define XHC_PORTPM1_DATAMASK 0xffffffffU 901 #define XHC_PORTPM1_RDWRMASK 0x00000000U 902 #define XHC_PORTPM1_RESETVALUE 0x00000000U 903 904 #define XHC_PORTLC1_OFFSET 0x428U 905 #define XHC_PORTLC1_BASE 0x428U 906 #define XHC_PORTLC1__reserved_L 31U 907 #define XHC_PORTLC1__reserved_R 0U 908 #define XHC_PORTLC1__reserved_WIDTH 32U 909 #define XHC_PORTLC1__reserved_RESETVALUE 0x00000000U 910 #define XHC_PORTLC1_WIDTH 32U 911 #define XHC_PORTLC1__WIDTH 32U 912 #define XHC_PORTLC1_ALL_L 31U 913 #define XHC_PORTLC1_ALL_R 0U 914 #define XHC_PORTLC1__ALL_L 31U 915 #define XHC_PORTLC1__ALL_R 0U 916 #define XHC_PORTLC1_DATAMASK 0xffffffffU 917 #define XHC_PORTLC1_RDWRMASK 0x00000000U 918 #define XHC_PORTLC1_RESETVALUE 0x00000000U 919 920 #define XHC_PORTSC2_OFFSET 0x430U 921 #define XHC_PORTSC2_BASE 0x430U 922 #define XHC_PORTSC2__WPR 31U 923 #define XHC_PORTSC2__WPR_L 31U 924 #define XHC_PORTSC2__WPR_R 31U 925 #define XHC_PORTSC2__WPR_WIDTH 1U 926 #define XHC_PORTSC2__WPR_RESETVALUE 0x0U 927 #define XHC_PORTSC2__DNR 30U 928 #define XHC_PORTSC2__DNR_L 30U 929 #define XHC_PORTSC2__DNR_R 30U 930 #define XHC_PORTSC2__DNR_WIDTH 1U 931 #define XHC_PORTSC2__DNR_RESETVALUE 0x0U 932 #define XHC_PORTSC2__WOE 27U 933 #define XHC_PORTSC2__WOE_L 27U 934 #define XHC_PORTSC2__WOE_R 27U 935 #define XHC_PORTSC2__WOE_WIDTH 1U 936 #define XHC_PORTSC2__WOE_RESETVALUE 0x0U 937 #define XHC_PORTSC2__WDE 26U 938 #define XHC_PORTSC2__WDE_L 26U 939 #define XHC_PORTSC2__WDE_R 26U 940 #define XHC_PORTSC2__WDE_WIDTH 1U 941 #define XHC_PORTSC2__WDE_RESETVALUE 0x0U 942 #define XHC_PORTSC2__WCE 25U 943 #define XHC_PORTSC2__WCE_L 25U 944 #define XHC_PORTSC2__WCE_R 25U 945 #define XHC_PORTSC2__WCE_WIDTH 1U 946 #define XHC_PORTSC2__WCE_RESETVALUE 0x0U 947 #define XHC_PORTSC2__CAS 24U 948 #define XHC_PORTSC2__CAS_L 24U 949 #define XHC_PORTSC2__CAS_R 24U 950 #define XHC_PORTSC2__CAS_WIDTH 1U 951 #define XHC_PORTSC2__CAS_RESETVALUE 0x0U 952 #define XHC_PORTSC2__CEC 23U 953 #define XHC_PORTSC2__CEC_L 23U 954 #define XHC_PORTSC2__CEC_R 23U 955 #define XHC_PORTSC2__CEC_WIDTH 1U 956 #define XHC_PORTSC2__CEC_RESETVALUE 0x0U 957 #define XHC_PORTSC2__PLC 22U 958 #define XHC_PORTSC2__PLC_L 22U 959 #define XHC_PORTSC2__PLC_R 22U 960 #define XHC_PORTSC2__PLC_WIDTH 1U 961 #define XHC_PORTSC2__PLC_RESETVALUE 0x0U 962 #define XHC_PORTSC2__PRC 21U 963 #define XHC_PORTSC2__PRC_L 21U 964 #define XHC_PORTSC2__PRC_R 21U 965 #define XHC_PORTSC2__PRC_WIDTH 1U 966 #define XHC_PORTSC2__PRC_RESETVALUE 0x0U 967 #define XHC_PORTSC2__OCC 20U 968 #define XHC_PORTSC2__OCC_L 20U 969 #define XHC_PORTSC2__OCC_R 20U 970 #define XHC_PORTSC2__OCC_WIDTH 1U 971 #define XHC_PORTSC2__OCC_RESETVALUE 0x0U 972 #define XHC_PORTSC2__WRC 19U 973 #define XHC_PORTSC2__WRC_L 19U 974 #define XHC_PORTSC2__WRC_R 19U 975 #define XHC_PORTSC2__WRC_WIDTH 1U 976 #define XHC_PORTSC2__WRC_RESETVALUE 0x0U 977 #define XHC_PORTSC2__PEC 18U 978 #define XHC_PORTSC2__PEC_L 18U 979 #define XHC_PORTSC2__PEC_R 18U 980 #define XHC_PORTSC2__PEC_WIDTH 1U 981 #define XHC_PORTSC2__PEC_RESETVALUE 0x0U 982 #define XHC_PORTSC2__CSC 17U 983 #define XHC_PORTSC2__CSC_L 17U 984 #define XHC_PORTSC2__CSC_R 17U 985 #define XHC_PORTSC2__CSC_WIDTH 1U 986 #define XHC_PORTSC2__CSC_RESETVALUE 0x0U 987 #define XHC_PORTSC2__LWS 16U 988 #define XHC_PORTSC2__LWS_L 16U 989 #define XHC_PORTSC2__LWS_R 16U 990 #define XHC_PORTSC2__LWS_WIDTH 1U 991 #define XHC_PORTSC2__LWS_RESETVALUE 0x0U 992 #define XHC_PORTSC2__PIC_L 15U 993 #define XHC_PORTSC2__PIC_R 14U 994 #define XHC_PORTSC2__PIC_WIDTH 2U 995 #define XHC_PORTSC2__PIC_RESETVALUE 0x0U 996 #define XHC_PORTSC2__PS_L 13U 997 #define XHC_PORTSC2__PS_R 10U 998 #define XHC_PORTSC2__PS_WIDTH 4U 999 #define XHC_PORTSC2__PS_RESETVALUE 0x0U 1000 #define XHC_PORTSC2__PP 9U 1001 #define XHC_PORTSC2__PP_L 9U 1002 #define XHC_PORTSC2__PP_R 9U 1003 #define XHC_PORTSC2__PP_WIDTH 1U 1004 #define XHC_PORTSC2__PP_RESETVALUE 0x0U 1005 #define XHC_PORTSC2__PLS_L 8U 1006 #define XHC_PORTSC2__PLS_R 5U 1007 #define XHC_PORTSC2__PLS_WIDTH 4U 1008 #define XHC_PORTSC2__PLS_RESETVALUE 0x5U 1009 1010 #define XHC_PORTSC2__PRST_L 4U 1011 #define XHC_PORTSC2__PRST_R 4U 1012 #define XHC_PORTSC2__PRST_WIDTH 1U 1013 #define XHC_PORTSC2__PRST_RESETVALUE 0x0U 1014 #define XHC_PORTSC2__OCA 3U 1015 #define XHC_PORTSC2__OCA_L 3U 1016 #define XHC_PORTSC2__OCA_R 3U 1017 #define XHC_PORTSC2__OCA_WIDTH 1U 1018 #define XHC_PORTSC2__OCA_RESETVALUE 0x0U 1019 #define XHC_PORTSC2__reserved 2U 1020 #define XHC_PORTSC2__reserved_L 2U 1021 #define XHC_PORTSC2__reserved_R 2U 1022 #define XHC_PORTSC2__reserved_WIDTH 1U 1023 #define XHC_PORTSC2__reserved_RESETVALUE 0x0U 1024 #define XHC_PORTSC2__PED 1U 1025 #define XHC_PORTSC2__PED_L 1U 1026 #define XHC_PORTSC2__PED_R 1U 1027 #define XHC_PORTSC2__PED_WIDTH 1U 1028 #define XHC_PORTSC2__PED_RESETVALUE 0x0U 1029 #define XHC_PORTSC2__CCS 0U 1030 #define XHC_PORTSC2__CCS_L 0U 1031 #define XHC_PORTSC2__CCS_R 0U 1032 #define XHC_PORTSC2__CCS_WIDTH 1U 1033 #define XHC_PORTSC2__CCS_RESETVALUE 0x0U 1034 #define XHC_PORTSC2__RESERVED_L 29U 1035 #define XHC_PORTSC2__RESERVED_R 28U 1036 #define XHC_PORTSC2_WIDTH 32U 1037 #define XHC_PORTSC2__WIDTH 32U 1038 #define XHC_PORTSC2_ALL_L 31U 1039 #define XHC_PORTSC2_ALL_R 0U 1040 #define XHC_PORTSC2__ALL_L 31U 1041 #define XHC_PORTSC2__ALL_R 0U 1042 #define XHC_PORTSC2_DATAMASK 0xcfffffffU 1043 #define XHC_PORTSC2_RDWRMASK 0x30000000U 1044 #define XHC_PORTSC2_RESETVALUE 0x000000a0U 1045 1046 #define XHC_PORTPM2_OFFSET 0x434U 1047 #define XHC_PORTPM2_BASE 0x434U 1048 #define XHC_PORTPM2__PTC_L 31U 1049 #define XHC_PORTPM2__PTC_R 28U 1050 #define XHC_PORTPM2__PTC_WIDTH 4U 1051 #define XHC_PORTPM2__PTC_RESETVALUE 0x0U 1052 #define XHC_PORTPM2__reserved_L 27U 1053 #define XHC_PORTPM2__reserved_R 17U 1054 #define XHC_PORTPM2__reserved_WIDTH 11U 1055 #define XHC_PORTPM2__reserved_RESETVALUE 0x0U 1056 #define XHC_PORTPM2__HLE 16U 1057 #define XHC_PORTPM2__HLE_L 16U 1058 #define XHC_PORTPM2__HLE_R 16U 1059 #define XHC_PORTPM2__HLE_WIDTH 1U 1060 #define XHC_PORTPM2__HLE_RESETVALUE 0x0U 1061 #define XHC_PORTPM2__L1DS_L 15U 1062 #define XHC_PORTPM2__L1DS_R 8U 1063 #define XHC_PORTPM2__L1DS_WIDTH 8U 1064 #define XHC_PORTPM2__L1DS_RESETVALUE 0x00U 1065 #define XHC_PORTPM2__BESL_L 7U 1066 #define XHC_PORTPM2__BESL_R 4U 1067 #define XHC_PORTPM2__BESL_WIDTH 4U 1068 #define XHC_PORTPM2__BESL_RESETVALUE 0x0U 1069 #define XHC_PORTPM2__RWE 3U 1070 #define XHC_PORTPM2__RWE_L 3U 1071 #define XHC_PORTPM2__RWE_R 3U 1072 #define XHC_PORTPM2__RWE_WIDTH 1U 1073 #define XHC_PORTPM2__RWE_RESETVALUE 0x0U 1074 #define XHC_PORTPM2__L1S_L 2U 1075 #define XHC_PORTPM2__L1S_R 0U 1076 #define XHC_PORTPM2__L1S_WIDTH 3U 1077 #define XHC_PORTPM2__L1S_RESETVALUE 0x0U 1078 #define XHC_PORTPM2_WIDTH 32U 1079 #define XHC_PORTPM2__WIDTH 32U 1080 #define XHC_PORTPM2_ALL_L 31U 1081 #define XHC_PORTPM2_ALL_R 0U 1082 #define XHC_PORTPM2__ALL_L 31U 1083 #define XHC_PORTPM2__ALL_R 0U 1084 #define XHC_PORTPM2_DATAMASK 0xffffffffU 1085 #define XHC_PORTPM2_RDWRMASK 0x00000000U 1086 #define XHC_PORTPM2_RESETVALUE 0x00000000U 1087 1088 #define XHC_PORTLC2_OFFSET 0x43cU 1089 #define XHC_PORTLC2_BASE 0x43cU 1090 #define XHC_PORTLC2__reserved_L 31U 1091 #define XHC_PORTLC2__reserved_R 14U 1092 #define XHC_PORTLC2__reserved_WIDTH 18U 1093 #define XHC_PORTLC2__reserved_RESETVALUE 0x0U 1094 #define XHC_PORTLC2__BESLD_L 13U 1095 #define XHC_PORTLC2__BESLD_R 10U 1096 #define XHC_PORTLC2__BESLD_WIDTH 4U 1097 #define XHC_PORTLC2__BESLD_RESETVALUE 0x0U 1098 #define XHC_PORTLC2__L1T_L 9U 1099 #define XHC_PORTLC2__L1T_R 2U 1100 #define XHC_PORTLC2__L1T_WIDTH 8U 1101 #define XHC_PORTLC2__L1T_RESETVALUE 0x00U 1102 #define XHC_PORTLC2__HIRDM_L 1U 1103 #define XHC_PORTLC2__HIRDM_R 0U 1104 #define XHC_PORTLC2__HIRDM_WIDTH 2U 1105 #define XHC_PORTLC2__HIRDM_RESETVALUE 0x0U 1106 #define XHC_PORTLC2_WIDTH 32U 1107 #define XHC_PORTLC2__WIDTH 32U 1108 #define XHC_PORTLC2_ALL_L 31U 1109 #define XHC_PORTLC2_ALL_R 0U 1110 #define XHC_PORTLC2__ALL_L 31U 1111 #define XHC_PORTLC2__ALL_R 0U 1112 #define XHC_PORTLC2_DATAMASK 0xffffffffU 1113 #define XHC_PORTLC2_RDWRMASK 0x00000000U 1114 #define XHC_PORTLC2_RESETVALUE 0x00000000U 1115 1116 #define XHC_PORTSC3_OFFSET 0x440U 1117 #define XHC_PORTSC3_BASE 0x440U 1118 #define XHC_PORTSC3__WPR 31U 1119 #define XHC_PORTSC3__WPR_L 31U 1120 #define XHC_PORTSC3__WPR_R 31U 1121 #define XHC_PORTSC3__WPR_WIDTH 1U 1122 #define XHC_PORTSC3__WPR_RESETVALUE 0x0U 1123 #define XHC_PORTSC3__DNR 30U 1124 #define XHC_PORTSC3__DNR_L 30U 1125 #define XHC_PORTSC3__DNR_R 30U 1126 #define XHC_PORTSC3__DNR_WIDTH 1U 1127 #define XHC_PORTSC3__DNR_RESETVALUE 0x0U 1128 #define XHC_PORTSC3__WOE 27U 1129 #define XHC_PORTSC3__WOE_L 27U 1130 #define XHC_PORTSC3__WOE_R 27U 1131 #define XHC_PORTSC3__WOE_WIDTH 1U 1132 #define XHC_PORTSC3__WOE_RESETVALUE 0x0U 1133 #define XHC_PORTSC3__WDE 26U 1134 #define XHC_PORTSC3__WDE_L 26U 1135 #define XHC_PORTSC3__WDE_R 26U 1136 #define XHC_PORTSC3__WDE_WIDTH 1U 1137 #define XHC_PORTSC3__WDE_RESETVALUE 0x0U 1138 #define XHC_PORTSC3__WCE 25U 1139 #define XHC_PORTSC3__WCE_L 25U 1140 #define XHC_PORTSC3__WCE_R 25U 1141 #define XHC_PORTSC3__WCE_WIDTH 1U 1142 #define XHC_PORTSC3__WCE_RESETVALUE 0x0U 1143 #define XHC_PORTSC3__CAS 24U 1144 #define XHC_PORTSC3__CAS_L 24U 1145 #define XHC_PORTSC3__CAS_R 24U 1146 #define XHC_PORTSC3__CAS_WIDTH 1U 1147 #define XHC_PORTSC3__CAS_RESETVALUE 0x0U 1148 #define XHC_PORTSC3__CEC 23U 1149 #define XHC_PORTSC3__CEC_L 23U 1150 #define XHC_PORTSC3__CEC_R 23U 1151 #define XHC_PORTSC3__CEC_WIDTH 1U 1152 #define XHC_PORTSC3__CEC_RESETVALUE 0x0U 1153 #define XHC_PORTSC3__PLC 22U 1154 #define XHC_PORTSC3__PLC_L 22U 1155 #define XHC_PORTSC3__PLC_R 22U 1156 #define XHC_PORTSC3__PLC_WIDTH 1U 1157 #define XHC_PORTSC3__PLC_RESETVALUE 0x0U 1158 #define XHC_PORTSC3__PRC 21U 1159 #define XHC_PORTSC3__PRC_L 21U 1160 #define XHC_PORTSC3__PRC_R 21U 1161 #define XHC_PORTSC3__PRC_WIDTH 1U 1162 #define XHC_PORTSC3__PRC_RESETVALUE 0x0U 1163 #define XHC_PORTSC3__OCC 20U 1164 #define XHC_PORTSC3__OCC_L 20U 1165 #define XHC_PORTSC3__OCC_R 20U 1166 #define XHC_PORTSC3__OCC_WIDTH 1U 1167 #define XHC_PORTSC3__OCC_RESETVALUE 0x0U 1168 #define XHC_PORTSC3__WRC 19U 1169 #define XHC_PORTSC3__WRC_L 19U 1170 #define XHC_PORTSC3__WRC_R 19U 1171 #define XHC_PORTSC3__WRC_WIDTH 1U 1172 #define XHC_PORTSC3__WRC_RESETVALUE 0x0U 1173 #define XHC_PORTSC3__PEC 18U 1174 #define XHC_PORTSC3__PEC_L 18U 1175 #define XHC_PORTSC3__PEC_R 18U 1176 #define XHC_PORTSC3__PEC_WIDTH 1U 1177 #define XHC_PORTSC3__PEC_RESETVALUE 0x0U 1178 #define XHC_PORTSC3__CSC 17U 1179 #define XHC_PORTSC3__CSC_L 17U 1180 #define XHC_PORTSC3__CSC_R 17U 1181 #define XHC_PORTSC3__CSC_WIDTH 1U 1182 #define XHC_PORTSC3__CSC_RESETVALUE 0x0U 1183 #define XHC_PORTSC3__LWS 16U 1184 #define XHC_PORTSC3__LWS_L 16U 1185 #define XHC_PORTSC3__LWS_R 16U 1186 #define XHC_PORTSC3__LWS_WIDTH 1U 1187 #define XHC_PORTSC3__LWS_RESETVALUE 0x0U 1188 #define XHC_PORTSC3__PIC_L 15U 1189 #define XHC_PORTSC3__PIC_R 14U 1190 #define XHC_PORTSC3__PIC_WIDTH 2U 1191 #define XHC_PORTSC3__PIC_RESETVALUE 0x0U 1192 #define XHC_PORTSC3__PS_L 13U 1193 #define XHC_PORTSC3__PS_R 10U 1194 #define XHC_PORTSC3__PS_WIDTH 4U 1195 #define XHC_PORTSC3__PS_RESETVALUE 0x0U 1196 #define XHC_PORTSC3__PP 9U 1197 #define XHC_PORTSC3__PP_L 9U 1198 #define XHC_PORTSC3__PP_R 9U 1199 #define XHC_PORTSC3__PP_WIDTH 1U 1200 #define XHC_PORTSC3__PP_RESETVALUE 0x0U 1201 #define XHC_PORTSC3__PLS_L 8U 1202 #define XHC_PORTSC3__PLS_R 5U 1203 #define XHC_PORTSC3__PLS_WIDTH 4U 1204 #define XHC_PORTSC3__PLS_RESETVALUE 0x5U 1205 #define XHC_PORTSC3__PR 4U 1206 #define XHC_PORTSC3__PR_L 4U 1207 #define XHC_PORTSC3__PR_R 4U 1208 #define XHC_PORTSC3__PR_WIDTH 1U 1209 #define XHC_PORTSC3__PR_RESETVALUE 0x0U 1210 #define XHC_PORTSC3__OCA 3U 1211 #define XHC_PORTSC3__OCA_L 3U 1212 #define XHC_PORTSC3__OCA_R 3U 1213 #define XHC_PORTSC3__OCA_WIDTH 1U 1214 #define XHC_PORTSC3__OCA_RESETVALUE 0x0U 1215 #define XHC_PORTSC3__reserved 2U 1216 #define XHC_PORTSC3__reserved_L 2U 1217 #define XHC_PORTSC3__reserved_R 2U 1218 #define XHC_PORTSC3__reserved_WIDTH 1U 1219 #define XHC_PORTSC3__reserved_RESETVALUE 0x0U 1220 #define XHC_PORTSC3__PED 1U 1221 #define XHC_PORTSC3__PED_L 1U 1222 #define XHC_PORTSC3__PED_R 1U 1223 #define XHC_PORTSC3__PED_WIDTH 1U 1224 #define XHC_PORTSC3__PED_RESETVALUE 0x0U 1225 #define XHC_PORTSC3__CCS 0U 1226 #define XHC_PORTSC3__CCS_L 0U 1227 #define XHC_PORTSC3__CCS_R 0U 1228 #define XHC_PORTSC3__CCS_WIDTH 1U 1229 #define XHC_PORTSC3__CCS_RESETVALUE 0x0U 1230 #define XHC_PORTSC3__RESERVED_L 29U 1231 #define XHC_PORTSC3__RESERVED_R 28U 1232 #define XHC_PORTSC3_WIDTH 32U 1233 #define XHC_PORTSC3__WIDTH 32U 1234 #define XHC_PORTSC3_ALL_L 31U 1235 #define XHC_PORTSC3_ALL_R 0U 1236 #define XHC_PORTSC3__ALL_L 31U 1237 #define XHC_PORTSC3__ALL_R 0U 1238 #define XHC_PORTSC3_DATAMASK 0xcfffffffU 1239 #define XHC_PORTSC3_RDWRMASK 0x30000000U 1240 #define XHC_PORTSC3_RESETVALUE 0x000000a0U 1241 1242 #define XHC_PORTPM3_OFFSET 0x444U 1243 #define XHC_PORTPM3_BASE 0x444U 1244 #define XHC_PORTPM3__PTC_L 31U 1245 #define XHC_PORTPM3__PTC_R 28U 1246 #define XHC_PORTPM3__PTC_WIDTH 4U 1247 #define XHC_PORTPM3__PTC_RESETVALUE 0x0U 1248 #define XHC_PORTPM3__reserved_L 27U 1249 #define XHC_PORTPM3__reserved_R 17U 1250 #define XHC_PORTPM3__reserved_WIDTH 11U 1251 #define XHC_PORTPM3__reserved_RESETVALUE 0x0U 1252 #define XHC_PORTPM3__HLE 16U 1253 #define XHC_PORTPM3__HLE_L 16U 1254 #define XHC_PORTPM3__HLE_R 16U 1255 #define XHC_PORTPM3__HLE_WIDTH 1U 1256 #define XHC_PORTPM3__HLE_RESETVALUE 0x0U 1257 #define XHC_PORTPM3__L1DS_L 15U 1258 #define XHC_PORTPM3__L1DS_R 8U 1259 #define XHC_PORTPM3__L1DS_WIDTH 8U 1260 #define XHC_PORTPM3__L1DS_RESETVALUE 0x00U 1261 #define XHC_PORTPM3__BESL_L 7U 1262 #define XHC_PORTPM3__BESL_R 4U 1263 #define XHC_PORTPM3__BESL_WIDTH 4U 1264 #define XHC_PORTPM3__BESL_RESETVALUE 0x0U 1265 #define XHC_PORTPM3__RWE 3U 1266 #define XHC_PORTPM3__RWE_L 3U 1267 #define XHC_PORTPM3__RWE_R 3U 1268 #define XHC_PORTPM3__RWE_WIDTH 1U 1269 #define XHC_PORTPM3__RWE_RESETVALUE 0x0U 1270 #define XHC_PORTPM3__L1S_L 2U 1271 #define XHC_PORTPM3__L1S_R 0U 1272 #define XHC_PORTPM3__L1S_WIDTH 3U 1273 #define XHC_PORTPM3__L1S_RESETVALUE 0x0U 1274 #define XHC_PORTPM3_WIDTH 32U 1275 #define XHC_PORTPM3__WIDTH 32U 1276 #define XHC_PORTPM3_ALL_L 31U 1277 #define XHC_PORTPM3_ALL_R 0U 1278 #define XHC_PORTPM3__ALL_L 31U 1279 #define XHC_PORTPM3__ALL_R 0U 1280 #define XHC_PORTPM3_DATAMASK 0xffffffffU 1281 #define XHC_PORTPM3_RDWRMASK 0x00000000U 1282 #define XHC_PORTPM3_RESETVALUE 0x00000000U 1283 1284 #define XHC_PORTLI3_OFFSET 0x44cU 1285 #define XHC_PORTLI3_BASE 0x44cU 1286 #define XHC_PORTLI3__reserved_L 31U 1287 #define XHC_PORTLI3__reserved_R 0U 1288 #define XHC_PORTLI3__reserved_WIDTH 32U 1289 #define XHC_PORTLI3__reserved_RESETVALUE 0x00000000U 1290 #define XHC_PORTLI3_WIDTH 32U 1291 #define XHC_PORTLI3__WIDTH 32U 1292 #define XHC_PORTLI3_ALL_L 31U 1293 #define XHC_PORTLI3_ALL_R 0U 1294 #define XHC_PORTLI3__ALL_L 31U 1295 #define XHC_PORTLI3__ALL_R 0U 1296 #define XHC_PORTLI3_DATAMASK 0xffffffffU 1297 #define XHC_PORTLI3_RDWRMASK 0x00000000U 1298 #define XHC_PORTLI3_RESETVALUE 0x00000000U 1299 1300 #define XHC_MFINDEX_OFFSET 0x4a0U 1301 #define XHC_MFINDEX_BASE 0x4a0U 1302 #define XHC_MFINDEX__reserved_L 31U 1303 #define XHC_MFINDEX__reserved_R 14U 1304 #define XHC_MFINDEX__reserved_WIDTH 18U 1305 #define XHC_MFINDEX__reserved_RESETVALUE 0x0U 1306 #define XHC_MFINDEX__MFI_L 13U 1307 #define XHC_MFINDEX__MFI_R 0U 1308 #define XHC_MFINDEX__MFI_WIDTH 14U 1309 #define XHC_MFINDEX__MFI_RESETVALUE 0x0U 1310 #define XHC_MFINDEX_WIDTH 32U 1311 #define XHC_MFINDEX__WIDTH 32U 1312 #define XHC_MFINDEX_ALL_L 31U 1313 #define XHC_MFINDEX_ALL_R 0U 1314 #define XHC_MFINDEX__ALL_L 31U 1315 #define XHC_MFINDEX__ALL_R 0U 1316 #define XHC_MFINDEX_DATAMASK 0xffffffffU 1317 #define XHC_MFINDEX_RDWRMASK 0x00000000U 1318 #define XHC_MFINDEX_RESETVALUE 0x00000000U 1319 1320 #define XHC_IMAN0_OFFSET 0x4c0U 1321 #define XHC_IMAN0_BASE 0x4c0U 1322 #define XHC_IMAN0__reserved_L 31U 1323 #define XHC_IMAN0__reserved_R 2U 1324 #define XHC_IMAN0__reserved_WIDTH 30U 1325 #define XHC_IMAN0__reserved_RESETVALUE 0x0U 1326 #define XHC_IMAN0__IE 1U 1327 #define XHC_IMAN0__IE_L 1U 1328 #define XHC_IMAN0__IE_R 1U 1329 #define XHC_IMAN0__IE_WIDTH 1U 1330 #define XHC_IMAN0__IE_RESETVALUE 0x0U 1331 #define XHC_IMAN0__IP 0U 1332 #define XHC_IMAN0__IP_L 0U 1333 #define XHC_IMAN0__IP_R 0U 1334 #define XHC_IMAN0__IP_WIDTH 1U 1335 #define XHC_IMAN0__IP_RESETVALUE 0x0U 1336 #define XHC_IMAN0_WIDTH 32U 1337 #define XHC_IMAN0__WIDTH 32U 1338 #define XHC_IMAN0_ALL_L 31U 1339 #define XHC_IMAN0_ALL_R 0U 1340 #define XHC_IMAN0__ALL_L 31U 1341 #define XHC_IMAN0__ALL_R 0U 1342 #define XHC_IMAN0_DATAMASK 0xffffffffU 1343 #define XHC_IMAN0_RDWRMASK 0x00000000U 1344 #define XHC_IMAN0_RESETVALUE 0x00000000U 1345 1346 #define XHC_IMOD0_OFFSET 0x4c4U 1347 #define XHC_IMOD0_BASE 0x4c4U 1348 #define XHC_IMOD0__IMODC_L 31U 1349 #define XHC_IMOD0__IMODC_R 16U 1350 #define XHC_IMOD0__IMODC_WIDTH 16U 1351 #define XHC_IMOD0__IMODC_RESETVALUE 0x0000U 1352 #define XHC_IMOD0__IMODI_L 15U 1353 #define XHC_IMOD0__IMODI_R 0U 1354 #define XHC_IMOD0__IMODI_WIDTH 16U 1355 #define XHC_IMOD0__IMODI_RESETVALUE 0x4000U 1356 #define XHC_IMOD0_WIDTH 32U 1357 #define XHC_IMOD0__WIDTH 32U 1358 #define XHC_IMOD0_ALL_L 31U 1359 #define XHC_IMOD0_ALL_R 0U 1360 #define XHC_IMOD0__ALL_L 31U 1361 #define XHC_IMOD0__ALL_R 0U 1362 #define XHC_IMOD0_DATAMASK 0xffffffffU 1363 #define XHC_IMOD0_RDWRMASK 0x00000000U 1364 #define XHC_IMOD0_RESETVALUE 0x00004000U 1365 1366 #define XHC_ERSTSZ0_OFFSET 0x4c8U 1367 #define XHC_ERSTSZ0_BASE 0x4c8U 1368 #define XHC_ERSTSZ0__reserved_L 31U 1369 #define XHC_ERSTSZ0__reserved_R 16U 1370 #define XHC_ERSTSZ0__reserved_WIDTH 16U 1371 #define XHC_ERSTSZ0__reserved_RESETVALUE 0x0000U 1372 #define XHC_ERSTSZ0__TSZ_L 15U 1373 #define XHC_ERSTSZ0__TSZ_R 0U 1374 #define XHC_ERSTSZ0__TSZ_WIDTH 16U 1375 #define XHC_ERSTSZ0__TSZ_RESETVALUE 0x0000U 1376 #define XHC_ERSTSZ0_WIDTH 32U 1377 #define XHC_ERSTSZ0__WIDTH 32U 1378 #define XHC_ERSTSZ0_ALL_L 31U 1379 #define XHC_ERSTSZ0_ALL_R 0U 1380 #define XHC_ERSTSZ0__ALL_L 31U 1381 #define XHC_ERSTSZ0__ALL_R 0U 1382 #define XHC_ERSTSZ0_DATAMASK 0xffffffffU 1383 #define XHC_ERSTSZ0_RDWRMASK 0x00000000U 1384 #define XHC_ERSTSZ0_RESETVALUE 0x00000000U 1385 1386 #define XHC_ERSTBAL0_OFFSET 0x4d0U 1387 #define XHC_ERSTBAL0_BASE 0x4d0U 1388 #define XHC_ERSTBAL0__BAL_L 31U 1389 #define XHC_ERSTBAL0__BAL_R 4U 1390 #define XHC_ERSTBAL0__BAL_WIDTH 28U 1391 #define XHC_ERSTBAL0__BAL_RESETVALUE 0x0000000U 1392 #define XHC_ERSTBAL0__reserved_L 3U 1393 #define XHC_ERSTBAL0__reserved_R 0U 1394 #define XHC_ERSTBAL0__reserved_WIDTH 4U 1395 #define XHC_ERSTBAL0__reserved_RESETVALUE 0x0U 1396 #define XHC_ERSTBAL0_WIDTH 32U 1397 #define XHC_ERSTBAL0__WIDTH 32U 1398 #define XHC_ERSTBAL0_ALL_L 31U 1399 #define XHC_ERSTBAL0_ALL_R 0U 1400 #define XHC_ERSTBAL0__ALL_L 31U 1401 #define XHC_ERSTBAL0__ALL_R 0U 1402 #define XHC_ERSTBAL0_DATAMASK 0xffffffffU 1403 #define XHC_ERSTBAL0_RDWRMASK 0x00000000U 1404 #define XHC_ERSTBAL0_RESETVALUE 0x00000000U 1405 1406 #define XHC_ERSTBAH0_OFFSET 0x4d4U 1407 #define XHC_ERSTBAH0_BASE 0x4d4U 1408 #define XHC_ERSTBAH0__BAH_L 31U 1409 #define XHC_ERSTBAH0__BAH_R 0U 1410 #define XHC_ERSTBAH0__BAH_WIDTH 32U 1411 #define XHC_ERSTBAH0__BAH_RESETVALUE 0x00000000U 1412 #define XHC_ERSTBAH0_WIDTH 32U 1413 #define XHC_ERSTBAH0__WIDTH 32U 1414 #define XHC_ERSTBAH0_ALL_L 31U 1415 #define XHC_ERSTBAH0_ALL_R 0U 1416 #define XHC_ERSTBAH0__ALL_L 31U 1417 #define XHC_ERSTBAH0__ALL_R 0U 1418 #define XHC_ERSTBAH0_DATAMASK 0xffffffffU 1419 #define XHC_ERSTBAH0_RDWRMASK 0x00000000U 1420 #define XHC_ERSTBAH0_RESETVALUE 0x00000000U 1421 1422 #define XHC_ERDPL0_OFFSET 0x4d8U 1423 #define XHC_ERDPL0_BASE 0x4d8U 1424 #define XHC_ERDPL0__DPL_L 31U 1425 #define XHC_ERDPL0__DPL_R 4U 1426 #define XHC_ERDPL0__DPL_WIDTH 28U 1427 #define XHC_ERDPL0__DPL_RESETVALUE 0x0000000U 1428 #define XHC_ERDPL0__EHB 3U 1429 #define XHC_ERDPL0__EHB_L 3U 1430 #define XHC_ERDPL0__EHB_R 3U 1431 #define XHC_ERDPL0__EHB_WIDTH 1U 1432 #define XHC_ERDPL0__EHB_RESETVALUE 0x0U 1433 #define XHC_ERDPL0__DESI_L 2U 1434 #define XHC_ERDPL0__DESI_R 0U 1435 #define XHC_ERDPL0__DESI_WIDTH 3U 1436 #define XHC_ERDPL0__DESI_RESETVALUE 0x0U 1437 #define XHC_ERDPL0_WIDTH 32U 1438 #define XHC_ERDPL0__WIDTH 32U 1439 #define XHC_ERDPL0_ALL_L 31U 1440 #define XHC_ERDPL0_ALL_R 0U 1441 #define XHC_ERDPL0__ALL_L 31U 1442 #define XHC_ERDPL0__ALL_R 0U 1443 #define XHC_ERDPL0_DATAMASK 0xffffffffU 1444 #define XHC_ERDPL0_RDWRMASK 0x00000000U 1445 #define XHC_ERDPL0_RESETVALUE 0x00000000U 1446 1447 #define XHC_ERDPH0_OFFSET 0x4dcU 1448 #define XHC_ERDPH0_BASE 0x4dcU 1449 #define XHC_ERDPH0__DPH_L 31U 1450 #define XHC_ERDPH0__DPH_R 0U 1451 #define XHC_ERDPH0__DPH_WIDTH 32U 1452 #define XHC_ERDPH0__DPH_RESETVALUE 0x00000000U 1453 #define XHC_ERDPH0_WIDTH 32U 1454 #define XHC_ERDPH0__WIDTH 32U 1455 #define XHC_ERDPH0_ALL_L 31U 1456 #define XHC_ERDPH0_ALL_R 0U 1457 #define XHC_ERDPH0__ALL_L 31U 1458 #define XHC_ERDPH0__ALL_R 0U 1459 #define XHC_ERDPH0_DATAMASK 0xffffffffU 1460 #define XHC_ERDPH0_RDWRMASK 0x00000000U 1461 #define XHC_ERDPH0_RESETVALUE 0x00000000U 1462 1463 #define XHC_IMAN1_OFFSET 0x4e0U 1464 #define XHC_IMAN1_BASE 0x4e0U 1465 #define XHC_IMAN1__reserved_L 31U 1466 #define XHC_IMAN1__reserved_R 2U 1467 #define XHC_IMAN1__reserved_WIDTH 30U 1468 #define XHC_IMAN1__reserved_RESETVALUE 0x0U 1469 #define XHC_IMAN1__IE 1U 1470 #define XHC_IMAN1__IE_L 1U 1471 #define XHC_IMAN1__IE_R 1U 1472 #define XHC_IMAN1__IE_WIDTH 1U 1473 #define XHC_IMAN1__IE_RESETVALUE 0x0U 1474 #define XHC_IMAN1__IP 0U 1475 #define XHC_IMAN1__IP_L 0U 1476 #define XHC_IMAN1__IP_R 0U 1477 #define XHC_IMAN1__IP_WIDTH 1U 1478 #define XHC_IMAN1__IP_RESETVALUE 0x0U 1479 #define XHC_IMAN1_WIDTH 32U 1480 #define XHC_IMAN1__WIDTH 32U 1481 #define XHC_IMAN1_ALL_L 31U 1482 #define XHC_IMAN1_ALL_R 0U 1483 #define XHC_IMAN1__ALL_L 31U 1484 #define XHC_IMAN1__ALL_R 0U 1485 #define XHC_IMAN1_DATAMASK 0xffffffffU 1486 #define XHC_IMAN1_RDWRMASK 0x00000000U 1487 #define XHC_IMAN1_RESETVALUE 0x00000000U 1488 1489 #define XHC_IMOD1_OFFSET 0x4e4U 1490 #define XHC_IMOD1_BASE 0x4e4U 1491 #define XHC_IMOD1__IMODC_L 31U 1492 #define XHC_IMOD1__IMODC_R 16U 1493 #define XHC_IMOD1__IMODC_WIDTH 16U 1494 #define XHC_IMOD1__IMODC_RESETVALUE 0x0000U 1495 #define XHC_IMOD1__IMODI_L 15U 1496 #define XHC_IMOD1__IMODI_R 0U 1497 #define XHC_IMOD1__IMODI_WIDTH 16U 1498 #define XHC_IMOD1__IMODI_RESETVALUE 0x4000U 1499 #define XHC_IMOD1_WIDTH 32U 1500 #define XHC_IMOD1__WIDTH 32U 1501 #define XHC_IMOD1_ALL_L 31U 1502 #define XHC_IMOD1_ALL_R 0U 1503 #define XHC_IMOD1__ALL_L 31U 1504 #define XHC_IMOD1__ALL_R 0U 1505 #define XHC_IMOD1_DATAMASK 0xffffffffU 1506 #define XHC_IMOD1_RDWRMASK 0x00000000U 1507 #define XHC_IMOD1_RESETVALUE 0x00004000U 1508 1509 #define XHC_ERSTSZ1_OFFSET 0x4e8U 1510 #define XHC_ERSTSZ1_BASE 0x4e8U 1511 #define XHC_ERSTSZ1__reserved_L 31U 1512 #define XHC_ERSTSZ1__reserved_R 16U 1513 #define XHC_ERSTSZ1__reserved_WIDTH 16U 1514 #define XHC_ERSTSZ1__reserved_RESETVALUE 0x0000U 1515 #define XHC_ERSTSZ1__TSZ_L 15U 1516 #define XHC_ERSTSZ1__TSZ_R 0U 1517 #define XHC_ERSTSZ1__TSZ_WIDTH 16U 1518 #define XHC_ERSTSZ1__TSZ_RESETVALUE 0x0000U 1519 #define XHC_ERSTSZ1_WIDTH 32U 1520 #define XHC_ERSTSZ1__WIDTH 32U 1521 #define XHC_ERSTSZ1_ALL_L 31U 1522 #define XHC_ERSTSZ1_ALL_R 0U 1523 #define XHC_ERSTSZ1__ALL_L 31U 1524 #define XHC_ERSTSZ1__ALL_R 0U 1525 #define XHC_ERSTSZ1_DATAMASK 0xffffffffU 1526 #define XHC_ERSTSZ1_RDWRMASK 0x00000000U 1527 #define XHC_ERSTSZ1_RESETVALUE 0x00000000U 1528 1529 #define XHC_ERSTBAL1_OFFSET 0x4f0U 1530 #define XHC_ERSTBAL1_BASE 0x4f0U 1531 #define XHC_ERSTBAL1__BAL_L 31U 1532 #define XHC_ERSTBAL1__BAL_R 4U 1533 #define XHC_ERSTBAL1__BAL_WIDTH 28U 1534 #define XHC_ERSTBAL1__BAL_RESETVALUE 0x0000000U 1535 #define XHC_ERSTBAL1__reserved_L 3U 1536 #define XHC_ERSTBAL1__reserved_R 0U 1537 #define XHC_ERSTBAL1__reserved_WIDTH 4U 1538 #define XHC_ERSTBAL1__reserved_RESETVALUE 0x0U 1539 #define XHC_ERSTBAL1_WIDTH 32U 1540 #define XHC_ERSTBAL1__WIDTH 32U 1541 #define XHC_ERSTBAL1_ALL_L 31U 1542 #define XHC_ERSTBAL1_ALL_R 0U 1543 #define XHC_ERSTBAL1__ALL_L 31U 1544 #define XHC_ERSTBAL1__ALL_R 0U 1545 #define XHC_ERSTBAL1_DATAMASK 0xffffffffU 1546 #define XHC_ERSTBAL1_RDWRMASK 0x00000000U 1547 #define XHC_ERSTBAL1_RESETVALUE 0x00000000U 1548 1549 #define XHC_ERSTBAH1_OFFSET 0x4f4U 1550 #define XHC_ERSTBAH1_BASE 0x4f4U 1551 #define XHC_ERSTBAH1__BAH_L 31U 1552 #define XHC_ERSTBAH1__BAH_R 0U 1553 #define XHC_ERSTBAH1__BAH_WIDTH 32U 1554 #define XHC_ERSTBAH1__BAH_RESETVALUE 0x00000000U 1555 #define XHC_ERSTBAH1_WIDTH 32U 1556 #define XHC_ERSTBAH1__WIDTH 32U 1557 #define XHC_ERSTBAH1_ALL_L 31U 1558 #define XHC_ERSTBAH1_ALL_R 0U 1559 #define XHC_ERSTBAH1__ALL_L 31U 1560 #define XHC_ERSTBAH1__ALL_R 0U 1561 #define XHC_ERSTBAH1_DATAMASK 0xffffffffU 1562 #define XHC_ERSTBAH1_RDWRMASK 0x00000000U 1563 #define XHC_ERSTBAH1_RESETVALUE 0x00000000U 1564 1565 #define XHC_ERDPL1_OFFSET 0x4f8U 1566 #define XHC_ERDPL1_BASE 0x4f8U 1567 #define XHC_ERDPL1__DPL_L 31U 1568 #define XHC_ERDPL1__DPL_R 4U 1569 #define XHC_ERDPL1__DPL_WIDTH 28U 1570 #define XHC_ERDPL1__DPL_RESETVALUE 0x0000000U 1571 #define XHC_ERDPL1__EHB 3U 1572 #define XHC_ERDPL1__EHB_L 3U 1573 #define XHC_ERDPL1__EHB_R 3U 1574 #define XHC_ERDPL1__EHB_WIDTH 1U 1575 #define XHC_ERDPL1__EHB_RESETVALUE 0x0U 1576 #define XHC_ERDPL1__DESI_L 2U 1577 #define XHC_ERDPL1__DESI_R 0U 1578 #define XHC_ERDPL1__DESI_WIDTH 3U 1579 #define XHC_ERDPL1__DESI_RESETVALUE 0x0U 1580 #define XHC_ERDPL1_WIDTH 32U 1581 #define XHC_ERDPL1__WIDTH 32U 1582 #define XHC_ERDPL1_ALL_L 31U 1583 #define XHC_ERDPL1_ALL_R 0U 1584 #define XHC_ERDPL1__ALL_L 31U 1585 #define XHC_ERDPL1__ALL_R 0U 1586 #define XHC_ERDPL1_DATAMASK 0xffffffffU 1587 #define XHC_ERDPL1_RDWRMASK 0x00000000U 1588 #define XHC_ERDPL1_RESETVALUE 0x00000000U 1589 1590 #define XHC_ERDPH1_OFFSET 0x4fcU 1591 #define XHC_ERDPH1_BASE 0x4fcU 1592 #define XHC_ERDPH1__DPH_L 31U 1593 #define XHC_ERDPH1__DPH_R 0U 1594 #define XHC_ERDPH1__DPH_WIDTH 32U 1595 #define XHC_ERDPH1__DPH_RESETVALUE 0x00000000U 1596 #define XHC_ERDPH1_WIDTH 32U 1597 #define XHC_ERDPH1__WIDTH 32U 1598 #define XHC_ERDPH1_ALL_L 31U 1599 #define XHC_ERDPH1_ALL_R 0U 1600 #define XHC_ERDPH1__ALL_L 31U 1601 #define XHC_ERDPH1__ALL_R 0U 1602 #define XHC_ERDPH1_DATAMASK 0xffffffffU 1603 #define XHC_ERDPH1_RDWRMASK 0x00000000U 1604 #define XHC_ERDPH1_RESETVALUE 0x00000000U 1605 1606 #define XHC_DBLCMD_OFFSET 0x8c0U 1607 #define XHC_DBLCMD_BASE 0x8c0U 1608 #define XHC_DBLCMD__SID_L 31U 1609 #define XHC_DBLCMD__SID_R 16U 1610 #define XHC_DBLCMD__SID_WIDTH 16U 1611 #define XHC_DBLCMD__SID_RESETVALUE 0x0000U 1612 #define XHC_DBLCMD__reserved_L 15U 1613 #define XHC_DBLCMD__reserved_R 8U 1614 #define XHC_DBLCMD__reserved_WIDTH 8U 1615 #define XHC_DBLCMD__reserved_RESETVALUE 0x00U 1616 #define XHC_DBLCMD__TGT_L 7U 1617 #define XHC_DBLCMD__TGT_R 0U 1618 #define XHC_DBLCMD__TGT_WIDTH 8U 1619 #define XHC_DBLCMD__TGT_RESETVALUE 0x00U 1620 #define XHC_DBLCMD_WIDTH 32U 1621 #define XHC_DBLCMD__WIDTH 32U 1622 #define XHC_DBLCMD_ALL_L 31U 1623 #define XHC_DBLCMD_ALL_R 0U 1624 #define XHC_DBLCMD__ALL_L 31U 1625 #define XHC_DBLCMD__ALL_R 0U 1626 #define XHC_DBLCMD_DATAMASK 0xffffffffU 1627 #define XHC_DBLCMD_RDWRMASK 0x00000000U 1628 #define XHC_DBLCMD_RESETVALUE 0x00000000U 1629 1630 #define XHC_DBLDVX1_OFFSET 0x8c4U 1631 #define XHC_DBLDVX1_BASE 0x8c4U 1632 #define XHC_DBLDVX1__SID_L 31U 1633 #define XHC_DBLDVX1__SID_R 16U 1634 #define XHC_DBLDVX1__SID_WIDTH 16U 1635 #define XHC_DBLDVX1__SID_RESETVALUE 0x0000U 1636 #define XHC_DBLDVX1__reserved_L 15U 1637 #define XHC_DBLDVX1__reserved_R 8U 1638 #define XHC_DBLDVX1__reserved_WIDTH 8U 1639 #define XHC_DBLDVX1__reserved_RESETVALUE 0x00U 1640 #define XHC_DBLDVX1__TGT_L 7U 1641 #define XHC_DBLDVX1__TGT_R 0U 1642 #define XHC_DBLDVX1__TGT_WIDTH 8U 1643 #define XHC_DBLDVX1__TGT_RESETVALUE 0x00U 1644 #define XHC_DBLDVX1_WIDTH 32U 1645 #define XHC_DBLDVX1__WIDTH 32U 1646 #define XHC_DBLDVX1_ALL_L 31U 1647 #define XHC_DBLDVX1_ALL_R 0U 1648 #define XHC_DBLDVX1__ALL_L 31U 1649 #define XHC_DBLDVX1__ALL_R 0U 1650 #define XHC_DBLDVX1_DATAMASK 0xffffffffU 1651 #define XHC_DBLDVX1_RDWRMASK 0x00000000U 1652 #define XHC_DBLDVX1_RESETVALUE 0x00000000U 1653 1654 #define XHC_DBLDVX2_OFFSET 0x8c8U 1655 #define XHC_DBLDVX2_BASE 0x8c8U 1656 #define XHC_DBLDVX2__SID_L 31U 1657 #define XHC_DBLDVX2__SID_R 16U 1658 #define XHC_DBLDVX2__SID_WIDTH 16U 1659 #define XHC_DBLDVX2__SID_RESETVALUE 0x0000U 1660 #define XHC_DBLDVX2__reserved_L 15U 1661 #define XHC_DBLDVX2__reserved_R 8U 1662 #define XHC_DBLDVX2__reserved_WIDTH 8U 1663 #define XHC_DBLDVX2__reserved_RESETVALUE 0x00U 1664 #define XHC_DBLDVX2__TGT_L 7U 1665 #define XHC_DBLDVX2__TGT_R 0U 1666 #define XHC_DBLDVX2__TGT_WIDTH 8U 1667 #define XHC_DBLDVX2__TGT_RESETVALUE 0x00U 1668 #define XHC_DBLDVX2_WIDTH 32U 1669 #define XHC_DBLDVX2__WIDTH 32U 1670 #define XHC_DBLDVX2_ALL_L 31U 1671 #define XHC_DBLDVX2_ALL_R 0U 1672 #define XHC_DBLDVX2__ALL_L 31U 1673 #define XHC_DBLDVX2__ALL_R 0U 1674 #define XHC_DBLDVX2_DATAMASK 0xffffffffU 1675 #define XHC_DBLDVX2_RDWRMASK 0x00000000U 1676 #define XHC_DBLDVX2_RESETVALUE 0x00000000U 1677 1678 #define XHC_DBLDVX3_OFFSET 0x8ccU 1679 #define XHC_DBLDVX3_BASE 0x8ccU 1680 #define XHC_DBLDVX3__SID_L 31U 1681 #define XHC_DBLDVX3__SID_R 16U 1682 #define XHC_DBLDVX3__SID_WIDTH 16U 1683 #define XHC_DBLDVX3__SID_RESETVALUE 0x0000U 1684 #define XHC_DBLDVX3__reserved_L 15U 1685 #define XHC_DBLDVX3__reserved_R 8U 1686 #define XHC_DBLDVX3__reserved_WIDTH 8U 1687 #define XHC_DBLDVX3__reserved_RESETVALUE 0x00U 1688 #define XHC_DBLDVX3__TGT_L 7U 1689 #define XHC_DBLDVX3__TGT_R 0U 1690 #define XHC_DBLDVX3__TGT_WIDTH 8U 1691 #define XHC_DBLDVX3__TGT_RESETVALUE 0x00U 1692 #define XHC_DBLDVX3_WIDTH 32U 1693 #define XHC_DBLDVX3__WIDTH 32U 1694 #define XHC_DBLDVX3_ALL_L 31U 1695 #define XHC_DBLDVX3_ALL_R 0U 1696 #define XHC_DBLDVX3__ALL_L 31U 1697 #define XHC_DBLDVX3__ALL_R 0U 1698 #define XHC_DBLDVX3_DATAMASK 0xffffffffU 1699 #define XHC_DBLDVX3_RDWRMASK 0x00000000U 1700 #define XHC_DBLDVX3_RESETVALUE 0x00000000U 1701 1702 #define XHC_DBLDVX4_OFFSET 0x8d0U 1703 #define XHC_DBLDVX4_BASE 0x8d0U 1704 #define XHC_DBLDVX4__SID_L 31U 1705 #define XHC_DBLDVX4__SID_R 16U 1706 #define XHC_DBLDVX4__SID_WIDTH 16U 1707 #define XHC_DBLDVX4__SID_RESETVALUE 0x0000U 1708 #define XHC_DBLDVX4__reserved_L 15U 1709 #define XHC_DBLDVX4__reserved_R 8U 1710 #define XHC_DBLDVX4__reserved_WIDTH 8U 1711 #define XHC_DBLDVX4__reserved_RESETVALUE 0x00U 1712 #define XHC_DBLDVX4__TGT_L 7U 1713 #define XHC_DBLDVX4__TGT_R 0U 1714 #define XHC_DBLDVX4__TGT_WIDTH 8U 1715 #define XHC_DBLDVX4__TGT_RESETVALUE 0x00U 1716 #define XHC_DBLDVX4_WIDTH 32U 1717 #define XHC_DBLDVX4__WIDTH 32U 1718 #define XHC_DBLDVX4_ALL_L 31U 1719 #define XHC_DBLDVX4_ALL_R 0U 1720 #define XHC_DBLDVX4__ALL_L 31U 1721 #define XHC_DBLDVX4__ALL_R 0U 1722 #define XHC_DBLDVX4_DATAMASK 0xffffffffU 1723 #define XHC_DBLDVX4_RDWRMASK 0x00000000U 1724 #define XHC_DBLDVX4_RESETVALUE 0x00000000U 1725 1726 #define XHC_DBLDVX5_OFFSET 0x8d4U 1727 #define XHC_DBLDVX5_BASE 0x8d4U 1728 #define XHC_DBLDVX5__SID_L 31U 1729 #define XHC_DBLDVX5__SID_R 16U 1730 #define XHC_DBLDVX5__SID_WIDTH 16U 1731 #define XHC_DBLDVX5__SID_RESETVALUE 0x0000U 1732 #define XHC_DBLDVX5__reserved_L 15U 1733 #define XHC_DBLDVX5__reserved_R 8U 1734 #define XHC_DBLDVX5__reserved_WIDTH 8U 1735 #define XHC_DBLDVX5__reserved_RESETVALUE 0x00U 1736 #define XHC_DBLDVX5__TGT_L 7U 1737 #define XHC_DBLDVX5__TGT_R 0U 1738 #define XHC_DBLDVX5__TGT_WIDTH 8U 1739 #define XHC_DBLDVX5__TGT_RESETVALUE 0x00U 1740 #define XHC_DBLDVX5_WIDTH 32U 1741 #define XHC_DBLDVX5__WIDTH 32U 1742 #define XHC_DBLDVX5_ALL_L 31U 1743 #define XHC_DBLDVX5_ALL_R 0U 1744 #define XHC_DBLDVX5__ALL_L 31U 1745 #define XHC_DBLDVX5__ALL_R 0U 1746 #define XHC_DBLDVX5_DATAMASK 0xffffffffU 1747 #define XHC_DBLDVX5_RDWRMASK 0x00000000U 1748 #define XHC_DBLDVX5_RESETVALUE 0x00000000U 1749 1750 #define XHC_DBLDVX6_OFFSET 0x8d8U 1751 #define XHC_DBLDVX6_BASE 0x8d8U 1752 #define XHC_DBLDVX6__SID_L 31U 1753 #define XHC_DBLDVX6__SID_R 16U 1754 #define XHC_DBLDVX6__SID_WIDTH 16U 1755 #define XHC_DBLDVX6__SID_RESETVALUE 0x0000U 1756 #define XHC_DBLDVX6__reserved_L 15U 1757 #define XHC_DBLDVX6__reserved_R 8U 1758 #define XHC_DBLDVX6__reserved_WIDTH 8U 1759 #define XHC_DBLDVX6__reserved_RESETVALUE 0x00U 1760 #define XHC_DBLDVX6__TGT_L 7U 1761 #define XHC_DBLDVX6__TGT_R 0U 1762 #define XHC_DBLDVX6__TGT_WIDTH 8U 1763 #define XHC_DBLDVX6__TGT_RESETVALUE 0x00U 1764 #define XHC_DBLDVX6_WIDTH 32U 1765 #define XHC_DBLDVX6__WIDTH 32U 1766 #define XHC_DBLDVX6_ALL_L 31U 1767 #define XHC_DBLDVX6_ALL_R 0U 1768 #define XHC_DBLDVX6__ALL_L 31U 1769 #define XHC_DBLDVX6__ALL_R 0U 1770 #define XHC_DBLDVX6_DATAMASK 0xffffffffU 1771 #define XHC_DBLDVX6_RDWRMASK 0x00000000U 1772 #define XHC_DBLDVX6_RESETVALUE 0x00000000U 1773 1774 #define XHC_DBLDVX7_OFFSET 0x8dcU 1775 #define XHC_DBLDVX7_BASE 0x8dcU 1776 #define XHC_DBLDVX7__SID_L 31U 1777 #define XHC_DBLDVX7__SID_R 16U 1778 #define XHC_DBLDVX7__SID_WIDTH 16U 1779 #define XHC_DBLDVX7__SID_RESETVALUE 0x0000U 1780 #define XHC_DBLDVX7__reserved_L 15U 1781 #define XHC_DBLDVX7__reserved_R 8U 1782 #define XHC_DBLDVX7__reserved_WIDTH 8U 1783 #define XHC_DBLDVX7__reserved_RESETVALUE 0x00U 1784 #define XHC_DBLDVX7__TGT_L 7U 1785 #define XHC_DBLDVX7__TGT_R 0U 1786 #define XHC_DBLDVX7__TGT_WIDTH 8U 1787 #define XHC_DBLDVX7__TGT_RESETVALUE 0x00U 1788 #define XHC_DBLDVX7_WIDTH 32U 1789 #define XHC_DBLDVX7__WIDTH 32U 1790 #define XHC_DBLDVX7_ALL_L 31U 1791 #define XHC_DBLDVX7_ALL_R 0U 1792 #define XHC_DBLDVX7__ALL_L 31U 1793 #define XHC_DBLDVX7__ALL_R 0U 1794 #define XHC_DBLDVX7_DATAMASK 0xffffffffU 1795 #define XHC_DBLDVX7_RDWRMASK 0x00000000U 1796 #define XHC_DBLDVX7_RESETVALUE 0x00000000U 1797 1798 #define XHC_DBLDVX8_OFFSET 0x8e0U 1799 #define XHC_DBLDVX8_BASE 0x8e0U 1800 #define XHC_DBLDVX8__SID_L 31U 1801 #define XHC_DBLDVX8__SID_R 16U 1802 #define XHC_DBLDVX8__SID_WIDTH 16U 1803 #define XHC_DBLDVX8__SID_RESETVALUE 0x0000U 1804 #define XHC_DBLDVX8__reserved_L 15U 1805 #define XHC_DBLDVX8__reserved_R 8U 1806 #define XHC_DBLDVX8__reserved_WIDTH 8U 1807 #define XHC_DBLDVX8__reserved_RESETVALUE 0x00U 1808 #define XHC_DBLDVX8__TGT_L 7U 1809 #define XHC_DBLDVX8__TGT_R 0U 1810 #define XHC_DBLDVX8__TGT_WIDTH 8U 1811 #define XHC_DBLDVX8__TGT_RESETVALUE 0x00U 1812 #define XHC_DBLDVX8_WIDTH 32U 1813 #define XHC_DBLDVX8__WIDTH 32U 1814 #define XHC_DBLDVX8_ALL_L 31U 1815 #define XHC_DBLDVX8_ALL_R 0U 1816 #define XHC_DBLDVX8__ALL_L 31U 1817 #define XHC_DBLDVX8__ALL_R 0U 1818 #define XHC_DBLDVX8_DATAMASK 0xffffffffU 1819 #define XHC_DBLDVX8_RDWRMASK 0x00000000U 1820 #define XHC_DBLDVX8_RESETVALUE 0x00000000U 1821 1822 #define XHC_DBLDVX9_OFFSET 0x8e4U 1823 #define XHC_DBLDVX9_BASE 0x8e4U 1824 #define XHC_DBLDVX9__SID_L 31U 1825 #define XHC_DBLDVX9__SID_R 16U 1826 #define XHC_DBLDVX9__SID_WIDTH 16U 1827 #define XHC_DBLDVX9__SID_RESETVALUE 0x0000U 1828 #define XHC_DBLDVX9__reserved_L 15U 1829 #define XHC_DBLDVX9__reserved_R 8U 1830 #define XHC_DBLDVX9__reserved_WIDTH 8U 1831 #define XHC_DBLDVX9__reserved_RESETVALUE 0x00U 1832 #define XHC_DBLDVX9__TGT_L 7U 1833 #define XHC_DBLDVX9__TGT_R 0U 1834 #define XHC_DBLDVX9__TGT_WIDTH 8U 1835 #define XHC_DBLDVX9__TGT_RESETVALUE 0x00U 1836 #define XHC_DBLDVX9_WIDTH 32U 1837 #define XHC_DBLDVX9__WIDTH 32U 1838 #define XHC_DBLDVX9_ALL_L 31U 1839 #define XHC_DBLDVX9_ALL_R 0U 1840 #define XHC_DBLDVX9__ALL_L 31U 1841 #define XHC_DBLDVX9__ALL_R 0U 1842 #define XHC_DBLDVX9_DATAMASK 0xffffffffU 1843 #define XHC_DBLDVX9_RDWRMASK 0x00000000U 1844 #define XHC_DBLDVX9_RESETVALUE 0x00000000U 1845 1846 #define XHC_DBLDVX10_OFFSET 0x8e8U 1847 #define XHC_DBLDVX10_BASE 0x8e8U 1848 #define XHC_DBLDVX10__SID_L 31U 1849 #define XHC_DBLDVX10__SID_R 16U 1850 #define XHC_DBLDVX10__SID_WIDTH 16U 1851 #define XHC_DBLDVX10__SID_RESETVALUE 0x0000U 1852 #define XHC_DBLDVX10__reserved_L 15U 1853 #define XHC_DBLDVX10__reserved_R 8U 1854 #define XHC_DBLDVX10__reserved_WIDTH 8U 1855 #define XHC_DBLDVX10__reserved_RESETVALUE 0x00U 1856 #define XHC_DBLDVX10__TGT_L 7U 1857 #define XHC_DBLDVX10__TGT_R 0U 1858 #define XHC_DBLDVX10__TGT_WIDTH 8U 1859 #define XHC_DBLDVX10__TGT_RESETVALUE 0x00U 1860 #define XHC_DBLDVX10_WIDTH 32U 1861 #define XHC_DBLDVX10__WIDTH 32U 1862 #define XHC_DBLDVX10_ALL_L 31U 1863 #define XHC_DBLDVX10_ALL_R 0U 1864 #define XHC_DBLDVX10__ALL_L 31U 1865 #define XHC_DBLDVX10__ALL_R 0U 1866 #define XHC_DBLDVX10_DATAMASK 0xffffffffU 1867 #define XHC_DBLDVX10_RDWRMASK 0x00000000U 1868 #define XHC_DBLDVX10_RESETVALUE 0x00000000U 1869 1870 #define XHC_DBLDVX11_OFFSET 0x8ecU 1871 #define XHC_DBLDVX11_BASE 0x8ecU 1872 #define XHC_DBLDVX11__SID_L 31U 1873 #define XHC_DBLDVX11__SID_R 16U 1874 #define XHC_DBLDVX11__SID_WIDTH 16U 1875 #define XHC_DBLDVX11__SID_RESETVALUE 0x0000U 1876 #define XHC_DBLDVX11__reserved_L 15U 1877 #define XHC_DBLDVX11__reserved_R 8U 1878 #define XHC_DBLDVX11__reserved_WIDTH 8U 1879 #define XHC_DBLDVX11__reserved_RESETVALUE 0x00U 1880 #define XHC_DBLDVX11__TGT_L 7U 1881 #define XHC_DBLDVX11__TGT_R 0U 1882 #define XHC_DBLDVX11__TGT_WIDTH 8U 1883 #define XHC_DBLDVX11__TGT_RESETVALUE 0x00U 1884 #define XHC_DBLDVX11_WIDTH 32U 1885 #define XHC_DBLDVX11__WIDTH 32U 1886 #define XHC_DBLDVX11_ALL_L 31U 1887 #define XHC_DBLDVX11_ALL_R 0U 1888 #define XHC_DBLDVX11__ALL_L 31U 1889 #define XHC_DBLDVX11__ALL_R 0U 1890 #define XHC_DBLDVX11_DATAMASK 0xffffffffU 1891 #define XHC_DBLDVX11_RDWRMASK 0x00000000U 1892 #define XHC_DBLDVX11_RESETVALUE 0x00000000U 1893 1894 #define XHC_DBLDVX12_OFFSET 0x8f0U 1895 #define XHC_DBLDVX12_BASE 0x8f0U 1896 #define XHC_DBLDVX12__SID_L 31U 1897 #define XHC_DBLDVX12__SID_R 16U 1898 #define XHC_DBLDVX12__SID_WIDTH 16U 1899 #define XHC_DBLDVX12__SID_RESETVALUE 0x0000U 1900 #define XHC_DBLDVX12__reserved_L 15U 1901 #define XHC_DBLDVX12__reserved_R 8U 1902 #define XHC_DBLDVX12__reserved_WIDTH 8U 1903 #define XHC_DBLDVX12__reserved_RESETVALUE 0x00U 1904 #define XHC_DBLDVX12__TGT_L 7U 1905 #define XHC_DBLDVX12__TGT_R 0U 1906 #define XHC_DBLDVX12__TGT_WIDTH 8U 1907 #define XHC_DBLDVX12__TGT_RESETVALUE 0x00U 1908 #define XHC_DBLDVX12_WIDTH 32U 1909 #define XHC_DBLDVX12__WIDTH 32U 1910 #define XHC_DBLDVX12_ALL_L 31U 1911 #define XHC_DBLDVX12_ALL_R 0U 1912 #define XHC_DBLDVX12__ALL_L 31U 1913 #define XHC_DBLDVX12__ALL_R 0U 1914 #define XHC_DBLDVX12_DATAMASK 0xffffffffU 1915 #define XHC_DBLDVX12_RDWRMASK 0x00000000U 1916 #define XHC_DBLDVX12_RESETVALUE 0x00000000U 1917 1918 #define XHC_DBLDVX13_OFFSET 0x8f4U 1919 #define XHC_DBLDVX13_BASE 0x8f4U 1920 #define XHC_DBLDVX13__SID_L 31U 1921 #define XHC_DBLDVX13__SID_R 16U 1922 #define XHC_DBLDVX13__SID_WIDTH 16U 1923 #define XHC_DBLDVX13__SID_RESETVALUE 0x0000U 1924 #define XHC_DBLDVX13__reserved_L 15U 1925 #define XHC_DBLDVX13__reserved_R 8U 1926 #define XHC_DBLDVX13__reserved_WIDTH 8U 1927 #define XHC_DBLDVX13__reserved_RESETVALUE 0x00U 1928 #define XHC_DBLDVX13__TGT_L 7U 1929 #define XHC_DBLDVX13__TGT_R 0U 1930 #define XHC_DBLDVX13__TGT_WIDTH 8U 1931 #define XHC_DBLDVX13__TGT_RESETVALUE 0x00U 1932 #define XHC_DBLDVX13_WIDTH 32U 1933 #define XHC_DBLDVX13__WIDTH 32U 1934 #define XHC_DBLDVX13_ALL_L 31U 1935 #define XHC_DBLDVX13_ALL_R 0U 1936 #define XHC_DBLDVX13__ALL_L 31U 1937 #define XHC_DBLDVX13__ALL_R 0U 1938 #define XHC_DBLDVX13_DATAMASK 0xffffffffU 1939 #define XHC_DBLDVX13_RDWRMASK 0x00000000U 1940 #define XHC_DBLDVX13_RESETVALUE 0x00000000U 1941 1942 #define XHC_DBLDVX14_OFFSET 0x8f8U 1943 #define XHC_DBLDVX14_BASE 0x8f8U 1944 #define XHC_DBLDVX14__SID_L 31U 1945 #define XHC_DBLDVX14__SID_R 16U 1946 #define XHC_DBLDVX14__SID_WIDTH 16U 1947 #define XHC_DBLDVX14__SID_RESETVALUE 0x0000U 1948 #define XHC_DBLDVX14__reserved_L 15U 1949 #define XHC_DBLDVX14__reserved_R 8U 1950 #define XHC_DBLDVX14__reserved_WIDTH 8U 1951 #define XHC_DBLDVX14__reserved_RESETVALUE 0x00U 1952 #define XHC_DBLDVX14__TGT_L 7U 1953 #define XHC_DBLDVX14__TGT_R 0U 1954 #define XHC_DBLDVX14__TGT_WIDTH 8U 1955 #define XHC_DBLDVX14__TGT_RESETVALUE 0x00U 1956 #define XHC_DBLDVX14_WIDTH 32U 1957 #define XHC_DBLDVX14__WIDTH 32U 1958 #define XHC_DBLDVX14_ALL_L 31U 1959 #define XHC_DBLDVX14_ALL_R 0U 1960 #define XHC_DBLDVX14__ALL_L 31U 1961 #define XHC_DBLDVX14__ALL_R 0U 1962 #define XHC_DBLDVX14_DATAMASK 0xffffffffU 1963 #define XHC_DBLDVX14_RDWRMASK 0x00000000U 1964 #define XHC_DBLDVX14_RESETVALUE 0x00000000U 1965 1966 #define XHC_DBLDVX15_OFFSET 0x8fcU 1967 #define XHC_DBLDVX15_BASE 0x8fcU 1968 #define XHC_DBLDVX15__SID_L 31U 1969 #define XHC_DBLDVX15__SID_R 16U 1970 #define XHC_DBLDVX15__SID_WIDTH 16U 1971 #define XHC_DBLDVX15__SID_RESETVALUE 0x0000U 1972 #define XHC_DBLDVX15__reserved_L 15U 1973 #define XHC_DBLDVX15__reserved_R 8U 1974 #define XHC_DBLDVX15__reserved_WIDTH 8U 1975 #define XHC_DBLDVX15__reserved_RESETVALUE 0x00U 1976 #define XHC_DBLDVX15__TGT_L 7U 1977 #define XHC_DBLDVX15__TGT_R 0U 1978 #define XHC_DBLDVX15__TGT_WIDTH 8U 1979 #define XHC_DBLDVX15__TGT_RESETVALUE 0x00U 1980 #define XHC_DBLDVX15_WIDTH 32U 1981 #define XHC_DBLDVX15__WIDTH 32U 1982 #define XHC_DBLDVX15_ALL_L 31U 1983 #define XHC_DBLDVX15_ALL_R 0U 1984 #define XHC_DBLDVX15__ALL_L 31U 1985 #define XHC_DBLDVX15__ALL_R 0U 1986 #define XHC_DBLDVX15_DATAMASK 0xffffffffU 1987 #define XHC_DBLDVX15_RDWRMASK 0x00000000U 1988 #define XHC_DBLDVX15_RESETVALUE 0x00000000U 1989 1990 #define XHC_DBLDVX16_OFFSET 0x900U 1991 #define XHC_DBLDVX16_BASE 0x900U 1992 #define XHC_DBLDVX16__SID_L 31U 1993 #define XHC_DBLDVX16__SID_R 16U 1994 #define XHC_DBLDVX16__SID_WIDTH 16U 1995 #define XHC_DBLDVX16__SID_RESETVALUE 0x0000U 1996 #define XHC_DBLDVX16__reserved_L 15U 1997 #define XHC_DBLDVX16__reserved_R 8U 1998 #define XHC_DBLDVX16__reserved_WIDTH 8U 1999 #define XHC_DBLDVX16__reserved_RESETVALUE 0x00U 2000 #define XHC_DBLDVX16__TGT_L 7U 2001 #define XHC_DBLDVX16__TGT_R 0U 2002 #define XHC_DBLDVX16__TGT_WIDTH 8U 2003 #define XHC_DBLDVX16__TGT_RESETVALUE 0x00U 2004 #define XHC_DBLDVX16_WIDTH 32U 2005 #define XHC_DBLDVX16__WIDTH 32U 2006 #define XHC_DBLDVX16_ALL_L 31U 2007 #define XHC_DBLDVX16_ALL_R 0U 2008 #define XHC_DBLDVX16__ALL_L 31U 2009 #define XHC_DBLDVX16__ALL_R 0U 2010 #define XHC_DBLDVX16_DATAMASK 0xffffffffU 2011 #define XHC_DBLDVX16_RDWRMASK 0x00000000U 2012 #define XHC_DBLDVX16_RESETVALUE 0x00000000U 2013 2014 #define XHC_ECHSPT3_OFFSET 0x940U 2015 #define XHC_ECHSPT3_BASE 0x940U 2016 #define XHC_ECHSPT3__RMAJ_L 31U 2017 #define XHC_ECHSPT3__RMAJ_R 24U 2018 #define XHC_ECHSPT3__RMAJ_WIDTH 8U 2019 #define XHC_ECHSPT3__RMAJ_RESETVALUE 0x00U 2020 #define XHC_ECHSPT3__RMIN_L 23U 2021 #define XHC_ECHSPT3__RMIN_R 16U 2022 #define XHC_ECHSPT3__RMIN_WIDTH 8U 2023 #define XHC_ECHSPT3__RMIN_RESETVALUE 0x00U 2024 #define XHC_ECHSPT3__NCP_L 15U 2025 #define XHC_ECHSPT3__NCP_R 8U 2026 #define XHC_ECHSPT3__NCP_WIDTH 8U 2027 #define XHC_ECHSPT3__NCP_RESETVALUE 0x00U 2028 #define XHC_ECHSPT3__CID_L 7U 2029 #define XHC_ECHSPT3__CID_R 0U 2030 #define XHC_ECHSPT3__CID_WIDTH 8U 2031 #define XHC_ECHSPT3__CID_RESETVALUE 0x02U 2032 #define XHC_ECHSPT3_WIDTH 32U 2033 #define XHC_ECHSPT3__WIDTH 32U 2034 #define XHC_ECHSPT3_ALL_L 31U 2035 #define XHC_ECHSPT3_ALL_R 0U 2036 #define XHC_ECHSPT3__ALL_L 31U 2037 #define XHC_ECHSPT3__ALL_R 0U 2038 #define XHC_ECHSPT3_DATAMASK 0xffffffffU 2039 #define XHC_ECHSPT3_RDWRMASK 0x00000000U 2040 #define XHC_ECHSPT3_RESETVALUE 0x00000002U 2041 2042 #define XHC_PNSTR3_OFFSET 0x944U 2043 #define XHC_PNSTR3_BASE 0x944U 2044 #define XHC_PNSTR3__STR_L 31U 2045 #define XHC_PNSTR3__STR_R 0U 2046 #define XHC_PNSTR3__STR_WIDTH 32U 2047 #define XHC_PNSTR3__STR_RESETVALUE 0x20425355U 2048 #define XHC_PNSTR3_WIDTH 32U 2049 #define XHC_PNSTR3__WIDTH 32U 2050 #define XHC_PNSTR3_ALL_L 31U 2051 #define XHC_PNSTR3_ALL_R 0U 2052 #define XHC_PNSTR3__ALL_L 31U 2053 #define XHC_PNSTR3__ALL_R 0U 2054 #define XHC_PNSTR3_DATAMASK 0xffffffffU 2055 #define XHC_PNSTR3_RDWRMASK 0x00000000U 2056 #define XHC_PNSTR3_RESETVALUE 0x20425355U 2057 2058 #define XHC_PSUM3_OFFSET 0x948U 2059 #define XHC_PSUM3_BASE 0x948U 2060 #define XHC_PSUM3__PSIC_L 31U 2061 #define XHC_PSUM3__PSIC_R 28U 2062 #define XHC_PSUM3__PSIC_WIDTH 4U 2063 #define XHC_PSUM3__PSIC_RESETVALUE 0x0U 2064 #define XHC_PSUM3__MHD_L 27U 2065 #define XHC_PSUM3__MHD_R 25U 2066 #define XHC_PSUM3__MHD_WIDTH 3U 2067 #define XHC_PSUM3__MHD_RESETVALUE 0x0U 2068 #define XHC_PSUM3__BLC 20U 2069 #define XHC_PSUM3__BLC_L 20U 2070 #define XHC_PSUM3__BLC_R 20U 2071 #define XHC_PSUM3__BLC_WIDTH 1U 2072 #define XHC_PSUM3__BLC_RESETVALUE 0x0U 2073 #define XHC_PSUM3__HLC 19U 2074 #define XHC_PSUM3__HLC_L 19U 2075 #define XHC_PSUM3__HLC_R 19U 2076 #define XHC_PSUM3__HLC_WIDTH 1U 2077 #define XHC_PSUM3__HLC_RESETVALUE 0x1U 2078 #define XHC_PSUM3__IHI 18U 2079 #define XHC_PSUM3__IHI_L 18U 2080 #define XHC_PSUM3__IHI_R 18U 2081 #define XHC_PSUM3__IHI_WIDTH 1U 2082 #define XHC_PSUM3__IHI_RESETVALUE 0x0U 2083 #define XHC_PSUM3__HSO 17U 2084 #define XHC_PSUM3__HSO_L 17U 2085 #define XHC_PSUM3__HSO_R 17U 2086 #define XHC_PSUM3__HSO_WIDTH 1U 2087 #define XHC_PSUM3__HSO_RESETVALUE 0x0U 2088 #define XHC_PSUM3__reserved 16U 2089 #define XHC_PSUM3__reserved_L 16U 2090 #define XHC_PSUM3__reserved_R 16U 2091 #define XHC_PSUM3__reserved_WIDTH 1U 2092 #define XHC_PSUM3__reserved_RESETVALUE 0x0U 2093 #define XHC_PSUM3__CPC_L 15U 2094 #define XHC_PSUM3__CPC_R 8U 2095 #define XHC_PSUM3__CPC_WIDTH 8U 2096 #define XHC_PSUM3__CPC_RESETVALUE 0x00U 2097 #define XHC_PSUM3__CPO_L 7U 2098 #define XHC_PSUM3__CPO_R 0U 2099 #define XHC_PSUM3__CPO_WIDTH 8U 2100 #define XHC_PSUM3__CPO_RESETVALUE 0x00U 2101 #define XHC_PSUM3__RESERVED_L 24U 2102 #define XHC_PSUM3__RESERVED_R 21U 2103 #define XHC_PSUM3_WIDTH 32U 2104 #define XHC_PSUM3__WIDTH 32U 2105 #define XHC_PSUM3_ALL_L 31U 2106 #define XHC_PSUM3_ALL_R 0U 2107 #define XHC_PSUM3__ALL_L 31U 2108 #define XHC_PSUM3__ALL_R 0U 2109 #define XHC_PSUM3_DATAMASK 0xfe1fffffU 2110 #define XHC_PSUM3_RDWRMASK 0x01e00000U 2111 #define XHC_PSUM3_RESETVALUE 0x00080000U 2112 2113 #define XHC_PTSLTYP3_OFFSET 0x94cU 2114 #define XHC_PTSLTYP3_BASE 0x94cU 2115 #define XHC_PTSLTYP3__reserved_L 31U 2116 #define XHC_PTSLTYP3__reserved_R 5U 2117 #define XHC_PTSLTYP3__reserved_WIDTH 27U 2118 #define XHC_PTSLTYP3__reserved_RESETVALUE 0x0U 2119 #define XHC_PTSLTYP3__PST_L 4U 2120 #define XHC_PTSLTYP3__PST_R 0U 2121 #define XHC_PTSLTYP3__PST_WIDTH 5U 2122 #define XHC_PTSLTYP3__PST_RESETVALUE 0x0U 2123 #define XHC_PTSLTYP3_WIDTH 32U 2124 #define XHC_PTSLTYP3__WIDTH 32U 2125 #define XHC_PTSLTYP3_ALL_L 31U 2126 #define XHC_PTSLTYP3_ALL_R 0U 2127 #define XHC_PTSLTYP3__ALL_L 31U 2128 #define XHC_PTSLTYP3__ALL_R 0U 2129 #define XHC_PTSLTYP3_DATAMASK 0xffffffffU 2130 #define XHC_PTSLTYP3_RDWRMASK 0x00000000U 2131 #define XHC_PTSLTYP3_RESETVALUE 0x00000000U 2132 2133 #define XHC_ECHSPT2_OFFSET 0x950U 2134 #define XHC_ECHSPT2_BASE 0x950U 2135 #define XHC_ECHSPT2__RMAJ_L 31U 2136 #define XHC_ECHSPT2__RMAJ_R 24U 2137 #define XHC_ECHSPT2__RMAJ_WIDTH 8U 2138 #define XHC_ECHSPT2__RMAJ_RESETVALUE 0x00U 2139 #define XHC_ECHSPT2__RMIN_L 23U 2140 #define XHC_ECHSPT2__RMIN_R 16U 2141 #define XHC_ECHSPT2__RMIN_WIDTH 8U 2142 #define XHC_ECHSPT2__RMIN_RESETVALUE 0x00U 2143 #define XHC_ECHSPT2__NCP_L 15U 2144 #define XHC_ECHSPT2__NCP_R 8U 2145 #define XHC_ECHSPT2__NCP_WIDTH 8U 2146 #define XHC_ECHSPT2__NCP_RESETVALUE 0x00U 2147 #define XHC_ECHSPT2__CID_L 7U 2148 #define XHC_ECHSPT2__CID_R 0U 2149 #define XHC_ECHSPT2__CID_WIDTH 8U 2150 #define XHC_ECHSPT2__CID_RESETVALUE 0x02U 2151 #define XHC_ECHSPT2_WIDTH 32U 2152 #define XHC_ECHSPT2__WIDTH 32U 2153 #define XHC_ECHSPT2_ALL_L 31U 2154 #define XHC_ECHSPT2_ALL_R 0U 2155 #define XHC_ECHSPT2__ALL_L 31U 2156 #define XHC_ECHSPT2__ALL_R 0U 2157 #define XHC_ECHSPT2_DATAMASK 0xffffffffU 2158 #define XHC_ECHSPT2_RDWRMASK 0x00000000U 2159 #define XHC_ECHSPT2_RESETVALUE 0x00000002U 2160 2161 #define XHC_PNSTR2_OFFSET 0x954U 2162 #define XHC_PNSTR2_BASE 0x954U 2163 #define XHC_PNSTR2__STR_L 31U 2164 #define XHC_PNSTR2__STR_R 0U 2165 #define XHC_PNSTR2__STR_WIDTH 32U 2166 #define XHC_PNSTR2__STR_RESETVALUE 0x20425355U 2167 #define XHC_PNSTR2_WIDTH 32U 2168 #define XHC_PNSTR2__WIDTH 32U 2169 #define XHC_PNSTR2_ALL_L 31U 2170 #define XHC_PNSTR2_ALL_R 0U 2171 #define XHC_PNSTR2__ALL_L 31U 2172 #define XHC_PNSTR2__ALL_R 0U 2173 #define XHC_PNSTR2_DATAMASK 0xffffffffU 2174 #define XHC_PNSTR2_RDWRMASK 0x00000000U 2175 #define XHC_PNSTR2_RESETVALUE 0x20425355U 2176 2177 #define XHC_PSUM2_OFFSET 0x958U 2178 #define XHC_PSUM2_BASE 0x958U 2179 #define XHC_PSUM2__PSIC_L 31U 2180 #define XHC_PSUM2__PSIC_R 28U 2181 #define XHC_PSUM2__PSIC_WIDTH 4U 2182 #define XHC_PSUM2__PSIC_RESETVALUE 0x0U 2183 #define XHC_PSUM2__MHD_L 27U 2184 #define XHC_PSUM2__MHD_R 25U 2185 #define XHC_PSUM2__MHD_WIDTH 3U 2186 #define XHC_PSUM2__MHD_RESETVALUE 0x0U 2187 #define XHC_PSUM2__BLC 20U 2188 #define XHC_PSUM2__BLC_L 20U 2189 #define XHC_PSUM2__BLC_R 20U 2190 #define XHC_PSUM2__BLC_WIDTH 1U 2191 #define XHC_PSUM2__BLC_RESETVALUE 0x0U 2192 #define XHC_PSUM2__HLC 19U 2193 #define XHC_PSUM2__HLC_L 19U 2194 #define XHC_PSUM2__HLC_R 19U 2195 #define XHC_PSUM2__HLC_WIDTH 1U 2196 #define XHC_PSUM2__HLC_RESETVALUE 0x1U 2197 #define XHC_PSUM2__IHI 18U 2198 #define XHC_PSUM2__IHI_L 18U 2199 #define XHC_PSUM2__IHI_R 18U 2200 #define XHC_PSUM2__IHI_WIDTH 1U 2201 #define XHC_PSUM2__IHI_RESETVALUE 0x0U 2202 #define XHC_PSUM2__HSO 17U 2203 #define XHC_PSUM2__HSO_L 17U 2204 #define XHC_PSUM2__HSO_R 17U 2205 #define XHC_PSUM2__HSO_WIDTH 1U 2206 #define XHC_PSUM2__HSO_RESETVALUE 0x0U 2207 #define XHC_PSUM2__reserved 16U 2208 #define XHC_PSUM2__reserved_L 16U 2209 #define XHC_PSUM2__reserved_R 16U 2210 #define XHC_PSUM2__reserved_WIDTH 1U 2211 #define XHC_PSUM2__reserved_RESETVALUE 0x0U 2212 #define XHC_PSUM2__CPC_L 15U 2213 #define XHC_PSUM2__CPC_R 8U 2214 #define XHC_PSUM2__CPC_WIDTH 8U 2215 #define XHC_PSUM2__CPC_RESETVALUE 0x00U 2216 #define XHC_PSUM2__CPO_L 7U 2217 #define XHC_PSUM2__CPO_R 0U 2218 #define XHC_PSUM2__CPO_WIDTH 8U 2219 #define XHC_PSUM2__CPO_RESETVALUE 0x00U 2220 #define XHC_PSUM2__RESERVED_L 24U 2221 #define XHC_PSUM2__RESERVED_R 21U 2222 #define XHC_PSUM2_WIDTH 32U 2223 #define XHC_PSUM2__WIDTH 32U 2224 #define XHC_PSUM2_ALL_L 31U 2225 #define XHC_PSUM2_ALL_R 0U 2226 #define XHC_PSUM2__ALL_L 31U 2227 #define XHC_PSUM2__ALL_R 0U 2228 #define XHC_PSUM2_DATAMASK 0xfe1fffffU 2229 #define XHC_PSUM2_RDWRMASK 0x01e00000U 2230 #define XHC_PSUM2_RESETVALUE 0x00080000U 2231 2232 #define XHC_PTSLTYP2_OFFSET 0x95cU 2233 #define XHC_PTSLTYP2_BASE 0x95cU 2234 #define XHC_PTSLTYP2__reserved_L 31U 2235 #define XHC_PTSLTYP2__reserved_R 5U 2236 #define XHC_PTSLTYP2__reserved_WIDTH 27U 2237 #define XHC_PTSLTYP2__reserved_RESETVALUE 0x0U 2238 #define XHC_PTSLTYP2__PST_L 4U 2239 #define XHC_PTSLTYP2__PST_R 0U 2240 #define XHC_PTSLTYP2__PST_WIDTH 5U 2241 #define XHC_PTSLTYP2__PST_RESETVALUE 0x0U 2242 #define XHC_PTSLTYP2_WIDTH 32U 2243 #define XHC_PTSLTYP2__WIDTH 32U 2244 #define XHC_PTSLTYP2_ALL_L 31U 2245 #define XHC_PTSLTYP2_ALL_R 0U 2246 #define XHC_PTSLTYP2__ALL_L 31U 2247 #define XHC_PTSLTYP2__ALL_R 0U 2248 #define XHC_PTSLTYP2_DATAMASK 0xffffffffU 2249 #define XHC_PTSLTYP2_RDWRMASK 0x00000000U 2250 #define XHC_PTSLTYP2_RESETVALUE 0x00000000U 2251 2252 #define XHC_ECHRSVP_OFFSET 0x960U 2253 #define XHC_ECHRSVP_BASE 0x960U 2254 #define XHC_ECHRSVP__reserved_L 31U 2255 #define XHC_ECHRSVP__reserved_R 16U 2256 #define XHC_ECHRSVP__reserved_WIDTH 16U 2257 #define XHC_ECHRSVP__reserved_RESETVALUE 0x0000U 2258 #define XHC_ECHRSVP__NCP_L 15U 2259 #define XHC_ECHRSVP__NCP_R 8U 2260 #define XHC_ECHRSVP__NCP_WIDTH 8U 2261 #define XHC_ECHRSVP__NCP_RESETVALUE 0x00U 2262 #define XHC_ECHRSVP__CID_L 7U 2263 #define XHC_ECHRSVP__CID_R 0U 2264 #define XHC_ECHRSVP__CID_WIDTH 8U 2265 #define XHC_ECHRSVP__CID_RESETVALUE 0xffU 2266 #define XHC_ECHRSVP_WIDTH 32U 2267 #define XHC_ECHRSVP__WIDTH 32U 2268 #define XHC_ECHRSVP_ALL_L 31U 2269 #define XHC_ECHRSVP_ALL_R 0U 2270 #define XHC_ECHRSVP__ALL_L 31U 2271 #define XHC_ECHRSVP__ALL_R 0U 2272 #define XHC_ECHRSVP_DATAMASK 0xffffffffU 2273 #define XHC_ECHRSVP_RDWRMASK 0x00000000U 2274 #define XHC_ECHRSVP_RESETVALUE 0x000000ffU 2275 2276 #define XHC_ECHRSVI_OFFSET 0x968U 2277 #define XHC_ECHRSVI_BASE 0x968U 2278 #define XHC_ECHRSVI__reserved_L 31U 2279 #define XHC_ECHRSVI__reserved_R 16U 2280 #define XHC_ECHRSVI__reserved_WIDTH 16U 2281 #define XHC_ECHRSVI__reserved_RESETVALUE 0x0000U 2282 #define XHC_ECHRSVI__NCP_L 15U 2283 #define XHC_ECHRSVI__NCP_R 8U 2284 #define XHC_ECHRSVI__NCP_WIDTH 8U 2285 #define XHC_ECHRSVI__NCP_RESETVALUE 0x00U 2286 #define XHC_ECHRSVI__CID_L 7U 2287 #define XHC_ECHRSVI__CID_R 0U 2288 #define XHC_ECHRSVI__CID_WIDTH 8U 2289 #define XHC_ECHRSVI__CID_RESETVALUE 0xffU 2290 #define XHC_ECHRSVI_WIDTH 32U 2291 #define XHC_ECHRSVI__WIDTH 32U 2292 #define XHC_ECHRSVI_ALL_L 31U 2293 #define XHC_ECHRSVI_ALL_R 0U 2294 #define XHC_ECHRSVI__ALL_L 31U 2295 #define XHC_ECHRSVI__ALL_R 0U 2296 #define XHC_ECHRSVI_DATAMASK 0xffffffffU 2297 #define XHC_ECHRSVI_RDWRMASK 0x00000000U 2298 #define XHC_ECHRSVI_RESETVALUE 0x000000ffU 2299 2300 #define XHC_ECHRSVM_OFFSET 0xae8U 2301 #define XHC_ECHRSVM_BASE 0xae8U 2302 #define XHC_ECHRSVM__reserved_L 31U 2303 #define XHC_ECHRSVM__reserved_R 16U 2304 #define XHC_ECHRSVM__reserved_WIDTH 16U 2305 #define XHC_ECHRSVM__reserved_RESETVALUE 0x0000U 2306 #define XHC_ECHRSVM__NCP_L 15U 2307 #define XHC_ECHRSVM__NCP_R 8U 2308 #define XHC_ECHRSVM__NCP_WIDTH 8U 2309 #define XHC_ECHRSVM__NCP_RESETVALUE 0x00U 2310 #define XHC_ECHRSVM__CID_L 7U 2311 #define XHC_ECHRSVM__CID_R 0U 2312 #define XHC_ECHRSVM__CID_WIDTH 8U 2313 #define XHC_ECHRSVM__CID_RESETVALUE 0xffU 2314 #define XHC_ECHRSVM_WIDTH 32U 2315 #define XHC_ECHRSVM__WIDTH 32U 2316 #define XHC_ECHRSVM_ALL_L 31U 2317 #define XHC_ECHRSVM_ALL_R 0U 2318 #define XHC_ECHRSVM__ALL_L 31U 2319 #define XHC_ECHRSVM__ALL_R 0U 2320 #define XHC_ECHRSVM_DATAMASK 0xffffffffU 2321 #define XHC_ECHRSVM_RDWRMASK 0x00000000U 2322 #define XHC_ECHRSVM_RESETVALUE 0x000000ffU 2323 2324 #define XHC_ECHRSVD_OFFSET 0xaf8U 2325 #define XHC_ECHRSVD_BASE 0xaf8U 2326 #define XHC_ECHRSVD__reserved_L 31U 2327 #define XHC_ECHRSVD__reserved_R 16U 2328 #define XHC_ECHRSVD__reserved_WIDTH 16U 2329 #define XHC_ECHRSVD__reserved_RESETVALUE 0x0000U 2330 #define XHC_ECHRSVD__NCP_L 15U 2331 #define XHC_ECHRSVD__NCP_R 8U 2332 #define XHC_ECHRSVD__NCP_WIDTH 8U 2333 #define XHC_ECHRSVD__NCP_RESETVALUE 0x00U 2334 #define XHC_ECHRSVD__CID_L 7U 2335 #define XHC_ECHRSVD__CID_R 0U 2336 #define XHC_ECHRSVD__CID_WIDTH 8U 2337 #define XHC_ECHRSVD__CID_RESETVALUE 0xffU 2338 #define XHC_ECHRSVD_WIDTH 32U 2339 #define XHC_ECHRSVD__WIDTH 32U 2340 #define XHC_ECHRSVD_ALL_L 31U 2341 #define XHC_ECHRSVD_ALL_R 0U 2342 #define XHC_ECHRSVD__ALL_L 31U 2343 #define XHC_ECHRSVD__ALL_R 0U 2344 #define XHC_ECHRSVD_DATAMASK 0xffffffffU 2345 #define XHC_ECHRSVD_RDWRMASK 0x00000000U 2346 #define XHC_ECHRSVD_RESETVALUE 0x000000ffU 2347 2348 #define XHC_ECHRSVO_OFFSET 0xb38U 2349 #define XHC_ECHRSVO_BASE 0xb38U 2350 #define XHC_ECHRSVO__reserved_L 31U 2351 #define XHC_ECHRSVO__reserved_R 16U 2352 #define XHC_ECHRSVO__reserved_WIDTH 16U 2353 #define XHC_ECHRSVO__reserved_RESETVALUE 0x0000U 2354 #define XHC_ECHRSVO__NCP_L 15U 2355 #define XHC_ECHRSVO__NCP_R 8U 2356 #define XHC_ECHRSVO__NCP_WIDTH 8U 2357 #define XHC_ECHRSVO__NCP_RESETVALUE 0x00U 2358 #define XHC_ECHRSVO__CID_L 7U 2359 #define XHC_ECHRSVO__CID_R 0U 2360 #define XHC_ECHRSVO__CID_WIDTH 8U 2361 #define XHC_ECHRSVO__CID_RESETVALUE 0xffU 2362 #define XHC_ECHRSVO_WIDTH 32U 2363 #define XHC_ECHRSVO__WIDTH 32U 2364 #define XHC_ECHRSVO_ALL_L 31U 2365 #define XHC_ECHRSVO_ALL_R 0U 2366 #define XHC_ECHRSVO__ALL_L 31U 2367 #define XHC_ECHRSVO__ALL_R 0U 2368 #define XHC_ECHRSVO_DATAMASK 0xffffffffU 2369 #define XHC_ECHRSVO_RDWRMASK 0x00000000U 2370 #define XHC_ECHRSVO_RESETVALUE 0x000000ffU 2371 2372 #define XHC_ECHCTT_OFFSET 0xbf0U 2373 #define XHC_ECHCTT_BASE 0xbf0U 2374 #define XHC_ECHCTT__reserved_L 31U 2375 #define XHC_ECHCTT__reserved_R 16U 2376 #define XHC_ECHCTT__reserved_WIDTH 16U 2377 #define XHC_ECHCTT__reserved_RESETVALUE 0x0000U 2378 #define XHC_ECHCTT__NCP_L 15U 2379 #define XHC_ECHCTT__NCP_R 8U 2380 #define XHC_ECHCTT__NCP_WIDTH 8U 2381 #define XHC_ECHCTT__NCP_RESETVALUE 0x04U 2382 #define XHC_ECHCTT__CID_L 7U 2383 #define XHC_ECHCTT__CID_R 0U 2384 #define XHC_ECHCTT__CID_WIDTH 8U 2385 #define XHC_ECHCTT__CID_RESETVALUE 0xe0U 2386 #define XHC_ECHCTT_WIDTH 32U 2387 #define XHC_ECHCTT__WIDTH 32U 2388 #define XHC_ECHCTT_ALL_L 31U 2389 #define XHC_ECHCTT_ALL_R 0U 2390 #define XHC_ECHCTT__ALL_L 31U 2391 #define XHC_ECHCTT__ALL_R 0U 2392 #define XHC_ECHCTT_DATAMASK 0xffffffffU 2393 #define XHC_ECHCTT_RDWRMASK 0x00000000U 2394 #define XHC_ECHCTT_RESETVALUE 0x000004e0U 2395 2396 #define XHC_CTTMTS0_OFFSET 0xbf8U 2397 #define XHC_CTTMTS0_BASE 0xbf8U 2398 #define XHC_CTTMTS0__DCM 31U 2399 #define XHC_CTTMTS0__DCM_L 31U 2400 #define XHC_CTTMTS0__DCM_R 31U 2401 #define XHC_CTTMTS0__DCM_WIDTH 1U 2402 #define XHC_CTTMTS0__DCM_RESETVALUE 0x0U 2403 #define XHC_CTTMTS0__reserved_L 30U 2404 #define XHC_CTTMTS0__reserved_R 10U 2405 #define XHC_CTTMTS0__reserved_WIDTH 21U 2406 #define XHC_CTTMTS0__reserved_RESETVALUE 0x0U 2407 #define XHC_CTTMTS0__SLA_L 9U 2408 #define XHC_CTTMTS0__SLA_R 0U 2409 #define XHC_CTTMTS0__SLA_WIDTH 10U 2410 #define XHC_CTTMTS0__SLA_RESETVALUE 0x0U 2411 #define XHC_CTTMTS0_WIDTH 32U 2412 #define XHC_CTTMTS0__WIDTH 32U 2413 #define XHC_CTTMTS0_ALL_L 31U 2414 #define XHC_CTTMTS0_ALL_R 0U 2415 #define XHC_CTTMTS0__ALL_L 31U 2416 #define XHC_CTTMTS0__ALL_R 0U 2417 #define XHC_CTTMTS0_DATAMASK 0xffffffffU 2418 #define XHC_CTTMTS0_RDWRMASK 0x00000000U 2419 #define XHC_CTTMTS0_RESETVALUE 0x00000000U 2420 2421 #define XHC_CTTMTS1_OFFSET 0xbfcU 2422 #define XHC_CTTMTS1_BASE 0xbfcU 2423 #define XHC_CTTMTS1__TXF_L 25U 2424 #define XHC_CTTMTS1__TXF_R 16U 2425 #define XHC_CTTMTS1__TXF_WIDTH 10U 2426 #define XHC_CTTMTS1__TXF_RESETVALUE 0x0U 2427 #define XHC_CTTMTS1__reserved_L 15U 2428 #define XHC_CTTMTS1__reserved_R 10U 2429 #define XHC_CTTMTS1__reserved_WIDTH 6U 2430 #define XHC_CTTMTS1__reserved_RESETVALUE 0x0U 2431 #define XHC_CTTMTS1__RXF_L 9U 2432 #define XHC_CTTMTS1__RXF_R 0U 2433 #define XHC_CTTMTS1__RXF_WIDTH 10U 2434 #define XHC_CTTMTS1__RXF_RESETVALUE 0x0U 2435 #define XHC_CTTMTS1__RESERVED_L 31U 2436 #define XHC_CTTMTS1__RESERVED_R 26U 2437 #define XHC_CTTMTS1_WIDTH 26U 2438 #define XHC_CTTMTS1__WIDTH 26U 2439 #define XHC_CTTMTS1_ALL_L 25U 2440 #define XHC_CTTMTS1_ALL_R 0U 2441 #define XHC_CTTMTS1__ALL_L 25U 2442 #define XHC_CTTMTS1__ALL_R 0U 2443 #define XHC_CTTMTS1_DATAMASK 0x03ffffffU 2444 #define XHC_CTTMTS1_RDWRMASK 0xfc000000U 2445 #define XHC_CTTMTS1_RESETVALUE 0x0000000U 2446 2447 #define XHC_ECHBIU_OFFSET 0xc00U 2448 #define XHC_ECHBIU_BASE 0xc00U 2449 #define XHC_ECHBIU__CLK_L 31U 2450 #define XHC_ECHBIU__CLK_R 21U 2451 #define XHC_ECHBIU__CLK_WIDTH 11U 2452 #define XHC_ECHBIU__CLK_RESETVALUE 0x0U 2453 #define XHC_ECHBIU__reserved_L 20U 2454 #define XHC_ECHBIU__reserved_R 19U 2455 #define XHC_ECHBIU__reserved_WIDTH 2U 2456 #define XHC_ECHBIU__reserved_RESETVALUE 0x0U 2457 #define XHC_ECHBIU__WID_L 18U 2458 #define XHC_ECHBIU__WID_R 16U 2459 #define XHC_ECHBIU__WID_WIDTH 3U 2460 #define XHC_ECHBIU__WID_RESETVALUE 0x0U 2461 #define XHC_ECHBIU__NCP_L 15U 2462 #define XHC_ECHBIU__NCP_R 8U 2463 #define XHC_ECHBIU__NCP_WIDTH 8U 2464 #define XHC_ECHBIU__NCP_RESETVALUE 0x08U 2465 #define XHC_ECHBIU__CID_L 7U 2466 #define XHC_ECHBIU__CID_R 0U 2467 #define XHC_ECHBIU__CID_WIDTH 8U 2468 #define XHC_ECHBIU__CID_RESETVALUE 0xc0U 2469 #define XHC_ECHBIU_WIDTH 32U 2470 #define XHC_ECHBIU__WIDTH 32U 2471 #define XHC_ECHBIU_ALL_L 31U 2472 #define XHC_ECHBIU_ALL_R 0U 2473 #define XHC_ECHBIU__ALL_L 31U 2474 #define XHC_ECHBIU__ALL_R 0U 2475 #define XHC_ECHBIU_DATAMASK 0xffffffffU 2476 #define XHC_ECHBIU_RDWRMASK 0x00000000U 2477 #define XHC_ECHBIU_RESETVALUE 0x000008c0U 2478 2479 #define XHC_BIUSPC_OFFSET 0xc04U 2480 #define XHC_BIUSPC_BASE 0xc04U 2481 #define XHC_BIUSPC__MAJ_L 31U 2482 #define XHC_BIUSPC__MAJ_R 28U 2483 #define XHC_BIUSPC__MAJ_WIDTH 4U 2484 #define XHC_BIUSPC__MAJ_RESETVALUE 0x0U 2485 #define XHC_BIUSPC__MIN_L 27U 2486 #define XHC_BIUSPC__MIN_R 24U 2487 #define XHC_BIUSPC__MIN_WIDTH 4U 2488 #define XHC_BIUSPC__MIN_RESETVALUE 0x0U 2489 #define XHC_BIUSPC__RLS_L 23U 2490 #define XHC_BIUSPC__RLS_R 20U 2491 #define XHC_BIUSPC__RLS_WIDTH 4U 2492 #define XHC_BIUSPC__RLS_RESETVALUE 0x0U 2493 #define XHC_BIUSPC__reserved_L 19U 2494 #define XHC_BIUSPC__reserved_R 4U 2495 #define XHC_BIUSPC__reserved_WIDTH 16U 2496 #define XHC_BIUSPC__reserved_RESETVALUE 0x0000U 2497 #define XHC_BIUSPC__SPI_L 3U 2498 #define XHC_BIUSPC__SPI_R 2U 2499 #define XHC_BIUSPC__SPI_WIDTH 2U 2500 #define XHC_BIUSPC__SPI_RESETVALUE 0x3U 2501 #define XHC_BIUSPC__TYP_L 1U 2502 #define XHC_BIUSPC__TYP_R 0U 2503 #define XHC_BIUSPC__TYP_WIDTH 2U 2504 #define XHC_BIUSPC__TYP_RESETVALUE 0x0U 2505 #define XHC_BIUSPC_WIDTH 32U 2506 #define XHC_BIUSPC__WIDTH 32U 2507 #define XHC_BIUSPC_ALL_L 31U 2508 #define XHC_BIUSPC_ALL_R 0U 2509 #define XHC_BIUSPC__ALL_L 31U 2510 #define XHC_BIUSPC__ALL_R 0U 2511 #define XHC_BIUSPC_DATAMASK 0xffffffffU 2512 #define XHC_BIUSPC_RDWRMASK 0x00000000U 2513 #define XHC_BIUSPC_RESETVALUE 0x0000000cU 2514 2515 #define XHC_AXIWRA_OFFSET 0xc08U 2516 #define XHC_AXIWRA_BASE 0xc08U 2517 #define XHC_AXIWRA__WTS_L 31U 2518 #define XHC_AXIWRA__WTS_R 28U 2519 #define XHC_AXIWRA__WTS_WIDTH 4U 2520 #define XHC_AXIWRA__WTS_RESETVALUE 0x2U 2521 #define XHC_AXIWRA__WUA_L 24U 2522 #define XHC_AXIWRA__WUA_R 16U 2523 #define XHC_AXIWRA__WUA_WIDTH 9U 2524 #define XHC_AXIWRA__WUA_RESETVALUE 0x0U 2525 #define XHC_AXIWRA__reserved_L 15U 2526 #define XHC_AXIWRA__reserved_R 10U 2527 #define XHC_AXIWRA__reserved_WIDTH 6U 2528 #define XHC_AXIWRA__reserved_RESETVALUE 0x0U 2529 #define XHC_AXIWRA__BYP 9U 2530 #define XHC_AXIWRA__BYP_L 9U 2531 #define XHC_AXIWRA__BYP_R 9U 2532 #define XHC_AXIWRA__BYP_WIDTH 1U 2533 #define XHC_AXIWRA__BYP_RESETVALUE 0x0U 2534 #define XHC_AXIWRA__WSA_L 8U 2535 #define XHC_AXIWRA__WSA_R 0U 2536 #define XHC_AXIWRA__WSA_WIDTH 9U 2537 #define XHC_AXIWRA__WSA_RESETVALUE 0x0U 2538 #define XHC_AXIWRA__RESERVED_L 27U 2539 #define XHC_AXIWRA__RESERVED_R 25U 2540 #define XHC_AXIWRA_WIDTH 32U 2541 #define XHC_AXIWRA__WIDTH 32U 2542 #define XHC_AXIWRA_ALL_L 31U 2543 #define XHC_AXIWRA_ALL_R 0U 2544 #define XHC_AXIWRA__ALL_L 31U 2545 #define XHC_AXIWRA__ALL_R 0U 2546 #define XHC_AXIWRA_DATAMASK 0xf1ffffffU 2547 #define XHC_AXIWRA_RDWRMASK 0x0e000000U 2548 #define XHC_AXIWRA_RESETVALUE 0x20000000U 2549 2550 #define XHC_AXIRDA_OFFSET 0xc0cU 2551 #define XHC_AXIRDA_BASE 0xc0cU 2552 #define XHC_AXIRDA__RTS_L 31U 2553 #define XHC_AXIRDA__RTS_R 28U 2554 #define XHC_AXIRDA__RTS_WIDTH 4U 2555 #define XHC_AXIRDA__RTS_RESETVALUE 0x2U 2556 #define XHC_AXIRDA__RFPC 27U 2557 #define XHC_AXIRDA__RFPC_L 27U 2558 #define XHC_AXIRDA__RFPC_R 27U 2559 #define XHC_AXIRDA__RFPC_WIDTH 1U 2560 #define XHC_AXIRDA__RFPC_RESETVALUE 0x0U 2561 #define XHC_AXIRDA__RUA_L 24U 2562 #define XHC_AXIRDA__RUA_R 16U 2563 #define XHC_AXIRDA__RUA_WIDTH 9U 2564 #define XHC_AXIRDA__RUA_RESETVALUE 0x0U 2565 #define XHC_AXIRDA__reserved_L 15U 2566 #define XHC_AXIRDA__reserved_R 9U 2567 #define XHC_AXIRDA__reserved_WIDTH 7U 2568 #define XHC_AXIRDA__reserved_RESETVALUE 0x0U 2569 #define XHC_AXIRDA__RSA_L 8U 2570 #define XHC_AXIRDA__RSA_R 0U 2571 #define XHC_AXIRDA__RSA_WIDTH 9U 2572 #define XHC_AXIRDA__RSA_RESETVALUE 0x0U 2573 #define XHC_AXIRDA__RESERVED_L 26U 2574 #define XHC_AXIRDA__RESERVED_R 25U 2575 #define XHC_AXIRDA_WIDTH 32U 2576 #define XHC_AXIRDA__WIDTH 32U 2577 #define XHC_AXIRDA_ALL_L 31U 2578 #define XHC_AXIRDA_ALL_R 0U 2579 #define XHC_AXIRDA__ALL_L 31U 2580 #define XHC_AXIRDA__ALL_R 0U 2581 #define XHC_AXIRDA_DATAMASK 0xf9ffffffU 2582 #define XHC_AXIRDA_RDWRMASK 0x06000000U 2583 #define XHC_AXIRDA_RESETVALUE 0x20000000U 2584 2585 #define XHC_AXILPM_OFFSET 0xc10U 2586 #define XHC_AXILPM_BASE 0xc10U 2587 #define XHC_AXILPM__ENB 31U 2588 #define XHC_AXILPM__ENB_L 31U 2589 #define XHC_AXILPM__ENB_R 31U 2590 #define XHC_AXILPM__ENB_WIDTH 1U 2591 #define XHC_AXILPM__ENB_RESETVALUE 0x0U 2592 #define XHC_AXILPM__reserved_L 30U 2593 #define XHC_AXILPM__reserved_R 3U 2594 #define XHC_AXILPM__reserved_WIDTH 28U 2595 #define XHC_AXILPM__reserved_RESETVALUE 0x0000000U 2596 #define XHC_AXILPM__ITT_L 2U 2597 #define XHC_AXILPM__ITT_R 0U 2598 #define XHC_AXILPM__ITT_WIDTH 3U 2599 #define XHC_AXILPM__ITT_RESETVALUE 0x0U 2600 #define XHC_AXILPM_WIDTH 32U 2601 #define XHC_AXILPM__WIDTH 32U 2602 #define XHC_AXILPM_ALL_L 31U 2603 #define XHC_AXILPM_ALL_R 0U 2604 #define XHC_AXILPM__ALL_L 31U 2605 #define XHC_AXILPM__ALL_R 0U 2606 #define XHC_AXILPM_DATAMASK 0xffffffffU 2607 #define XHC_AXILPM_RDWRMASK 0x00000000U 2608 #define XHC_AXILPM_RESETVALUE 0x00000000U 2609 2610 #define XHC_AXIQOS_OFFSET 0xc14U 2611 #define XHC_AXIQOS_BASE 0xc14U 2612 #define XHC_AXIQOS__WQOS3_L 31U 2613 #define XHC_AXIQOS__WQOS3_R 28U 2614 #define XHC_AXIQOS__WQOS3_WIDTH 4U 2615 #define XHC_AXIQOS__WQOS3_RESETVALUE 0x0U 2616 #define XHC_AXIQOS__WQOS2_L 27U 2617 #define XHC_AXIQOS__WQOS2_R 24U 2618 #define XHC_AXIQOS__WQOS2_WIDTH 4U 2619 #define XHC_AXIQOS__WQOS2_RESETVALUE 0x0U 2620 #define XHC_AXIQOS__WQOS1_L 23U 2621 #define XHC_AXIQOS__WQOS1_R 20U 2622 #define XHC_AXIQOS__WQOS1_WIDTH 4U 2623 #define XHC_AXIQOS__WQOS1_RESETVALUE 0x0U 2624 #define XHC_AXIQOS__WQOS0_L 19U 2625 #define XHC_AXIQOS__WQOS0_R 16U 2626 #define XHC_AXIQOS__WQOS0_WIDTH 4U 2627 #define XHC_AXIQOS__WQOS0_RESETVALUE 0x0U 2628 #define XHC_AXIQOS__RQOS3_L 15U 2629 #define XHC_AXIQOS__RQOS3_R 12U 2630 #define XHC_AXIQOS__RQOS3_WIDTH 4U 2631 #define XHC_AXIQOS__RQOS3_RESETVALUE 0x0U 2632 #define XHC_AXIQOS__RQOS2_L 11U 2633 #define XHC_AXIQOS__RQOS2_R 8U 2634 #define XHC_AXIQOS__RQOS2_WIDTH 4U 2635 #define XHC_AXIQOS__RQOS2_RESETVALUE 0x0U 2636 #define XHC_AXIQOS__RQOS1_L 7U 2637 #define XHC_AXIQOS__RQOS1_R 4U 2638 #define XHC_AXIQOS__RQOS1_WIDTH 4U 2639 #define XHC_AXIQOS__RQOS1_RESETVALUE 0x0U 2640 #define XHC_AXIQOS__RQOS0_L 3U 2641 #define XHC_AXIQOS__RQOS0_R 0U 2642 #define XHC_AXIQOS__RQOS0_WIDTH 4U 2643 #define XHC_AXIQOS__RQOS0_RESETVALUE 0x0U 2644 #define XHC_AXIQOS_WIDTH 32U 2645 #define XHC_AXIQOS__WIDTH 32U 2646 #define XHC_AXIQOS_ALL_L 31U 2647 #define XHC_AXIQOS_ALL_R 0U 2648 #define XHC_AXIQOS__ALL_L 31U 2649 #define XHC_AXIQOS__ALL_R 0U 2650 #define XHC_AXIQOS_DATAMASK 0xffffffffU 2651 #define XHC_AXIQOS_RDWRMASK 0x00000000U 2652 #define XHC_AXIQOS_RESETVALUE 0x00000000U 2653 2654 #define XHC_ECHCSR_OFFSET 0xc20U 2655 #define XHC_ECHCSR_BASE 0xc20U 2656 #define XHC_ECHCSR__CLK_L 31U 2657 #define XHC_ECHCSR__CLK_R 21U 2658 #define XHC_ECHCSR__CLK_WIDTH 11U 2659 #define XHC_ECHCSR__CLK_RESETVALUE 0x0U 2660 #define XHC_ECHCSR__reserved_L 20U 2661 #define XHC_ECHCSR__reserved_R 19U 2662 #define XHC_ECHCSR__reserved_WIDTH 2U 2663 #define XHC_ECHCSR__reserved_RESETVALUE 0x0U 2664 #define XHC_ECHCSR__WID_L 18U 2665 #define XHC_ECHCSR__WID_R 16U 2666 #define XHC_ECHCSR__WID_WIDTH 3U 2667 #define XHC_ECHCSR__WID_RESETVALUE 0x0U 2668 #define XHC_ECHCSR__NCP_L 15U 2669 #define XHC_ECHCSR__NCP_R 8U 2670 #define XHC_ECHCSR__NCP_WIDTH 8U 2671 #define XHC_ECHCSR__NCP_RESETVALUE 0x04U 2672 #define XHC_ECHCSR__CID_L 7U 2673 #define XHC_ECHCSR__CID_R 0U 2674 #define XHC_ECHCSR__CID_WIDTH 8U 2675 #define XHC_ECHCSR__CID_RESETVALUE 0xc1U 2676 #define XHC_ECHCSR_WIDTH 32U 2677 #define XHC_ECHCSR__WIDTH 32U 2678 #define XHC_ECHCSR_ALL_L 31U 2679 #define XHC_ECHCSR_ALL_R 0U 2680 #define XHC_ECHCSR__ALL_L 31U 2681 #define XHC_ECHCSR__ALL_R 0U 2682 #define XHC_ECHCSR_DATAMASK 0xffffffffU 2683 #define XHC_ECHCSR_RDWRMASK 0x00000000U 2684 #define XHC_ECHCSR_RESETVALUE 0x000004c1U 2685 2686 #define XHC_CSRSPC_OFFSET 0xc24U 2687 #define XHC_CSRSPC_BASE 0xc24U 2688 #define XHC_CSRSPC__MAJ_L 31U 2689 #define XHC_CSRSPC__MAJ_R 28U 2690 #define XHC_CSRSPC__MAJ_WIDTH 4U 2691 #define XHC_CSRSPC__MAJ_RESETVALUE 0x0U 2692 #define XHC_CSRSPC__MIN_L 27U 2693 #define XHC_CSRSPC__MIN_R 24U 2694 #define XHC_CSRSPC__MIN_WIDTH 4U 2695 #define XHC_CSRSPC__MIN_RESETVALUE 0x0U 2696 #define XHC_CSRSPC__RLS_L 23U 2697 #define XHC_CSRSPC__RLS_R 20U 2698 #define XHC_CSRSPC__RLS_WIDTH 4U 2699 #define XHC_CSRSPC__RLS_RESETVALUE 0x0U 2700 #define XHC_CSRSPC__reserved_L 19U 2701 #define XHC_CSRSPC__reserved_R 3U 2702 #define XHC_CSRSPC__reserved_WIDTH 17U 2703 #define XHC_CSRSPC__reserved_RESETVALUE 0x0U 2704 #define XHC_CSRSPC__ASP 2U 2705 #define XHC_CSRSPC__ASP_L 2U 2706 #define XHC_CSRSPC__ASP_R 2U 2707 #define XHC_CSRSPC__ASP_WIDTH 1U 2708 #define XHC_CSRSPC__ASP_RESETVALUE 0x0U 2709 #define XHC_CSRSPC__TYP_L 1U 2710 #define XHC_CSRSPC__TYP_R 0U 2711 #define XHC_CSRSPC__TYP_WIDTH 2U 2712 #define XHC_CSRSPC__TYP_RESETVALUE 0x0U 2713 #define XHC_CSRSPC_WIDTH 32U 2714 #define XHC_CSRSPC__WIDTH 32U 2715 #define XHC_CSRSPC_ALL_L 31U 2716 #define XHC_CSRSPC_ALL_R 0U 2717 #define XHC_CSRSPC__ALL_L 31U 2718 #define XHC_CSRSPC__ALL_R 0U 2719 #define XHC_CSRSPC_DATAMASK 0xffffffffU 2720 #define XHC_CSRSPC_RDWRMASK 0x00000000U 2721 #define XHC_CSRSPC_RESETVALUE 0x00000000U 2722 2723 #define XHC_ECHAIU_OFFSET 0xc30U 2724 #define XHC_ECHAIU_BASE 0xc30U 2725 #define XHC_ECHAIU__DMA_L 31U 2726 #define XHC_ECHAIU__DMA_R 30U 2727 #define XHC_ECHAIU__DMA_WIDTH 2U 2728 #define XHC_ECHAIU__DMA_RESETVALUE 0x1U 2729 #define XHC_ECHAIU__PBRS_L 29U 2730 #define XHC_ECHAIU__PBRS_R 28U 2731 #define XHC_ECHAIU__PBRS_WIDTH 2U 2732 #define XHC_ECHAIU__PBRS_RESETVALUE 0x0U 2733 #define XHC_ECHAIU__PBR2_L 27U 2734 #define XHC_ECHAIU__PBR2_R 26U 2735 #define XHC_ECHAIU__PBR2_WIDTH 2U 2736 #define XHC_ECHAIU__PBR2_RESETVALUE 0x0U 2737 #define XHC_ECHAIU__SCHS_L 25U 2738 #define XHC_ECHAIU__SCHS_R 24U 2739 #define XHC_ECHAIU__SCHS_WIDTH 2U 2740 #define XHC_ECHAIU__SCHS_RESETVALUE 0x0U 2741 #define XHC_ECHAIU__SCH2_L 23U 2742 #define XHC_ECHAIU__SCH2_R 22U 2743 #define XHC_ECHAIU__SCH2_WIDTH 2U 2744 #define XHC_ECHAIU__SCH2_RESETVALUE 0x0U 2745 #define XHC_ECHAIU__CHMS_L 21U 2746 #define XHC_ECHAIU__CHMS_R 20U 2747 #define XHC_ECHAIU__CHMS_WIDTH 2U 2748 #define XHC_ECHAIU__CHMS_RESETVALUE 0x3U 2749 #define XHC_ECHAIU__CHM2_L 19U 2750 #define XHC_ECHAIU__CHM2_R 18U 2751 #define XHC_ECHAIU__CHM2_WIDTH 2U 2752 #define XHC_ECHAIU__CHM2_RESETVALUE 0x0U 2753 #define XHC_ECHAIU__reserved_L 17U 2754 #define XHC_ECHAIU__reserved_R 16U 2755 #define XHC_ECHAIU__reserved_WIDTH 2U 2756 #define XHC_ECHAIU__reserved_RESETVALUE 0x0U 2757 #define XHC_ECHAIU__NCP_L 15U 2758 #define XHC_ECHAIU__NCP_R 8U 2759 #define XHC_ECHAIU__NCP_WIDTH 8U 2760 #define XHC_ECHAIU__NCP_RESETVALUE 0x04U 2761 #define XHC_ECHAIU__CID_L 7U 2762 #define XHC_ECHAIU__CID_R 0U 2763 #define XHC_ECHAIU__CID_WIDTH 8U 2764 #define XHC_ECHAIU__CID_RESETVALUE 0xc2U 2765 #define XHC_ECHAIU_WIDTH 32U 2766 #define XHC_ECHAIU__WIDTH 32U 2767 #define XHC_ECHAIU_ALL_L 31U 2768 #define XHC_ECHAIU_ALL_R 0U 2769 #define XHC_ECHAIU__ALL_L 31U 2770 #define XHC_ECHAIU__ALL_R 0U 2771 #define XHC_ECHAIU_DATAMASK 0xffffffffU 2772 #define XHC_ECHAIU_RDWRMASK 0x00000000U 2773 #define XHC_ECHAIU_RESETVALUE 0x403004c2U 2774 2775 #define XHC_AIUDMA_OFFSET 0xc34U 2776 #define XHC_AIUDMA_BASE 0xc34U 2777 #define XHC_AIUDMA__WRMB_L 31U 2778 #define XHC_AIUDMA__WRMB_R 28U 2779 #define XHC_AIUDMA__WRMB_WIDTH 4U 2780 #define XHC_AIUDMA__WRMB_RESETVALUE 0x0U 2781 #define XHC_AIUDMA__WRD_L 27U 2782 #define XHC_AIUDMA__WRD_R 26U 2783 #define XHC_AIUDMA__WRD_WIDTH 2U 2784 #define XHC_AIUDMA__WRD_RESETVALUE 0x0U 2785 #define XHC_AIUDMA__WED_L 25U 2786 #define XHC_AIUDMA__WED_R 24U 2787 #define XHC_AIUDMA__WED_WIDTH 2U 2788 #define XHC_AIUDMA__WED_RESETVALUE 0x0U 2789 #define XHC_AIUDMA__WMS_L 23U 2790 #define XHC_AIUDMA__WMS_R 22U 2791 #define XHC_AIUDMA__WMS_WIDTH 2U 2792 #define XHC_AIUDMA__WMS_RESETVALUE 0x0U 2793 #define XHC_AIUDMA__WMI_L 21U 2794 #define XHC_AIUDMA__WMI_R 20U 2795 #define XHC_AIUDMA__WMI_WIDTH 2U 2796 #define XHC_AIUDMA__WMI_RESETVALUE 0x0U 2797 #define XHC_AIUDMA__WPF_L 19U 2798 #define XHC_AIUDMA__WPF_R 16U 2799 #define XHC_AIUDMA__WPF_WIDTH 4U 2800 #define XHC_AIUDMA__WPF_RESETVALUE 0x6U 2801 #define XHC_AIUDMA__RRMB_L 15U 2802 #define XHC_AIUDMA__RRMB_R 12U 2803 #define XHC_AIUDMA__RRMB_WIDTH 4U 2804 #define XHC_AIUDMA__RRMB_RESETVALUE 0x0U 2805 #define XHC_AIUDMA__RTD_L 11U 2806 #define XHC_AIUDMA__RTD_R 10U 2807 #define XHC_AIUDMA__RTD_WIDTH 2U 2808 #define XHC_AIUDMA__RTD_RESETVALUE 0x0U 2809 #define XHC_AIUDMA__RTF_L 9U 2810 #define XHC_AIUDMA__RTF_R 8U 2811 #define XHC_AIUDMA__RTF_WIDTH 2U 2812 #define XHC_AIUDMA__RTF_RESETVALUE 0x0U 2813 #define XHC_AIUDMA__RM_S_L 7U 2814 #define XHC_AIUDMA__RM_S_R 6U 2815 #define XHC_AIUDMA__RM_S_WIDTH 2U 2816 #define XHC_AIUDMA__RM_S_RESETVALUE 0x0U 2817 #define XHC_AIUDMA__TFBS_L 5U 2818 #define XHC_AIUDMA__TFBS_R 3U 2819 #define XHC_AIUDMA__TFBS_WIDTH 3U 2820 #define XHC_AIUDMA__TFBS_RESETVALUE 0x0U 2821 #define XHC_AIUDMA__reserved_L 2U 2822 #define XHC_AIUDMA__reserved_R 0U 2823 #define XHC_AIUDMA__reserved_WIDTH 3U 2824 #define XHC_AIUDMA__reserved_RESETVALUE 0x0U 2825 #define XHC_AIUDMA_WIDTH 32U 2826 #define XHC_AIUDMA__WIDTH 32U 2827 #define XHC_AIUDMA_ALL_L 31U 2828 #define XHC_AIUDMA_ALL_R 0U 2829 #define XHC_AIUDMA__ALL_L 31U 2830 #define XHC_AIUDMA__ALL_R 0U 2831 #define XHC_AIUDMA_DATAMASK 0xffffffffU 2832 #define XHC_AIUDMA_RDWRMASK 0x00000000U 2833 #define XHC_AIUDMA_RESETVALUE 0x00060000U 2834 2835 #define XHC_AIUFLA_OFFSET 0xc38U 2836 #define XHC_AIUFLA_BASE 0xc38U 2837 #define XHC_AIUFLA__ACLK_L 31U 2838 #define XHC_AIUFLA__ACLK_R 23U 2839 #define XHC_AIUFLA__ACLK_WIDTH 9U 2840 #define XHC_AIUFLA__ACLK_RESETVALUE 0x0U 2841 #define XHC_AIUFLA__MFLV_L 22U 2842 #define XHC_AIUFLA__MFLV_R 7U 2843 #define XHC_AIUFLA__MFLV_WIDTH 16U 2844 #define XHC_AIUFLA__MFLV_RESETVALUE 0x0000U 2845 #define XHC_AIUFLA__NFC 6U 2846 #define XHC_AIUFLA__NFC_L 6U 2847 #define XHC_AIUFLA__NFC_R 6U 2848 #define XHC_AIUFLA__NFC_WIDTH 1U 2849 #define XHC_AIUFLA__NFC_RESETVALUE 0x1U 2850 #define XHC_AIUFLA__FLADJ_L 5U 2851 #define XHC_AIUFLA__FLADJ_R 0U 2852 #define XHC_AIUFLA__FLADJ_WIDTH 6U 2853 #define XHC_AIUFLA__FLADJ_RESETVALUE 0x20U 2854 #define XHC_AIUFLA_WIDTH 32U 2855 #define XHC_AIUFLA__WIDTH 32U 2856 #define XHC_AIUFLA_ALL_L 31U 2857 #define XHC_AIUFLA_ALL_R 0U 2858 #define XHC_AIUFLA__ALL_L 31U 2859 #define XHC_AIUFLA__ALL_R 0U 2860 #define XHC_AIUFLA_DATAMASK 0xffffffffU 2861 #define XHC_AIUFLA_RDWRMASK 0x00000000U 2862 #define XHC_AIUFLA_RESETVALUE 0x00000060U 2863 2864 #define XHC_AIUCFG_OFFSET 0xc3cU 2865 #define XHC_AIUCFG_BASE 0xc3cU 2866 #define XHC_AIUCFG__ISO_L 30U 2867 #define XHC_AIUCFG__ISO_R 28U 2868 #define XHC_AIUCFG__ISO_WIDTH 3U 2869 #define XHC_AIUCFG__ISO_RESETVALUE 0x0U 2870 #define XHC_AIUCFG__EPC_L 26U 2871 #define XHC_AIUCFG__EPC_R 24U 2872 #define XHC_AIUCFG__EPC_WIDTH 3U 2873 #define XHC_AIUCFG__EPC_RESETVALUE 0x5U 2874 #define XHC_AIUCFG__PTQ_L 22U 2875 #define XHC_AIUCFG__PTQ_R 20U 2876 #define XHC_AIUCFG__PTQ_WIDTH 3U 2877 #define XHC_AIUCFG__PTQ_RESETVALUE 0x3U 2878 #define XHC_AIUCFG__NTQ_L 18U 2879 #define XHC_AIUCFG__NTQ_R 16U 2880 #define XHC_AIUCFG__NTQ_WIDTH 3U 2881 #define XHC_AIUCFG__NTQ_RESETVALUE 0x3U 2882 #define XHC_AIUCFG__HID 15U 2883 #define XHC_AIUCFG__HID_L 15U 2884 #define XHC_AIUCFG__HID_R 15U 2885 #define XHC_AIUCFG__HID_WIDTH 1U 2886 #define XHC_AIUCFG__HID_RESETVALUE 0x0U 2887 #define XHC_AIUCFG__EPS_L 14U 2888 #define XHC_AIUCFG__EPS_R 12U 2889 #define XHC_AIUCFG__EPS_WIDTH 3U 2890 #define XHC_AIUCFG__EPS_RESETVALUE 0x0U 2891 #define XHC_AIUCFG__reserved_L 11U 2892 #define XHC_AIUCFG__reserved_R 9U 2893 #define XHC_AIUCFG__reserved_WIDTH 3U 2894 #define XHC_AIUCFG__reserved_RESETVALUE 0x0U 2895 #define XHC_AIUCFG__PEP2_L 8U 2896 #define XHC_AIUCFG__PEP2_R 6U 2897 #define XHC_AIUCFG__PEP2_WIDTH 3U 2898 #define XHC_AIUCFG__PEP2_RESETVALUE 0x4U 2899 #define XHC_AIUCFG__MELADJ_L 5U 2900 #define XHC_AIUCFG__MELADJ_R 0U 2901 #define XHC_AIUCFG__MELADJ_WIDTH 6U 2902 #define XHC_AIUCFG__MELADJ_RESETVALUE 0x0U 2903 #define XHC_AIUCFG__RESERVED_0 31U 2904 #define XHC_AIUCFG__RESERVED_0_L 31U 2905 #define XHC_AIUCFG__RESERVED_0_R 31U 2906 #define XHC_AIUCFG__RESERVED_1 27U 2907 #define XHC_AIUCFG__RESERVED_1_L 27U 2908 #define XHC_AIUCFG__RESERVED_1_R 27U 2909 #define XHC_AIUCFG__RESERVED_2 23U 2910 #define XHC_AIUCFG__RESERVED_2_L 23U 2911 #define XHC_AIUCFG__RESERVED_2_R 23U 2912 #define XHC_AIUCFG__RESERVED_3 19U 2913 #define XHC_AIUCFG__RESERVED_3_L 19U 2914 #define XHC_AIUCFG__RESERVED_3_R 19U 2915 #define XHC_AIUCFG_WIDTH 31U 2916 #define XHC_AIUCFG__WIDTH 31U 2917 #define XHC_AIUCFG_ALL_L 30U 2918 #define XHC_AIUCFG_ALL_R 0U 2919 #define XHC_AIUCFG__ALL_L 30U 2920 #define XHC_AIUCFG__ALL_R 0U 2921 #define XHC_AIUCFG_DATAMASK 0x7777ffffU 2922 #define XHC_AIUCFG_RDWRMASK 0x88880000U 2923 #define XHC_AIUCFG_RESETVALUE 0x05330100U 2924 2925 #define XHC_ECHFSC_OFFSET 0xc40U 2926 #define XHC_ECHFSC_BASE 0xc40U 2927 #define XHC_ECHFSC__reserved_L 31U 2928 #define XHC_ECHFSC__reserved_R 24U 2929 #define XHC_ECHFSC__reserved_WIDTH 8U 2930 #define XHC_ECHFSC__reserved_RESETVALUE 0x00U 2931 #define XHC_ECHFSC__WRMB_L 23U 2932 #define XHC_ECHFSC__WRMB_R 20U 2933 #define XHC_ECHFSC__WRMB_WIDTH 4U 2934 #define XHC_ECHFSC__WRMB_RESETVALUE 0x0U 2935 #define XHC_ECHFSC__RRMB_L 19U 2936 #define XHC_ECHFSC__RRMB_R 16U 2937 #define XHC_ECHFSC__RRMB_WIDTH 4U 2938 #define XHC_ECHFSC__RRMB_RESETVALUE 0x0U 2939 #define XHC_ECHFSC__NCP_L 15U 2940 #define XHC_ECHFSC__NCP_R 8U 2941 #define XHC_ECHFSC__NCP_WIDTH 8U 2942 #define XHC_ECHFSC__NCP_RESETVALUE 0x50U 2943 #define XHC_ECHFSC__CID_L 7U 2944 #define XHC_ECHFSC__CID_R 0U 2945 #define XHC_ECHFSC__CID_WIDTH 8U 2946 #define XHC_ECHFSC__CID_RESETVALUE 0xc3U 2947 #define XHC_ECHFSC_WIDTH 32U 2948 #define XHC_ECHFSC__WIDTH 32U 2949 #define XHC_ECHFSC_ALL_L 31U 2950 #define XHC_ECHFSC_ALL_R 0U 2951 #define XHC_ECHFSC__ALL_L 31U 2952 #define XHC_ECHFSC__ALL_R 0U 2953 #define XHC_ECHFSC_DATAMASK 0xffffffffU 2954 #define XHC_ECHFSC_RDWRMASK 0x00000000U 2955 #define XHC_ECHFSC_RESETVALUE 0x000050c3U 2956 2957 #define XHC_FSCPOC_OFFSET 0xc54U 2958 #define XHC_FSCPOC_BASE 0xc54U 2959 #define XHC_FSCPOC__NCS_L 31U 2960 #define XHC_FSCPOC__NCS_R 28U 2961 #define XHC_FSCPOC__NCS_WIDTH 4U 2962 #define XHC_FSCPOC__NCS_RESETVALUE 0x0U 2963 #define XHC_FSCPOC__FSIZ_L 22U 2964 #define XHC_FSCPOC__FSIZ_R 18U 2965 #define XHC_FSCPOC__FSIZ_WIDTH 5U 2966 #define XHC_FSCPOC__FSIZ_RESETVALUE 0x0U 2967 #define XHC_FSCPOC__PSIZ_L 16U 2968 #define XHC_FSCPOC__PSIZ_R 12U 2969 #define XHC_FSCPOC__PSIZ_WIDTH 5U 2970 #define XHC_FSCPOC__PSIZ_RESETVALUE 0x0U 2971 #define XHC_FSCPOC__reserved_L 11U 2972 #define XHC_FSCPOC__reserved_R 5U 2973 #define XHC_FSCPOC__reserved_WIDTH 7U 2974 #define XHC_FSCPOC__reserved_RESETVALUE 0x0U 2975 #define XHC_FSCPOC__TSIZ_L 4U 2976 #define XHC_FSCPOC__TSIZ_R 0U 2977 #define XHC_FSCPOC__TSIZ_WIDTH 5U 2978 #define XHC_FSCPOC__TSIZ_RESETVALUE 0x0U 2979 #define XHC_FSCPOC__RESERVED_L 27U 2980 #define XHC_FSCPOC__RESERVED_R 23U 2981 #define XHC_FSCPOC_WIDTH 32U 2982 #define XHC_FSCPOC__WIDTH 32U 2983 #define XHC_FSCPOC_ALL_L 31U 2984 #define XHC_FSCPOC_ALL_R 0U 2985 #define XHC_FSCPOC__ALL_L 31U 2986 #define XHC_FSCPOC__ALL_R 0U 2987 #define XHC_FSCPOC_DATAMASK 0xf07dffffU 2988 #define XHC_FSCPOC_RDWRMASK 0x0f820000U 2989 #define XHC_FSCPOC_RESETVALUE 0x00000000U 2990 2991 #define XHC_FSCGOC_OFFSET 0xc58U 2992 #define XHC_FSCGOC_BASE 0xc58U 2993 #define XHC_FSCGOC__NCS_L 31U 2994 #define XHC_FSCGOC__NCS_R 28U 2995 #define XHC_FSCGOC__NCS_WIDTH 4U 2996 #define XHC_FSCGOC__NCS_RESETVALUE 0x0U 2997 #define XHC_FSCGOC__FSIZ_L 22U 2998 #define XHC_FSCGOC__FSIZ_R 18U 2999 #define XHC_FSCGOC__FSIZ_WIDTH 5U 3000 #define XHC_FSCGOC__FSIZ_RESETVALUE 0x0U 3001 #define XHC_FSCGOC__PSIZ_L 16U 3002 #define XHC_FSCGOC__PSIZ_R 12U 3003 #define XHC_FSCGOC__PSIZ_WIDTH 5U 3004 #define XHC_FSCGOC__PSIZ_RESETVALUE 0x0U 3005 #define XHC_FSCGOC__reserved_L 11U 3006 #define XHC_FSCGOC__reserved_R 5U 3007 #define XHC_FSCGOC__reserved_WIDTH 7U 3008 #define XHC_FSCGOC__reserved_RESETVALUE 0x0U 3009 #define XHC_FSCGOC__TSIZ_L 4U 3010 #define XHC_FSCGOC__TSIZ_R 0U 3011 #define XHC_FSCGOC__TSIZ_WIDTH 5U 3012 #define XHC_FSCGOC__TSIZ_RESETVALUE 0x0U 3013 #define XHC_FSCGOC__RESERVED_L 27U 3014 #define XHC_FSCGOC__RESERVED_R 23U 3015 #define XHC_FSCGOC_WIDTH 32U 3016 #define XHC_FSCGOC__WIDTH 32U 3017 #define XHC_FSCGOC_ALL_L 31U 3018 #define XHC_FSCGOC_ALL_R 0U 3019 #define XHC_FSCGOC__ALL_L 31U 3020 #define XHC_FSCGOC__ALL_R 0U 3021 #define XHC_FSCGOC_DATAMASK 0xf07dffffU 3022 #define XHC_FSCGOC_RDWRMASK 0x0f820000U 3023 #define XHC_FSCGOC_RESETVALUE 0x00000000U 3024 3025 #define XHC_FSCNOC_OFFSET 0xc5cU 3026 #define XHC_FSCNOC_BASE 0xc5cU 3027 #define XHC_FSCNOC__NCS_L 31U 3028 #define XHC_FSCNOC__NCS_R 28U 3029 #define XHC_FSCNOC__NCS_WIDTH 4U 3030 #define XHC_FSCNOC__NCS_RESETVALUE 0x0U 3031 #define XHC_FSCNOC__FSIZ_L 22U 3032 #define XHC_FSCNOC__FSIZ_R 18U 3033 #define XHC_FSCNOC__FSIZ_WIDTH 5U 3034 #define XHC_FSCNOC__FSIZ_RESETVALUE 0x0U 3035 #define XHC_FSCNOC__PSIZ_L 16U 3036 #define XHC_FSCNOC__PSIZ_R 12U 3037 #define XHC_FSCNOC__PSIZ_WIDTH 5U 3038 #define XHC_FSCNOC__PSIZ_RESETVALUE 0x0U 3039 #define XHC_FSCNOC__reserved_L 11U 3040 #define XHC_FSCNOC__reserved_R 5U 3041 #define XHC_FSCNOC__reserved_WIDTH 7U 3042 #define XHC_FSCNOC__reserved_RESETVALUE 0x0U 3043 #define XHC_FSCNOC__TSIZ_L 4U 3044 #define XHC_FSCNOC__TSIZ_R 0U 3045 #define XHC_FSCNOC__TSIZ_WIDTH 5U 3046 #define XHC_FSCNOC__TSIZ_RESETVALUE 0x0U 3047 #define XHC_FSCNOC__RESERVED_L 27U 3048 #define XHC_FSCNOC__RESERVED_R 23U 3049 #define XHC_FSCNOC_WIDTH 32U 3050 #define XHC_FSCNOC__WIDTH 32U 3051 #define XHC_FSCNOC_ALL_L 31U 3052 #define XHC_FSCNOC_ALL_R 0U 3053 #define XHC_FSCNOC__ALL_L 31U 3054 #define XHC_FSCNOC__ALL_R 0U 3055 #define XHC_FSCNOC_DATAMASK 0xf07dffffU 3056 #define XHC_FSCNOC_RDWRMASK 0x0f820000U 3057 #define XHC_FSCNOC_RESETVALUE 0x00000000U 3058 3059 #define XHC_FSCAIC_OFFSET 0xc60U 3060 #define XHC_FSCAIC_BASE 0xc60U 3061 #define XHC_FSCAIC__FSIZ_L 22U 3062 #define XHC_FSCAIC__FSIZ_R 18U 3063 #define XHC_FSCAIC__FSIZ_WIDTH 5U 3064 #define XHC_FSCAIC__FSIZ_RESETVALUE 0x0U 3065 #define XHC_FSCAIC__PSIZ_L 16U 3066 #define XHC_FSCAIC__PSIZ_R 12U 3067 #define XHC_FSCAIC__PSIZ_WIDTH 5U 3068 #define XHC_FSCAIC__PSIZ_RESETVALUE 0x0U 3069 #define XHC_FSCAIC__reserved_L 11U 3070 #define XHC_FSCAIC__reserved_R 0U 3071 #define XHC_FSCAIC__reserved_WIDTH 12U 3072 #define XHC_FSCAIC__reserved_RESETVALUE 0x000U 3073 #define XHC_FSCAIC__RESERVED_L 31U 3074 #define XHC_FSCAIC__RESERVED_R 23U 3075 #define XHC_FSCAIC_WIDTH 23U 3076 #define XHC_FSCAIC__WIDTH 23U 3077 #define XHC_FSCAIC_ALL_L 22U 3078 #define XHC_FSCAIC_ALL_R 0U 3079 #define XHC_FSCAIC__ALL_L 22U 3080 #define XHC_FSCAIC__ALL_R 0U 3081 #define XHC_FSCAIC_DATAMASK 0x007dffffU 3082 #define XHC_FSCAIC_RDWRMASK 0xff820000U 3083 #define XHC_FSCAIC_RESETVALUE 0x000000U 3084 3085 #define XHC_FSCPIC_OFFSET 0xc64U 3086 #define XHC_FSCPIC_BASE 0xc64U 3087 #define XHC_FSCPIC__NCS_L 31U 3088 #define XHC_FSCPIC__NCS_R 28U 3089 #define XHC_FSCPIC__NCS_WIDTH 4U 3090 #define XHC_FSCPIC__NCS_RESETVALUE 0x0U 3091 #define XHC_FSCPIC__reserved_L 27U 3092 #define XHC_FSCPIC__reserved_R 5U 3093 #define XHC_FSCPIC__reserved_WIDTH 23U 3094 #define XHC_FSCPIC__reserved_RESETVALUE 0x0U 3095 #define XHC_FSCPIC__TSIZ_L 4U 3096 #define XHC_FSCPIC__TSIZ_R 0U 3097 #define XHC_FSCPIC__TSIZ_WIDTH 5U 3098 #define XHC_FSCPIC__TSIZ_RESETVALUE 0x0U 3099 #define XHC_FSCPIC_WIDTH 32U 3100 #define XHC_FSCPIC__WIDTH 32U 3101 #define XHC_FSCPIC_ALL_L 31U 3102 #define XHC_FSCPIC_ALL_R 0U 3103 #define XHC_FSCPIC__ALL_L 31U 3104 #define XHC_FSCPIC__ALL_R 0U 3105 #define XHC_FSCPIC_DATAMASK 0xffffffffU 3106 #define XHC_FSCPIC_RDWRMASK 0x00000000U 3107 #define XHC_FSCPIC_RESETVALUE 0x00000000U 3108 3109 #define XHC_FSCGIC_OFFSET 0xc68U 3110 #define XHC_FSCGIC_BASE 0xc68U 3111 #define XHC_FSCGIC__NCS_L 31U 3112 #define XHC_FSCGIC__NCS_R 28U 3113 #define XHC_FSCGIC__NCS_WIDTH 4U 3114 #define XHC_FSCGIC__NCS_RESETVALUE 0x0U 3115 #define XHC_FSCGIC__reserved_L 27U 3116 #define XHC_FSCGIC__reserved_R 5U 3117 #define XHC_FSCGIC__reserved_WIDTH 23U 3118 #define XHC_FSCGIC__reserved_RESETVALUE 0x0U 3119 #define XHC_FSCGIC__TSIZ_L 4U 3120 #define XHC_FSCGIC__TSIZ_R 0U 3121 #define XHC_FSCGIC__TSIZ_WIDTH 5U 3122 #define XHC_FSCGIC__TSIZ_RESETVALUE 0x0U 3123 #define XHC_FSCGIC_WIDTH 32U 3124 #define XHC_FSCGIC__WIDTH 32U 3125 #define XHC_FSCGIC_ALL_L 31U 3126 #define XHC_FSCGIC_ALL_R 0U 3127 #define XHC_FSCGIC__ALL_L 31U 3128 #define XHC_FSCGIC__ALL_R 0U 3129 #define XHC_FSCGIC_DATAMASK 0xffffffffU 3130 #define XHC_FSCGIC_RDWRMASK 0x00000000U 3131 #define XHC_FSCGIC_RESETVALUE 0x00000000U 3132 3133 #define XHC_FSCNIC_OFFSET 0xc6cU 3134 #define XHC_FSCNIC_BASE 0xc6cU 3135 #define XHC_FSCNIC__NCS_L 31U 3136 #define XHC_FSCNIC__NCS_R 28U 3137 #define XHC_FSCNIC__NCS_WIDTH 4U 3138 #define XHC_FSCNIC__NCS_RESETVALUE 0x0U 3139 #define XHC_FSCNIC__reserved_L 27U 3140 #define XHC_FSCNIC__reserved_R 5U 3141 #define XHC_FSCNIC__reserved_WIDTH 23U 3142 #define XHC_FSCNIC__reserved_RESETVALUE 0x0U 3143 #define XHC_FSCNIC__TSIZ_L 4U 3144 #define XHC_FSCNIC__TSIZ_R 0U 3145 #define XHC_FSCNIC__TSIZ_WIDTH 5U 3146 #define XHC_FSCNIC__TSIZ_RESETVALUE 0x0U 3147 #define XHC_FSCNIC_WIDTH 32U 3148 #define XHC_FSCNIC__WIDTH 32U 3149 #define XHC_FSCNIC_ALL_L 31U 3150 #define XHC_FSCNIC_ALL_R 0U 3151 #define XHC_FSCNIC__ALL_L 31U 3152 #define XHC_FSCNIC__ALL_R 0U 3153 #define XHC_FSCNIC_DATAMASK 0xffffffffU 3154 #define XHC_FSCNIC_RDWRMASK 0x00000000U 3155 #define XHC_FSCNIC_RESETVALUE 0x00000000U 3156 3157 #define XHC_ECHPRT_OFFSET 0xc70U 3158 #define XHC_ECHPRT_BASE 0xc70U 3159 #define XHC_ECHPRT__TDP 31U 3160 #define XHC_ECHPRT__TDP_L 31U 3161 #define XHC_ECHPRT__TDP_R 31U 3162 #define XHC_ECHPRT__TDP_WIDTH 1U 3163 #define XHC_ECHPRT__TDP_RESETVALUE 0x0U 3164 #define XHC_ECHPRT__RDP 30U 3165 #define XHC_ECHPRT__RDP_L 30U 3166 #define XHC_ECHPRT__RDP_R 30U 3167 #define XHC_ECHPRT__RDP_WIDTH 1U 3168 #define XHC_ECHPRT__RDP_RESETVALUE 0x0U 3169 #define XHC_ECHPRT__reserved_L 29U 3170 #define XHC_ECHPRT__reserved_R 25U 3171 #define XHC_ECHPRT__reserved_WIDTH 5U 3172 #define XHC_ECHPRT__reserved_RESETVALUE 0x0U 3173 #define XHC_ECHPRT__MFT_L 24U 3174 #define XHC_ECHPRT__MFT_R 17U 3175 #define XHC_ECHPRT__MFT_WIDTH 8U 3176 #define XHC_ECHPRT__MFT_RESETVALUE 0x7dU 3177 #define XHC_ECHPRT__HST 16U 3178 #define XHC_ECHPRT__HST_L 16U 3179 #define XHC_ECHPRT__HST_R 16U 3180 #define XHC_ECHPRT__HST_WIDTH 1U 3181 #define XHC_ECHPRT__HST_RESETVALUE 0x0U 3182 #define XHC_ECHPRT__NCP_L 15U 3183 #define XHC_ECHPRT__NCP_R 8U 3184 #define XHC_ECHPRT__NCP_WIDTH 8U 3185 #define XHC_ECHPRT__NCP_RESETVALUE 0x04U 3186 #define XHC_ECHPRT__CID_L 7U 3187 #define XHC_ECHPRT__CID_R 0U 3188 #define XHC_ECHPRT__CID_WIDTH 8U 3189 #define XHC_ECHPRT__CID_RESETVALUE 0xc4U 3190 #define XHC_ECHPRT_WIDTH 32U 3191 #define XHC_ECHPRT__WIDTH 32U 3192 #define XHC_ECHPRT_ALL_L 31U 3193 #define XHC_ECHPRT_ALL_R 0U 3194 #define XHC_ECHPRT__ALL_L 31U 3195 #define XHC_ECHPRT__ALL_R 0U 3196 #define XHC_ECHPRT_DATAMASK 0xffffffffU 3197 #define XHC_ECHPRT_RDWRMASK 0x00000000U 3198 #define XHC_ECHPRT_RESETVALUE 0x00fa04c4U 3199 3200 #define XHC_PRTHSC_OFFSET 0xc78U 3201 #define XHC_PRTHSC_BASE 0xc78U 3202 #define XHC_PRTHSC__TMR_L 31U 3203 #define XHC_PRTHSC__TMR_R 16U 3204 #define XHC_PRTHSC__TMR_WIDTH 16U 3205 #define XHC_PRTHSC__TMR_RESETVALUE 0x0000U 3206 #define XHC_PRTHSC__RSL_L 7U 3207 #define XHC_PRTHSC__RSL_R 6U 3208 #define XHC_PRTHSC__RSL_WIDTH 2U 3209 #define XHC_PRTHSC__RSL_RESETVALUE 0x0U 3210 #define XHC_PRTHSC__AS_M_L 5U 3211 #define XHC_PRTHSC__AS_M_R 4U 3212 #define XHC_PRTHSC__AS_M_WIDTH 2U 3213 #define XHC_PRTHSC__AS_M_RESETVALUE 0x0U 3214 #define XHC_PRTHSC__CMD_L 3U 3215 #define XHC_PRTHSC__CMD_R 2U 3216 #define XHC_PRTHSC__CMD_WIDTH 2U 3217 #define XHC_PRTHSC__CMD_RESETVALUE 0x0U 3218 #define XHC_PRTHSC__reserved 1U 3219 #define XHC_PRTHSC__reserved_L 1U 3220 #define XHC_PRTHSC__reserved_R 1U 3221 #define XHC_PRTHSC__reserved_WIDTH 1U 3222 #define XHC_PRTHSC__reserved_RESETVALUE 0x0U 3223 #define XHC_PRTHSC__STB 0U 3224 #define XHC_PRTHSC__STB_L 0U 3225 #define XHC_PRTHSC__STB_R 0U 3226 #define XHC_PRTHSC__STB_WIDTH 1U 3227 #define XHC_PRTHSC__STB_RESETVALUE 0x0U 3228 #define XHC_PRTHSC__RESERVED_L 15U 3229 #define XHC_PRTHSC__RESERVED_R 8U 3230 #define XHC_PRTHSC_WIDTH 32U 3231 #define XHC_PRTHSC__WIDTH 32U 3232 #define XHC_PRTHSC_ALL_L 31U 3233 #define XHC_PRTHSC_ALL_R 0U 3234 #define XHC_PRTHSC__ALL_L 31U 3235 #define XHC_PRTHSC__ALL_R 0U 3236 #define XHC_PRTHSC_DATAMASK 0xffff00ffU 3237 #define XHC_PRTHSC_RDWRMASK 0x0000ff00U 3238 #define XHC_PRTHSC_RESETVALUE 0x00000000U 3239 3240 #define XHC_PRTHSR_OFFSET 0xc7cU 3241 #define XHC_PRTHSR_BASE 0xc7cU 3242 #define XHC_PRTHSR__RDLY_L 31U 3243 #define XHC_PRTHSR__RDLY_R 24U 3244 #define XHC_PRTHSR__RDLY_WIDTH 8U 3245 #define XHC_PRTHSR__RDLY_RESETVALUE 0x00U 3246 #define XHC_PRTHSR__TDPP_L 23U 3247 #define XHC_PRTHSR__TDPP_R 16U 3248 #define XHC_PRTHSR__TDPP_WIDTH 8U 3249 #define XHC_PRTHSR__TDPP_RESETVALUE 0x00U 3250 #define XHC_PRTHSR__RDPP_L 15U 3251 #define XHC_PRTHSR__RDPP_R 8U 3252 #define XHC_PRTHSR__RDPP_WIDTH 8U 3253 #define XHC_PRTHSR__RDPP_RESETVALUE 0x00U 3254 #define XHC_PRTHSR__TRTY_L 7U 3255 #define XHC_PRTHSR__TRTY_R 0U 3256 #define XHC_PRTHSR__TRTY_WIDTH 8U 3257 #define XHC_PRTHSR__TRTY_RESETVALUE 0x00U 3258 #define XHC_PRTHSR_WIDTH 32U 3259 #define XHC_PRTHSR__WIDTH 32U 3260 #define XHC_PRTHSR_ALL_L 31U 3261 #define XHC_PRTHSR_ALL_R 0U 3262 #define XHC_PRTHSR__ALL_L 31U 3263 #define XHC_PRTHSR__ALL_R 0U 3264 #define XHC_PRTHSR_DATAMASK 0xffffffffU 3265 #define XHC_PRTHSR_RDWRMASK 0x00000000U 3266 #define XHC_PRTHSR_RESETVALUE 0x00000000U 3267 3268 #define XHC_ECHRHS_OFFSET 0xc80U 3269 #define XHC_ECHRHS_BASE 0xc80U 3270 #define XHC_ECHRHS__RPO_L 30U 3271 #define XHC_ECHRHS__RPO_R 24U 3272 #define XHC_ECHRHS__RPO_WIDTH 7U 3273 #define XHC_ECHRHS__RPO_RESETVALUE 0x0U 3274 #define XHC_ECHRHS__reserved_L 23U 3275 #define XHC_ECHRHS__reserved_R 22U 3276 #define XHC_ECHRHS__reserved_WIDTH 2U 3277 #define XHC_ECHRHS__reserved_RESETVALUE 0x0U 3278 #define XHC_ECHRHS__RPN_L 21U 3279 #define XHC_ECHRHS__RPN_R 20U 3280 #define XHC_ECHRHS__RPN_WIDTH 2U 3281 #define XHC_ECHRHS__RPN_RESETVALUE 0x0U 3282 #define XHC_ECHRHS__DNR_L 19U 3283 #define XHC_ECHRHS__DNR_R 16U 3284 #define XHC_ECHRHS__DNR_WIDTH 4U 3285 #define XHC_ECHRHS__DNR_RESETVALUE 0x0U 3286 #define XHC_ECHRHS__NCP_L 15U 3287 #define XHC_ECHRHS__NCP_R 8U 3288 #define XHC_ECHRHS__NCP_WIDTH 8U 3289 #define XHC_ECHRHS__NCP_RESETVALUE 0x0cU 3290 #define XHC_ECHRHS__CID_L 7U 3291 #define XHC_ECHRHS__CID_R 0U 3292 #define XHC_ECHRHS__CID_WIDTH 8U 3293 #define XHC_ECHRHS__CID_RESETVALUE 0xc8U 3294 #define XHC_ECHRHS__RESERVED 31U 3295 #define XHC_ECHRHS__RESERVED_L 31U 3296 #define XHC_ECHRHS__RESERVED_R 31U 3297 #define XHC_ECHRHS_WIDTH 31U 3298 #define XHC_ECHRHS__WIDTH 31U 3299 #define XHC_ECHRHS_ALL_L 30U 3300 #define XHC_ECHRHS_ALL_R 0U 3301 #define XHC_ECHRHS__ALL_L 30U 3302 #define XHC_ECHRHS__ALL_R 0U 3303 #define XHC_ECHRHS_DATAMASK 0x7fffffffU 3304 #define XHC_ECHRHS_RDWRMASK 0x80000000U 3305 #define XHC_ECHRHS_RESETVALUE 0x00000cc8U 3306 3307 #define XHC_RHSDES_OFFSET 0xc84U 3308 #define XHC_RHSDES_BASE 0xc84U 3309 #define XHC_RHSDES__PIS3_L 31U 3310 #define XHC_RHSDES__PIS3_R 30U 3311 #define XHC_RHSDES__PIS3_WIDTH 2U 3312 #define XHC_RHSDES__PIS3_RESETVALUE 0x0U 3313 #define XHC_RHSDES__HIST3 24U 3314 #define XHC_RHSDES__HIST3_L 24U 3315 #define XHC_RHSDES__HIST3_R 24U 3316 #define XHC_RHSDES__HIST3_WIDTH 1U 3317 #define XHC_RHSDES__HIST3_RESETVALUE 0x0U 3318 #define XHC_RHSDES__PIS2_L 23U 3319 #define XHC_RHSDES__PIS2_R 22U 3320 #define XHC_RHSDES__PIS2_WIDTH 2U 3321 #define XHC_RHSDES__PIS2_RESETVALUE 0x0U 3322 #define XHC_RHSDES__HIST2 16U 3323 #define XHC_RHSDES__HIST2_L 16U 3324 #define XHC_RHSDES__HIST2_R 16U 3325 #define XHC_RHSDES__HIST2_WIDTH 1U 3326 #define XHC_RHSDES__HIST2_RESETVALUE 0x0U 3327 #define XHC_RHSDES__PIS1_L 15U 3328 #define XHC_RHSDES__PIS1_R 14U 3329 #define XHC_RHSDES__PIS1_WIDTH 2U 3330 #define XHC_RHSDES__PIS1_RESETVALUE 0x0U 3331 #define XHC_RHSDES__HIST1 8U 3332 #define XHC_RHSDES__HIST1_L 8U 3333 #define XHC_RHSDES__HIST1_R 8U 3334 #define XHC_RHSDES__HIST1_WIDTH 1U 3335 #define XHC_RHSDES__HIST1_RESETVALUE 0x0U 3336 #define XHC_RHSDES__PIS0_L 7U 3337 #define XHC_RHSDES__PIS0_R 6U 3338 #define XHC_RHSDES__PIS0_WIDTH 2U 3339 #define XHC_RHSDES__PIS0_RESETVALUE 0x0U 3340 #define XHC_RHSDES__reserved_L 5U 3341 #define XHC_RHSDES__reserved_R 1U 3342 #define XHC_RHSDES__reserved_WIDTH 5U 3343 #define XHC_RHSDES__reserved_RESETVALUE 0x0U 3344 #define XHC_RHSDES__HIST0 0U 3345 #define XHC_RHSDES__HIST0_L 0U 3346 #define XHC_RHSDES__HIST0_R 0U 3347 #define XHC_RHSDES__HIST0_WIDTH 1U 3348 #define XHC_RHSDES__HIST0_RESETVALUE 0x0U 3349 #define XHC_RHSDES__RESERVED_0_L 29U 3350 #define XHC_RHSDES__RESERVED_0_R 25U 3351 #define XHC_RHSDES__RESERVED_1_L 21U 3352 #define XHC_RHSDES__RESERVED_1_R 17U 3353 #define XHC_RHSDES__RESERVED_2_L 13U 3354 #define XHC_RHSDES__RESERVED_2_R 9U 3355 #define XHC_RHSDES__RESERVED_L 29U 3356 #define XHC_RHSDES__RESERVED_R 25U 3357 #define XHC_RHSDES_WIDTH 32U 3358 #define XHC_RHSDES__WIDTH 32U 3359 #define XHC_RHSDES_ALL_L 31U 3360 #define XHC_RHSDES_ALL_R 0U 3361 #define XHC_RHSDES__ALL_L 31U 3362 #define XHC_RHSDES__ALL_R 0U 3363 #define XHC_RHSDES_DATAMASK 0xc1c1c1ffU 3364 #define XHC_RHSDES_RDWRMASK 0x3e3e3e00U 3365 #define XHC_RHSDES_RESETVALUE 0x00000000U 3366 3367 #define XHC_RHSHSC0_OFFSET 0xc90U 3368 #define XHC_RHSHSC0_BASE 0xc90U 3369 #define XHC_RHSHSC0__TMR_L 31U 3370 #define XHC_RHSHSC0__TMR_R 16U 3371 #define XHC_RHSHSC0__TMR_WIDTH 16U 3372 #define XHC_RHSHSC0__TMR_RESETVALUE 0x0000U 3373 #define XHC_RHSHSC0__RSL_L 7U 3374 #define XHC_RHSHSC0__RSL_R 6U 3375 #define XHC_RHSHSC0__RSL_WIDTH 2U 3376 #define XHC_RHSHSC0__RSL_RESETVALUE 0x0U 3377 #define XHC_RHSHSC0__AS_M_L 5U 3378 #define XHC_RHSHSC0__AS_M_R 4U 3379 #define XHC_RHSHSC0__AS_M_WIDTH 2U 3380 #define XHC_RHSHSC0__AS_M_RESETVALUE 0x0U 3381 #define XHC_RHSHSC0__CMD_L 3U 3382 #define XHC_RHSHSC0__CMD_R 2U 3383 #define XHC_RHSHSC0__CMD_WIDTH 2U 3384 #define XHC_RHSHSC0__CMD_RESETVALUE 0x0U 3385 #define XHC_RHSHSC0__reserved 1U 3386 #define XHC_RHSHSC0__reserved_L 1U 3387 #define XHC_RHSHSC0__reserved_R 1U 3388 #define XHC_RHSHSC0__reserved_WIDTH 1U 3389 #define XHC_RHSHSC0__reserved_RESETVALUE 0x0U 3390 #define XHC_RHSHSC0__STB 0U 3391 #define XHC_RHSHSC0__STB_L 0U 3392 #define XHC_RHSHSC0__STB_R 0U 3393 #define XHC_RHSHSC0__STB_WIDTH 1U 3394 #define XHC_RHSHSC0__STB_RESETVALUE 0x0U 3395 #define XHC_RHSHSC0__RESERVED_L 15U 3396 #define XHC_RHSHSC0__RESERVED_R 8U 3397 #define XHC_RHSHSC0_WIDTH 32U 3398 #define XHC_RHSHSC0__WIDTH 32U 3399 #define XHC_RHSHSC0_ALL_L 31U 3400 #define XHC_RHSHSC0_ALL_R 0U 3401 #define XHC_RHSHSC0__ALL_L 31U 3402 #define XHC_RHSHSC0__ALL_R 0U 3403 #define XHC_RHSHSC0_DATAMASK 0xffff00ffU 3404 #define XHC_RHSHSC0_RDWRMASK 0x0000ff00U 3405 #define XHC_RHSHSC0_RESETVALUE 0x00000000U 3406 3407 #define XHC_RHSHSR0_OFFSET 0xc94U 3408 #define XHC_RHSHSR0_BASE 0xc94U 3409 #define XHC_RHSHSR0__C2U_L 31U 3410 #define XHC_RHSHSR0__C2U_R 24U 3411 #define XHC_RHSHSR0__C2U_WIDTH 8U 3412 #define XHC_RHSHSR0__C2U_RESETVALUE 0x00U 3413 #define XHC_RHSHSR0__C1U_L 23U 3414 #define XHC_RHSHSR0__C1U_R 16U 3415 #define XHC_RHSHSR0__C1U_WIDTH 8U 3416 #define XHC_RHSHSR0__C1U_RESETVALUE 0x00U 3417 #define XHC_RHSHSR0__RCV_L 15U 3418 #define XHC_RHSHSR0__RCV_R 8U 3419 #define XHC_RHSHSR0__RCV_WIDTH 8U 3420 #define XHC_RHSHSR0__RCV_RESETVALUE 0x00U 3421 #define XHC_RHSHSR0__RTY_L 7U 3422 #define XHC_RHSHSR0__RTY_R 0U 3423 #define XHC_RHSHSR0__RTY_WIDTH 8U 3424 #define XHC_RHSHSR0__RTY_RESETVALUE 0x00U 3425 #define XHC_RHSHSR0_WIDTH 32U 3426 #define XHC_RHSHSR0__WIDTH 32U 3427 #define XHC_RHSHSR0_ALL_L 31U 3428 #define XHC_RHSHSR0_ALL_R 0U 3429 #define XHC_RHSHSR0__ALL_L 31U 3430 #define XHC_RHSHSR0__ALL_R 0U 3431 #define XHC_RHSHSR0_DATAMASK 0xffffffffU 3432 #define XHC_RHSHSR0_RDWRMASK 0x00000000U 3433 #define XHC_RHSHSR0_RESETVALUE 0x00000000U 3434 3435 #define XHC_RHSHSC1_OFFSET 0xc98U 3436 #define XHC_RHSHSC1_BASE 0xc98U 3437 #define XHC_RHSHSC1__TMR_L 31U 3438 #define XHC_RHSHSC1__TMR_R 16U 3439 #define XHC_RHSHSC1__TMR_WIDTH 16U 3440 #define XHC_RHSHSC1__TMR_RESETVALUE 0x0000U 3441 #define XHC_RHSHSC1__RSL_L 7U 3442 #define XHC_RHSHSC1__RSL_R 6U 3443 #define XHC_RHSHSC1__RSL_WIDTH 2U 3444 #define XHC_RHSHSC1__RSL_RESETVALUE 0x0U 3445 #define XHC_RHSHSC1__AS_M_L 5U 3446 #define XHC_RHSHSC1__AS_M_R 4U 3447 #define XHC_RHSHSC1__AS_M_WIDTH 2U 3448 #define XHC_RHSHSC1__AS_M_RESETVALUE 0x0U 3449 #define XHC_RHSHSC1__CMD_L 3U 3450 #define XHC_RHSHSC1__CMD_R 2U 3451 #define XHC_RHSHSC1__CMD_WIDTH 2U 3452 #define XHC_RHSHSC1__CMD_RESETVALUE 0x0U 3453 #define XHC_RHSHSC1__reserved 1U 3454 #define XHC_RHSHSC1__reserved_L 1U 3455 #define XHC_RHSHSC1__reserved_R 1U 3456 #define XHC_RHSHSC1__reserved_WIDTH 1U 3457 #define XHC_RHSHSC1__reserved_RESETVALUE 0x0U 3458 #define XHC_RHSHSC1__STB 0U 3459 #define XHC_RHSHSC1__STB_L 0U 3460 #define XHC_RHSHSC1__STB_R 0U 3461 #define XHC_RHSHSC1__STB_WIDTH 1U 3462 #define XHC_RHSHSC1__STB_RESETVALUE 0x0U 3463 #define XHC_RHSHSC1__RESERVED_L 15U 3464 #define XHC_RHSHSC1__RESERVED_R 8U 3465 #define XHC_RHSHSC1_WIDTH 32U 3466 #define XHC_RHSHSC1__WIDTH 32U 3467 #define XHC_RHSHSC1_ALL_L 31U 3468 #define XHC_RHSHSC1_ALL_R 0U 3469 #define XHC_RHSHSC1__ALL_L 31U 3470 #define XHC_RHSHSC1__ALL_R 0U 3471 #define XHC_RHSHSC1_DATAMASK 0xffff00ffU 3472 #define XHC_RHSHSC1_RDWRMASK 0x0000ff00U 3473 #define XHC_RHSHSC1_RESETVALUE 0x00000000U 3474 3475 #define XHC_RHSHSR1_OFFSET 0xc9cU 3476 #define XHC_RHSHSR1_BASE 0xc9cU 3477 #define XHC_RHSHSR1__C2U_L 31U 3478 #define XHC_RHSHSR1__C2U_R 24U 3479 #define XHC_RHSHSR1__C2U_WIDTH 8U 3480 #define XHC_RHSHSR1__C2U_RESETVALUE 0x00U 3481 #define XHC_RHSHSR1__C1U_L 23U 3482 #define XHC_RHSHSR1__C1U_R 16U 3483 #define XHC_RHSHSR1__C1U_WIDTH 8U 3484 #define XHC_RHSHSR1__C1U_RESETVALUE 0x00U 3485 #define XHC_RHSHSR1__RCV_L 15U 3486 #define XHC_RHSHSR1__RCV_R 8U 3487 #define XHC_RHSHSR1__RCV_WIDTH 8U 3488 #define XHC_RHSHSR1__RCV_RESETVALUE 0x00U 3489 #define XHC_RHSHSR1__RTY_L 7U 3490 #define XHC_RHSHSR1__RTY_R 0U 3491 #define XHC_RHSHSR1__RTY_WIDTH 8U 3492 #define XHC_RHSHSR1__RTY_RESETVALUE 0x00U 3493 #define XHC_RHSHSR1_WIDTH 32U 3494 #define XHC_RHSHSR1__WIDTH 32U 3495 #define XHC_RHSHSR1_ALL_L 31U 3496 #define XHC_RHSHSR1_ALL_R 0U 3497 #define XHC_RHSHSR1__ALL_L 31U 3498 #define XHC_RHSHSR1__ALL_R 0U 3499 #define XHC_RHSHSR1_DATAMASK 0xffffffffU 3500 #define XHC_RHSHSR1_RDWRMASK 0x00000000U 3501 #define XHC_RHSHSR1_RESETVALUE 0x00000000U 3502 3503 #define XHC_RHSHSC2_OFFSET 0xca0U 3504 #define XHC_RHSHSC2_BASE 0xca0U 3505 #define XHC_RHSHSC2__TMR_L 31U 3506 #define XHC_RHSHSC2__TMR_R 16U 3507 #define XHC_RHSHSC2__TMR_WIDTH 16U 3508 #define XHC_RHSHSC2__TMR_RESETVALUE 0x0000U 3509 #define XHC_RHSHSC2__RSL_L 7U 3510 #define XHC_RHSHSC2__RSL_R 6U 3511 #define XHC_RHSHSC2__RSL_WIDTH 2U 3512 #define XHC_RHSHSC2__RSL_RESETVALUE 0x0U 3513 #define XHC_RHSHSC2__AS_M_L 5U 3514 #define XHC_RHSHSC2__AS_M_R 4U 3515 #define XHC_RHSHSC2__AS_M_WIDTH 2U 3516 #define XHC_RHSHSC2__AS_M_RESETVALUE 0x0U 3517 #define XHC_RHSHSC2__CMD_L 3U 3518 #define XHC_RHSHSC2__CMD_R 2U 3519 #define XHC_RHSHSC2__CMD_WIDTH 2U 3520 #define XHC_RHSHSC2__CMD_RESETVALUE 0x0U 3521 #define XHC_RHSHSC2__reserved 1U 3522 #define XHC_RHSHSC2__reserved_L 1U 3523 #define XHC_RHSHSC2__reserved_R 1U 3524 #define XHC_RHSHSC2__reserved_WIDTH 1U 3525 #define XHC_RHSHSC2__reserved_RESETVALUE 0x0U 3526 #define XHC_RHSHSC2__STB 0U 3527 #define XHC_RHSHSC2__STB_L 0U 3528 #define XHC_RHSHSC2__STB_R 0U 3529 #define XHC_RHSHSC2__STB_WIDTH 1U 3530 #define XHC_RHSHSC2__STB_RESETVALUE 0x0U 3531 #define XHC_RHSHSC2__RESERVED_L 15U 3532 #define XHC_RHSHSC2__RESERVED_R 8U 3533 #define XHC_RHSHSC2_WIDTH 32U 3534 #define XHC_RHSHSC2__WIDTH 32U 3535 #define XHC_RHSHSC2_ALL_L 31U 3536 #define XHC_RHSHSC2_ALL_R 0U 3537 #define XHC_RHSHSC2__ALL_L 31U 3538 #define XHC_RHSHSC2__ALL_R 0U 3539 #define XHC_RHSHSC2_DATAMASK 0xffff00ffU 3540 #define XHC_RHSHSC2_RDWRMASK 0x0000ff00U 3541 #define XHC_RHSHSC2_RESETVALUE 0x00000000U 3542 3543 #define XHC_RHSHSR2_OFFSET 0xca4U 3544 #define XHC_RHSHSR2_BASE 0xca4U 3545 #define XHC_RHSHSR2__C2U_L 31U 3546 #define XHC_RHSHSR2__C2U_R 24U 3547 #define XHC_RHSHSR2__C2U_WIDTH 8U 3548 #define XHC_RHSHSR2__C2U_RESETVALUE 0x00U 3549 #define XHC_RHSHSR2__C1U_L 23U 3550 #define XHC_RHSHSR2__C1U_R 16U 3551 #define XHC_RHSHSR2__C1U_WIDTH 8U 3552 #define XHC_RHSHSR2__C1U_RESETVALUE 0x00U 3553 #define XHC_RHSHSR2__RCV_L 15U 3554 #define XHC_RHSHSR2__RCV_R 8U 3555 #define XHC_RHSHSR2__RCV_WIDTH 8U 3556 #define XHC_RHSHSR2__RCV_RESETVALUE 0x00U 3557 #define XHC_RHSHSR2__RTY_L 7U 3558 #define XHC_RHSHSR2__RTY_R 0U 3559 #define XHC_RHSHSR2__RTY_WIDTH 8U 3560 #define XHC_RHSHSR2__RTY_RESETVALUE 0x00U 3561 #define XHC_RHSHSR2_WIDTH 32U 3562 #define XHC_RHSHSR2__WIDTH 32U 3563 #define XHC_RHSHSR2_ALL_L 31U 3564 #define XHC_RHSHSR2_ALL_R 0U 3565 #define XHC_RHSHSR2__ALL_L 31U 3566 #define XHC_RHSHSR2__ALL_R 0U 3567 #define XHC_RHSHSR2_DATAMASK 0xffffffffU 3568 #define XHC_RHSHSR2_RDWRMASK 0x00000000U 3569 #define XHC_RHSHSR2_RESETVALUE 0x00000000U 3570 3571 #define XHC_RHSHSC3_OFFSET 0xca8U 3572 #define XHC_RHSHSC3_BASE 0xca8U 3573 #define XHC_RHSHSC3__TMR_L 31U 3574 #define XHC_RHSHSC3__TMR_R 16U 3575 #define XHC_RHSHSC3__TMR_WIDTH 16U 3576 #define XHC_RHSHSC3__TMR_RESETVALUE 0x0000U 3577 #define XHC_RHSHSC3__RSL_L 7U 3578 #define XHC_RHSHSC3__RSL_R 6U 3579 #define XHC_RHSHSC3__RSL_WIDTH 2U 3580 #define XHC_RHSHSC3__RSL_RESETVALUE 0x0U 3581 #define XHC_RHSHSC3__AS_M_L 5U 3582 #define XHC_RHSHSC3__AS_M_R 4U 3583 #define XHC_RHSHSC3__AS_M_WIDTH 2U 3584 #define XHC_RHSHSC3__AS_M_RESETVALUE 0x0U 3585 #define XHC_RHSHSC3__CMD_L 3U 3586 #define XHC_RHSHSC3__CMD_R 2U 3587 #define XHC_RHSHSC3__CMD_WIDTH 2U 3588 #define XHC_RHSHSC3__CMD_RESETVALUE 0x0U 3589 #define XHC_RHSHSC3__reserved 1U 3590 #define XHC_RHSHSC3__reserved_L 1U 3591 #define XHC_RHSHSC3__reserved_R 1U 3592 #define XHC_RHSHSC3__reserved_WIDTH 1U 3593 #define XHC_RHSHSC3__reserved_RESETVALUE 0x0U 3594 #define XHC_RHSHSC3__STB 0U 3595 #define XHC_RHSHSC3__STB_L 0U 3596 #define XHC_RHSHSC3__STB_R 0U 3597 #define XHC_RHSHSC3__STB_WIDTH 1U 3598 #define XHC_RHSHSC3__STB_RESETVALUE 0x0U 3599 #define XHC_RHSHSC3__RESERVED_L 15U 3600 #define XHC_RHSHSC3__RESERVED_R 8U 3601 #define XHC_RHSHSC3_WIDTH 32U 3602 #define XHC_RHSHSC3__WIDTH 32U 3603 #define XHC_RHSHSC3_ALL_L 31U 3604 #define XHC_RHSHSC3_ALL_R 0U 3605 #define XHC_RHSHSC3__ALL_L 31U 3606 #define XHC_RHSHSC3__ALL_R 0U 3607 #define XHC_RHSHSC3_DATAMASK 0xffff00ffU 3608 #define XHC_RHSHSC3_RDWRMASK 0x0000ff00U 3609 #define XHC_RHSHSC3_RESETVALUE 0x00000000U 3610 3611 #define XHC_RHSHSR3_OFFSET 0xcacU 3612 #define XHC_RHSHSR3_BASE 0xcacU 3613 #define XHC_RHSHSR3__C2U_L 31U 3614 #define XHC_RHSHSR3__C2U_R 24U 3615 #define XHC_RHSHSR3__C2U_WIDTH 8U 3616 #define XHC_RHSHSR3__C2U_RESETVALUE 0x00U 3617 #define XHC_RHSHSR3__C1U_L 23U 3618 #define XHC_RHSHSR3__C1U_R 16U 3619 #define XHC_RHSHSR3__C1U_WIDTH 8U 3620 #define XHC_RHSHSR3__C1U_RESETVALUE 0x00U 3621 #define XHC_RHSHSR3__RCV_L 15U 3622 #define XHC_RHSHSR3__RCV_R 8U 3623 #define XHC_RHSHSR3__RCV_WIDTH 8U 3624 #define XHC_RHSHSR3__RCV_RESETVALUE 0x00U 3625 #define XHC_RHSHSR3__RTY_L 7U 3626 #define XHC_RHSHSR3__RTY_R 0U 3627 #define XHC_RHSHSR3__RTY_WIDTH 8U 3628 #define XHC_RHSHSR3__RTY_RESETVALUE 0x00U 3629 #define XHC_RHSHSR3_WIDTH 32U 3630 #define XHC_RHSHSR3__WIDTH 32U 3631 #define XHC_RHSHSR3_ALL_L 31U 3632 #define XHC_RHSHSR3_ALL_R 0U 3633 #define XHC_RHSHSR3__ALL_L 31U 3634 #define XHC_RHSHSR3__ALL_R 0U 3635 #define XHC_RHSHSR3_DATAMASK 0xffffffffU 3636 #define XHC_RHSHSR3_RDWRMASK 0x00000000U 3637 #define XHC_RHSHSR3_RESETVALUE 0x00000000U 3638 3639 #define XHC_ECHSSP_OFFSET 0xcb0U 3640 #define XHC_ECHSSP_BASE 0xcb0U 3641 #define XHC_ECHSSP__reserved_L 31U 3642 #define XHC_ECHSSP__reserved_R 16U 3643 #define XHC_ECHSSP__reserved_WIDTH 16U 3644 #define XHC_ECHSSP__reserved_RESETVALUE 0x0000U 3645 #define XHC_ECHSSP__NCP_L 15U 3646 #define XHC_ECHSSP__NCP_R 8U 3647 #define XHC_ECHSSP__NCP_WIDTH 8U 3648 #define XHC_ECHSSP__NCP_RESETVALUE 0x04U 3649 #define XHC_ECHSSP__CID_L 7U 3650 #define XHC_ECHSSP__CID_R 0U 3651 #define XHC_ECHSSP__CID_WIDTH 8U 3652 #define XHC_ECHSSP__CID_RESETVALUE 0xc6U 3653 #define XHC_ECHSSP_WIDTH 32U 3654 #define XHC_ECHSSP__WIDTH 32U 3655 #define XHC_ECHSSP_ALL_L 31U 3656 #define XHC_ECHSSP_ALL_R 0U 3657 #define XHC_ECHSSP__ALL_L 31U 3658 #define XHC_ECHSSP__ALL_R 0U 3659 #define XHC_ECHSSP_DATAMASK 0xffffffffU 3660 #define XHC_ECHSSP_RDWRMASK 0x00000000U 3661 #define XHC_ECHSSP_RESETVALUE 0x000004c6U 3662 3663 #define XHC_SSPVER_OFFSET 0xcb4U 3664 #define XHC_SSPVER_BASE 0xcb4U 3665 #define XHC_SSPVER__MAJ_L 31U 3666 #define XHC_SSPVER__MAJ_R 28U 3667 #define XHC_SSPVER__MAJ_WIDTH 4U 3668 #define XHC_SSPVER__MAJ_RESETVALUE 0x0U 3669 #define XHC_SSPVER__MIN_L 27U 3670 #define XHC_SSPVER__MIN_R 24U 3671 #define XHC_SSPVER__MIN_WIDTH 4U 3672 #define XHC_SSPVER__MIN_RESETVALUE 0x0U 3673 #define XHC_SSPVER__RLS_L 23U 3674 #define XHC_SSPVER__RLS_R 20U 3675 #define XHC_SSPVER__RLS_WIDTH 4U 3676 #define XHC_SSPVER__RLS_RESETVALUE 0x0U 3677 #define XHC_SSPVER__reserved_L 19U 3678 #define XHC_SSPVER__reserved_R 0U 3679 #define XHC_SSPVER__reserved_WIDTH 20U 3680 #define XHC_SSPVER__reserved_RESETVALUE 0x00000U 3681 #define XHC_SSPVER_WIDTH 32U 3682 #define XHC_SSPVER__WIDTH 32U 3683 #define XHC_SSPVER_ALL_L 31U 3684 #define XHC_SSPVER_ALL_R 0U 3685 #define XHC_SSPVER__ALL_L 31U 3686 #define XHC_SSPVER__ALL_R 0U 3687 #define XHC_SSPVER_DATAMASK 0xffffffffU 3688 #define XHC_SSPVER_RDWRMASK 0x00000000U 3689 #define XHC_SSPVER_RESETVALUE 0x00000000U 3690 3691 #define XHC_SSPMGN_OFFSET 0xcb8U 3692 #define XHC_SSPMGN_BASE 0xcb8U 3693 #define XHC_SSPMGN__MGN_L 31U 3694 #define XHC_SSPMGN__MGN_R 0U 3695 #define XHC_SSPMGN__MGN_WIDTH 32U 3696 #define XHC_SSPMGN__MGN_RESETVALUE 0x4b535040U 3697 #define XHC_SSPMGN_WIDTH 32U 3698 #define XHC_SSPMGN__WIDTH 32U 3699 #define XHC_SSPMGN_ALL_L 31U 3700 #define XHC_SSPMGN_ALL_R 0U 3701 #define XHC_SSPMGN__ALL_L 31U 3702 #define XHC_SSPMGN__ALL_R 0U 3703 #define XHC_SSPMGN_DATAMASK 0xffffffffU 3704 #define XHC_SSPMGN_RDWRMASK 0x00000000U 3705 #define XHC_SSPMGN_RESETVALUE 0x4b535040U 3706 3707 #define XHC_ECHFSC2_OFFSET 0xcc0U 3708 #define XHC_ECHFSC2_BASE 0xcc0U 3709 #define XHC_ECHFSC2__reserved_L 31U 3710 #define XHC_ECHFSC2__reserved_R 16U 3711 #define XHC_ECHFSC2__reserved_WIDTH 16U 3712 #define XHC_ECHFSC2__reserved_RESETVALUE 0x0000U 3713 #define XHC_ECHFSC2__NCP_L 15U 3714 #define XHC_ECHFSC2__NCP_R 8U 3715 #define XHC_ECHFSC2__NCP_WIDTH 8U 3716 #define XHC_ECHFSC2__NCP_RESETVALUE 0x50U 3717 #define XHC_ECHFSC2__CID_L 7U 3718 #define XHC_ECHFSC2__CID_R 0U 3719 #define XHC_ECHFSC2__CID_WIDTH 8U 3720 #define XHC_ECHFSC2__CID_RESETVALUE 0xc7U 3721 #define XHC_ECHFSC2_WIDTH 32U 3722 #define XHC_ECHFSC2__WIDTH 32U 3723 #define XHC_ECHFSC2_ALL_L 31U 3724 #define XHC_ECHFSC2_ALL_R 0U 3725 #define XHC_ECHFSC2__ALL_L 31U 3726 #define XHC_ECHFSC2__ALL_R 0U 3727 #define XHC_ECHFSC2_DATAMASK 0xffffffffU 3728 #define XHC_ECHFSC2_RDWRMASK 0x00000000U 3729 #define XHC_ECHFSC2_RESETVALUE 0x000050c7U 3730 3731 #define XHC_FSC2POC_OFFSET 0xcd4U 3732 #define XHC_FSC2POC_BASE 0xcd4U 3733 #define XHC_FSC2POC__NCS_L 31U 3734 #define XHC_FSC2POC__NCS_R 28U 3735 #define XHC_FSC2POC__NCS_WIDTH 4U 3736 #define XHC_FSC2POC__NCS_RESETVALUE 0x0U 3737 #define XHC_FSC2POC__FSIZ_L 22U 3738 #define XHC_FSC2POC__FSIZ_R 18U 3739 #define XHC_FSC2POC__FSIZ_WIDTH 5U 3740 #define XHC_FSC2POC__FSIZ_RESETVALUE 0x0U 3741 #define XHC_FSC2POC__PSIZ_L 16U 3742 #define XHC_FSC2POC__PSIZ_R 12U 3743 #define XHC_FSC2POC__PSIZ_WIDTH 5U 3744 #define XHC_FSC2POC__PSIZ_RESETVALUE 0x0U 3745 #define XHC_FSC2POC__reserved_L 11U 3746 #define XHC_FSC2POC__reserved_R 5U 3747 #define XHC_FSC2POC__reserved_WIDTH 7U 3748 #define XHC_FSC2POC__reserved_RESETVALUE 0x0U 3749 #define XHC_FSC2POC__TSIZ_L 4U 3750 #define XHC_FSC2POC__TSIZ_R 0U 3751 #define XHC_FSC2POC__TSIZ_WIDTH 5U 3752 #define XHC_FSC2POC__TSIZ_RESETVALUE 0x0U 3753 #define XHC_FSC2POC__RESERVED_L 27U 3754 #define XHC_FSC2POC__RESERVED_R 23U 3755 #define XHC_FSC2POC_WIDTH 32U 3756 #define XHC_FSC2POC__WIDTH 32U 3757 #define XHC_FSC2POC_ALL_L 31U 3758 #define XHC_FSC2POC_ALL_R 0U 3759 #define XHC_FSC2POC__ALL_L 31U 3760 #define XHC_FSC2POC__ALL_R 0U 3761 #define XHC_FSC2POC_DATAMASK 0xf07dffffU 3762 #define XHC_FSC2POC_RDWRMASK 0x0f820000U 3763 #define XHC_FSC2POC_RESETVALUE 0x00000000U 3764 3765 #define XHC_FSC2GOC_OFFSET 0xcd8U 3766 #define XHC_FSC2GOC_BASE 0xcd8U 3767 #define XHC_FSC2GOC__NCS_L 31U 3768 #define XHC_FSC2GOC__NCS_R 28U 3769 #define XHC_FSC2GOC__NCS_WIDTH 4U 3770 #define XHC_FSC2GOC__NCS_RESETVALUE 0x0U 3771 #define XHC_FSC2GOC__FSIZ_L 22U 3772 #define XHC_FSC2GOC__FSIZ_R 18U 3773 #define XHC_FSC2GOC__FSIZ_WIDTH 5U 3774 #define XHC_FSC2GOC__FSIZ_RESETVALUE 0x0U 3775 #define XHC_FSC2GOC__PSIZ_L 16U 3776 #define XHC_FSC2GOC__PSIZ_R 12U 3777 #define XHC_FSC2GOC__PSIZ_WIDTH 5U 3778 #define XHC_FSC2GOC__PSIZ_RESETVALUE 0x0U 3779 #define XHC_FSC2GOC__reserved_L 11U 3780 #define XHC_FSC2GOC__reserved_R 5U 3781 #define XHC_FSC2GOC__reserved_WIDTH 7U 3782 #define XHC_FSC2GOC__reserved_RESETVALUE 0x0U 3783 #define XHC_FSC2GOC__TSIZ_L 4U 3784 #define XHC_FSC2GOC__TSIZ_R 0U 3785 #define XHC_FSC2GOC__TSIZ_WIDTH 5U 3786 #define XHC_FSC2GOC__TSIZ_RESETVALUE 0x0U 3787 #define XHC_FSC2GOC__RESERVED_L 27U 3788 #define XHC_FSC2GOC__RESERVED_R 23U 3789 #define XHC_FSC2GOC_WIDTH 32U 3790 #define XHC_FSC2GOC__WIDTH 32U 3791 #define XHC_FSC2GOC_ALL_L 31U 3792 #define XHC_FSC2GOC_ALL_R 0U 3793 #define XHC_FSC2GOC__ALL_L 31U 3794 #define XHC_FSC2GOC__ALL_R 0U 3795 #define XHC_FSC2GOC_DATAMASK 0xf07dffffU 3796 #define XHC_FSC2GOC_RDWRMASK 0x0f820000U 3797 #define XHC_FSC2GOC_RESETVALUE 0x00000000U 3798 3799 #define XHC_FSC2NOC_OFFSET 0xcdcU 3800 #define XHC_FSC2NOC_BASE 0xcdcU 3801 #define XHC_FSC2NOC__NCS_L 31U 3802 #define XHC_FSC2NOC__NCS_R 28U 3803 #define XHC_FSC2NOC__NCS_WIDTH 4U 3804 #define XHC_FSC2NOC__NCS_RESETVALUE 0x0U 3805 #define XHC_FSC2NOC__FSIZ_L 22U 3806 #define XHC_FSC2NOC__FSIZ_R 18U 3807 #define XHC_FSC2NOC__FSIZ_WIDTH 5U 3808 #define XHC_FSC2NOC__FSIZ_RESETVALUE 0x0U 3809 #define XHC_FSC2NOC__PSIZ_L 16U 3810 #define XHC_FSC2NOC__PSIZ_R 12U 3811 #define XHC_FSC2NOC__PSIZ_WIDTH 5U 3812 #define XHC_FSC2NOC__PSIZ_RESETVALUE 0x0U 3813 #define XHC_FSC2NOC__reserved_L 11U 3814 #define XHC_FSC2NOC__reserved_R 5U 3815 #define XHC_FSC2NOC__reserved_WIDTH 7U 3816 #define XHC_FSC2NOC__reserved_RESETVALUE 0x0U 3817 #define XHC_FSC2NOC__TSIZ_L 4U 3818 #define XHC_FSC2NOC__TSIZ_R 0U 3819 #define XHC_FSC2NOC__TSIZ_WIDTH 5U 3820 #define XHC_FSC2NOC__TSIZ_RESETVALUE 0x0U 3821 #define XHC_FSC2NOC__RESERVED_L 27U 3822 #define XHC_FSC2NOC__RESERVED_R 23U 3823 #define XHC_FSC2NOC_WIDTH 32U 3824 #define XHC_FSC2NOC__WIDTH 32U 3825 #define XHC_FSC2NOC_ALL_L 31U 3826 #define XHC_FSC2NOC_ALL_R 0U 3827 #define XHC_FSC2NOC__ALL_L 31U 3828 #define XHC_FSC2NOC__ALL_R 0U 3829 #define XHC_FSC2NOC_DATAMASK 0xf07dffffU 3830 #define XHC_FSC2NOC_RDWRMASK 0x0f820000U 3831 #define XHC_FSC2NOC_RESETVALUE 0x00000000U 3832 3833 #define XHC_FSC2AIC_OFFSET 0xce0U 3834 #define XHC_FSC2AIC_BASE 0xce0U 3835 #define XHC_FSC2AIC__FSIZ_L 22U 3836 #define XHC_FSC2AIC__FSIZ_R 18U 3837 #define XHC_FSC2AIC__FSIZ_WIDTH 5U 3838 #define XHC_FSC2AIC__FSIZ_RESETVALUE 0x0U 3839 #define XHC_FSC2AIC__PSIZ_L 16U 3840 #define XHC_FSC2AIC__PSIZ_R 12U 3841 #define XHC_FSC2AIC__PSIZ_WIDTH 5U 3842 #define XHC_FSC2AIC__PSIZ_RESETVALUE 0x0U 3843 #define XHC_FSC2AIC__reserved_L 11U 3844 #define XHC_FSC2AIC__reserved_R 0U 3845 #define XHC_FSC2AIC__reserved_WIDTH 12U 3846 #define XHC_FSC2AIC__reserved_RESETVALUE 0x000U 3847 #define XHC_FSC2AIC__RESERVED_L 31U 3848 #define XHC_FSC2AIC__RESERVED_R 23U 3849 #define XHC_FSC2AIC_WIDTH 23U 3850 #define XHC_FSC2AIC__WIDTH 23U 3851 #define XHC_FSC2AIC_ALL_L 22U 3852 #define XHC_FSC2AIC_ALL_R 0U 3853 #define XHC_FSC2AIC__ALL_L 22U 3854 #define XHC_FSC2AIC__ALL_R 0U 3855 #define XHC_FSC2AIC_DATAMASK 0x007dffffU 3856 #define XHC_FSC2AIC_RDWRMASK 0xff820000U 3857 #define XHC_FSC2AIC_RESETVALUE 0x000000U 3858 3859 #define XHC_FSC2PIC_OFFSET 0xce4U 3860 #define XHC_FSC2PIC_BASE 0xce4U 3861 #define XHC_FSC2PIC__NCS_L 31U 3862 #define XHC_FSC2PIC__NCS_R 28U 3863 #define XHC_FSC2PIC__NCS_WIDTH 4U 3864 #define XHC_FSC2PIC__NCS_RESETVALUE 0x0U 3865 #define XHC_FSC2PIC__reserved_L 27U 3866 #define XHC_FSC2PIC__reserved_R 5U 3867 #define XHC_FSC2PIC__reserved_WIDTH 23U 3868 #define XHC_FSC2PIC__reserved_RESETVALUE 0x0U 3869 #define XHC_FSC2PIC__TSIZ_L 4U 3870 #define XHC_FSC2PIC__TSIZ_R 0U 3871 #define XHC_FSC2PIC__TSIZ_WIDTH 5U 3872 #define XHC_FSC2PIC__TSIZ_RESETVALUE 0x0U 3873 #define XHC_FSC2PIC_WIDTH 32U 3874 #define XHC_FSC2PIC__WIDTH 32U 3875 #define XHC_FSC2PIC_ALL_L 31U 3876 #define XHC_FSC2PIC_ALL_R 0U 3877 #define XHC_FSC2PIC__ALL_L 31U 3878 #define XHC_FSC2PIC__ALL_R 0U 3879 #define XHC_FSC2PIC_DATAMASK 0xffffffffU 3880 #define XHC_FSC2PIC_RDWRMASK 0x00000000U 3881 #define XHC_FSC2PIC_RESETVALUE 0x00000000U 3882 3883 #define XHC_FSC2GIC_OFFSET 0xce8U 3884 #define XHC_FSC2GIC_BASE 0xce8U 3885 #define XHC_FSC2GIC__NCS_L 31U 3886 #define XHC_FSC2GIC__NCS_R 28U 3887 #define XHC_FSC2GIC__NCS_WIDTH 4U 3888 #define XHC_FSC2GIC__NCS_RESETVALUE 0x0U 3889 #define XHC_FSC2GIC__reserved_L 27U 3890 #define XHC_FSC2GIC__reserved_R 5U 3891 #define XHC_FSC2GIC__reserved_WIDTH 23U 3892 #define XHC_FSC2GIC__reserved_RESETVALUE 0x0U 3893 #define XHC_FSC2GIC__TSIZ_L 4U 3894 #define XHC_FSC2GIC__TSIZ_R 0U 3895 #define XHC_FSC2GIC__TSIZ_WIDTH 5U 3896 #define XHC_FSC2GIC__TSIZ_RESETVALUE 0x0U 3897 #define XHC_FSC2GIC_WIDTH 32U 3898 #define XHC_FSC2GIC__WIDTH 32U 3899 #define XHC_FSC2GIC_ALL_L 31U 3900 #define XHC_FSC2GIC_ALL_R 0U 3901 #define XHC_FSC2GIC__ALL_L 31U 3902 #define XHC_FSC2GIC__ALL_R 0U 3903 #define XHC_FSC2GIC_DATAMASK 0xffffffffU 3904 #define XHC_FSC2GIC_RDWRMASK 0x00000000U 3905 #define XHC_FSC2GIC_RESETVALUE 0x00000000U 3906 3907 #define XHC_FSC2NIC_OFFSET 0xcecU 3908 #define XHC_FSC2NIC_BASE 0xcecU 3909 #define XHC_FSC2NIC__NCS_L 31U 3910 #define XHC_FSC2NIC__NCS_R 28U 3911 #define XHC_FSC2NIC__NCS_WIDTH 4U 3912 #define XHC_FSC2NIC__NCS_RESETVALUE 0x0U 3913 #define XHC_FSC2NIC__reserved_L 27U 3914 #define XHC_FSC2NIC__reserved_R 5U 3915 #define XHC_FSC2NIC__reserved_WIDTH 23U 3916 #define XHC_FSC2NIC__reserved_RESETVALUE 0x0U 3917 #define XHC_FSC2NIC__TSIZ_L 4U 3918 #define XHC_FSC2NIC__TSIZ_R 0U 3919 #define XHC_FSC2NIC__TSIZ_WIDTH 5U 3920 #define XHC_FSC2NIC__TSIZ_RESETVALUE 0x0U 3921 #define XHC_FSC2NIC_WIDTH 32U 3922 #define XHC_FSC2NIC__WIDTH 32U 3923 #define XHC_FSC2NIC_ALL_L 31U 3924 #define XHC_FSC2NIC_ALL_R 0U 3925 #define XHC_FSC2NIC__ALL_L 31U 3926 #define XHC_FSC2NIC__ALL_R 0U 3927 #define XHC_FSC2NIC_DATAMASK 0xffffffffU 3928 #define XHC_FSC2NIC_RDWRMASK 0x00000000U 3929 #define XHC_FSC2NIC_RESETVALUE 0x00000000U 3930 3931 #define XHC_ECHPRT2_OFFSET 0xcf0U 3932 #define XHC_ECHPRT2_BASE 0xcf0U 3933 #define XHC_ECHPRT2__HDP 31U 3934 #define XHC_ECHPRT2__HDP_L 31U 3935 #define XHC_ECHPRT2__HDP_R 31U 3936 #define XHC_ECHPRT2__HDP_WIDTH 1U 3937 #define XHC_ECHPRT2__HDP_RESETVALUE 0x0U 3938 #define XHC_ECHPRT2__FDP 30U 3939 #define XHC_ECHPRT2__FDP_L 30U 3940 #define XHC_ECHPRT2__FDP_R 30U 3941 #define XHC_ECHPRT2__FDP_WIDTH 1U 3942 #define XHC_ECHPRT2__FDP_RESETVALUE 0x0U 3943 #define XHC_ECHPRT2__reserved_L 29U 3944 #define XHC_ECHPRT2__reserved_R 17U 3945 #define XHC_ECHPRT2__reserved_WIDTH 13U 3946 #define XHC_ECHPRT2__reserved_RESETVALUE 0x0U 3947 #define XHC_ECHPRT2__HST 16U 3948 #define XHC_ECHPRT2__HST_L 16U 3949 #define XHC_ECHPRT2__HST_R 16U 3950 #define XHC_ECHPRT2__HST_WIDTH 1U 3951 #define XHC_ECHPRT2__HST_RESETVALUE 0x0U 3952 #define XHC_ECHPRT2__NCP_L 15U 3953 #define XHC_ECHPRT2__NCP_R 8U 3954 #define XHC_ECHPRT2__NCP_WIDTH 8U 3955 #define XHC_ECHPRT2__NCP_RESETVALUE 0x04U 3956 #define XHC_ECHPRT2__CID_L 7U 3957 #define XHC_ECHPRT2__CID_R 0U 3958 #define XHC_ECHPRT2__CID_WIDTH 8U 3959 #define XHC_ECHPRT2__CID_RESETVALUE 0xc8U 3960 #define XHC_ECHPRT2_WIDTH 32U 3961 #define XHC_ECHPRT2__WIDTH 32U 3962 #define XHC_ECHPRT2_ALL_L 31U 3963 #define XHC_ECHPRT2_ALL_R 0U 3964 #define XHC_ECHPRT2__ALL_L 31U 3965 #define XHC_ECHPRT2__ALL_R 0U 3966 #define XHC_ECHPRT2_DATAMASK 0xffffffffU 3967 #define XHC_ECHPRT2_RDWRMASK 0x00000000U 3968 #define XHC_ECHPRT2_RESETVALUE 0x000004c8U 3969 3970 #define XHC_PRT2HSC_OFFSET 0xcf8U 3971 #define XHC_PRT2HSC_BASE 0xcf8U 3972 #define XHC_PRT2HSC__TMR_L 31U 3973 #define XHC_PRT2HSC__TMR_R 16U 3974 #define XHC_PRT2HSC__TMR_WIDTH 16U 3975 #define XHC_PRT2HSC__TMR_RESETVALUE 0x0000U 3976 #define XHC_PRT2HSC__RSL_L 7U 3977 #define XHC_PRT2HSC__RSL_R 6U 3978 #define XHC_PRT2HSC__RSL_WIDTH 2U 3979 #define XHC_PRT2HSC__RSL_RESETVALUE 0x0U 3980 #define XHC_PRT2HSC__AS_M_L 5U 3981 #define XHC_PRT2HSC__AS_M_R 4U 3982 #define XHC_PRT2HSC__AS_M_WIDTH 2U 3983 #define XHC_PRT2HSC__AS_M_RESETVALUE 0x0U 3984 #define XHC_PRT2HSC__CMD_L 3U 3985 #define XHC_PRT2HSC__CMD_R 2U 3986 #define XHC_PRT2HSC__CMD_WIDTH 2U 3987 #define XHC_PRT2HSC__CMD_RESETVALUE 0x0U 3988 #define XHC_PRT2HSC__reserved 1U 3989 #define XHC_PRT2HSC__reserved_L 1U 3990 #define XHC_PRT2HSC__reserved_R 1U 3991 #define XHC_PRT2HSC__reserved_WIDTH 1U 3992 #define XHC_PRT2HSC__reserved_RESETVALUE 0x0U 3993 #define XHC_PRT2HSC__STB 0U 3994 #define XHC_PRT2HSC__STB_L 0U 3995 #define XHC_PRT2HSC__STB_R 0U 3996 #define XHC_PRT2HSC__STB_WIDTH 1U 3997 #define XHC_PRT2HSC__STB_RESETVALUE 0x0U 3998 #define XHC_PRT2HSC__RESERVED_L 15U 3999 #define XHC_PRT2HSC__RESERVED_R 8U 4000 #define XHC_PRT2HSC_WIDTH 32U 4001 #define XHC_PRT2HSC__WIDTH 32U 4002 #define XHC_PRT2HSC_ALL_L 31U 4003 #define XHC_PRT2HSC_ALL_R 0U 4004 #define XHC_PRT2HSC__ALL_L 31U 4005 #define XHC_PRT2HSC__ALL_R 0U 4006 #define XHC_PRT2HSC_DATAMASK 0xffff00ffU 4007 #define XHC_PRT2HSC_RDWRMASK 0x0000ff00U 4008 #define XHC_PRT2HSC_RESETVALUE 0x00000000U 4009 4010 #define XHC_PRT2HSR_OFFSET 0xcfcU 4011 #define XHC_PRT2HSR_BASE 0xcfcU 4012 #define XHC_PRT2HSR__RNAK_L 31U 4013 #define XHC_PRT2HSR__RNAK_R 24U 4014 #define XHC_PRT2HSR__RNAK_WIDTH 8U 4015 #define XHC_PRT2HSR__RNAK_RESETVALUE 0x00U 4016 #define XHC_PRT2HSR__HSTX_L 23U 4017 #define XHC_PRT2HSR__HSTX_R 16U 4018 #define XHC_PRT2HSR__HSTX_WIDTH 8U 4019 #define XHC_PRT2HSR__HSTX_RESETVALUE 0x00U 4020 #define XHC_PRT2HSR__HSRX_L 15U 4021 #define XHC_PRT2HSR__HSRX_R 8U 4022 #define XHC_PRT2HSR__HSRX_WIDTH 8U 4023 #define XHC_PRT2HSR__HSRX_RESETVALUE 0x00U 4024 #define XHC_PRT2HSR__SPLT_L 7U 4025 #define XHC_PRT2HSR__SPLT_R 0U 4026 #define XHC_PRT2HSR__SPLT_WIDTH 8U 4027 #define XHC_PRT2HSR__SPLT_RESETVALUE 0x00U 4028 #define XHC_PRT2HSR_WIDTH 32U 4029 #define XHC_PRT2HSR__WIDTH 32U 4030 #define XHC_PRT2HSR_ALL_L 31U 4031 #define XHC_PRT2HSR_ALL_R 0U 4032 #define XHC_PRT2HSR__ALL_L 31U 4033 #define XHC_PRT2HSR__ALL_R 0U 4034 #define XHC_PRT2HSR_DATAMASK 0xffffffffU 4035 #define XHC_PRT2HSR_RDWRMASK 0x00000000U 4036 #define XHC_PRT2HSR_RESETVALUE 0x00000000U 4037 4038 #define XHC_ECHRH2_OFFSET 0xd00U 4039 #define XHC_ECHRH2_BASE 0xd00U 4040 #define XHC_ECHRH2__MTT 31U 4041 #define XHC_ECHRH2__MTT_L 31U 4042 #define XHC_ECHRH2__MTT_R 31U 4043 #define XHC_ECHRH2__MTT_WIDTH 1U 4044 #define XHC_ECHRH2__MTT_RESETVALUE 0x0U 4045 #define XHC_ECHRH2__RPO_L 30U 4046 #define XHC_ECHRH2__RPO_R 24U 4047 #define XHC_ECHRH2__RPO_WIDTH 7U 4048 #define XHC_ECHRH2__RPO_RESETVALUE 0x0U 4049 #define XHC_ECHRH2__reserved_L 23U 4050 #define XHC_ECHRH2__reserved_R 22U 4051 #define XHC_ECHRH2__reserved_WIDTH 2U 4052 #define XHC_ECHRH2__reserved_RESETVALUE 0x0U 4053 #define XHC_ECHRH2__RPN_L 21U 4054 #define XHC_ECHRH2__RPN_R 20U 4055 #define XHC_ECHRH2__RPN_WIDTH 2U 4056 #define XHC_ECHRH2__RPN_RESETVALUE 0x0U 4057 #define XHC_ECHRH2__DNR_L 19U 4058 #define XHC_ECHRH2__DNR_R 16U 4059 #define XHC_ECHRH2__DNR_WIDTH 4U 4060 #define XHC_ECHRH2__DNR_RESETVALUE 0x0U 4061 #define XHC_ECHRH2__NCP_L 15U 4062 #define XHC_ECHRH2__NCP_R 8U 4063 #define XHC_ECHRH2__NCP_WIDTH 8U 4064 #define XHC_ECHRH2__NCP_RESETVALUE 0x0cU 4065 #define XHC_ECHRH2__CID_L 7U 4066 #define XHC_ECHRH2__CID_R 0U 4067 #define XHC_ECHRH2__CID_WIDTH 8U 4068 #define XHC_ECHRH2__CID_RESETVALUE 0xc9U 4069 #define XHC_ECHRH2_WIDTH 32U 4070 #define XHC_ECHRH2__WIDTH 32U 4071 #define XHC_ECHRH2_ALL_L 31U 4072 #define XHC_ECHRH2_ALL_R 0U 4073 #define XHC_ECHRH2__ALL_L 31U 4074 #define XHC_ECHRH2__ALL_R 0U 4075 #define XHC_ECHRH2_DATAMASK 0xffffffffU 4076 #define XHC_ECHRH2_RDWRMASK 0x00000000U 4077 #define XHC_ECHRH2_RESETVALUE 0x00000cc9U 4078 4079 #define XHC_RH2DES_OFFSET 0xd04U 4080 #define XHC_RH2DES_BASE 0xd04U 4081 #define XHC_RH2DES__PIS3_L 31U 4082 #define XHC_RH2DES__PIS3_R 30U 4083 #define XHC_RH2DES__PIS3_WIDTH 2U 4084 #define XHC_RH2DES__PIS3_RESETVALUE 0x0U 4085 #define XHC_RH2DES__HIST3 24U 4086 #define XHC_RH2DES__HIST3_L 24U 4087 #define XHC_RH2DES__HIST3_R 24U 4088 #define XHC_RH2DES__HIST3_WIDTH 1U 4089 #define XHC_RH2DES__HIST3_RESETVALUE 0x0U 4090 #define XHC_RH2DES__PIS2_L 23U 4091 #define XHC_RH2DES__PIS2_R 22U 4092 #define XHC_RH2DES__PIS2_WIDTH 2U 4093 #define XHC_RH2DES__PIS2_RESETVALUE 0x0U 4094 #define XHC_RH2DES__HIST2 16U 4095 #define XHC_RH2DES__HIST2_L 16U 4096 #define XHC_RH2DES__HIST2_R 16U 4097 #define XHC_RH2DES__HIST2_WIDTH 1U 4098 #define XHC_RH2DES__HIST2_RESETVALUE 0x0U 4099 #define XHC_RH2DES__PIS1_L 15U 4100 #define XHC_RH2DES__PIS1_R 14U 4101 #define XHC_RH2DES__PIS1_WIDTH 2U 4102 #define XHC_RH2DES__PIS1_RESETVALUE 0x0U 4103 #define XHC_RH2DES__HIST1 8U 4104 #define XHC_RH2DES__HIST1_L 8U 4105 #define XHC_RH2DES__HIST1_R 8U 4106 #define XHC_RH2DES__HIST1_WIDTH 1U 4107 #define XHC_RH2DES__HIST1_RESETVALUE 0x0U 4108 #define XHC_RH2DES__PIS0_L 7U 4109 #define XHC_RH2DES__PIS0_R 6U 4110 #define XHC_RH2DES__PIS0_WIDTH 2U 4111 #define XHC_RH2DES__PIS0_RESETVALUE 0x0U 4112 #define XHC_RH2DES__reserved_L 5U 4113 #define XHC_RH2DES__reserved_R 1U 4114 #define XHC_RH2DES__reserved_WIDTH 5U 4115 #define XHC_RH2DES__reserved_RESETVALUE 0x0U 4116 #define XHC_RH2DES__HIST0 0U 4117 #define XHC_RH2DES__HIST0_L 0U 4118 #define XHC_RH2DES__HIST0_R 0U 4119 #define XHC_RH2DES__HIST0_WIDTH 1U 4120 #define XHC_RH2DES__HIST0_RESETVALUE 0x0U 4121 #define XHC_RH2DES__RESERVED_0_L 29U 4122 #define XHC_RH2DES__RESERVED_0_R 25U 4123 #define XHC_RH2DES__RESERVED_1_L 21U 4124 #define XHC_RH2DES__RESERVED_1_R 17U 4125 #define XHC_RH2DES__RESERVED_2_L 13U 4126 #define XHC_RH2DES__RESERVED_2_R 9U 4127 #define XHC_RH2DES__RESERVED_L 29U 4128 #define XHC_RH2DES__RESERVED_R 25U 4129 #define XHC_RH2DES_WIDTH 32U 4130 #define XHC_RH2DES__WIDTH 32U 4131 #define XHC_RH2DES_ALL_L 31U 4132 #define XHC_RH2DES_ALL_R 0U 4133 #define XHC_RH2DES__ALL_L 31U 4134 #define XHC_RH2DES__ALL_R 0U 4135 #define XHC_RH2DES_DATAMASK 0xc1c1c1ffU 4136 #define XHC_RH2DES_RDWRMASK 0x3e3e3e00U 4137 #define XHC_RH2DES_RESETVALUE 0x00000000U 4138 4139 #define XHC_RH2HSC0_OFFSET 0xd10U 4140 #define XHC_RH2HSC0_BASE 0xd10U 4141 #define XHC_RH2HSC0__TMR_L 31U 4142 #define XHC_RH2HSC0__TMR_R 16U 4143 #define XHC_RH2HSC0__TMR_WIDTH 16U 4144 #define XHC_RH2HSC0__TMR_RESETVALUE 0x0000U 4145 #define XHC_RH2HSC0__RSL_L 7U 4146 #define XHC_RH2HSC0__RSL_R 6U 4147 #define XHC_RH2HSC0__RSL_WIDTH 2U 4148 #define XHC_RH2HSC0__RSL_RESETVALUE 0x0U 4149 #define XHC_RH2HSC0__AS_M_L 5U 4150 #define XHC_RH2HSC0__AS_M_R 4U 4151 #define XHC_RH2HSC0__AS_M_WIDTH 2U 4152 #define XHC_RH2HSC0__AS_M_RESETVALUE 0x0U 4153 #define XHC_RH2HSC0__CMD_L 3U 4154 #define XHC_RH2HSC0__CMD_R 2U 4155 #define XHC_RH2HSC0__CMD_WIDTH 2U 4156 #define XHC_RH2HSC0__CMD_RESETVALUE 0x0U 4157 #define XHC_RH2HSC0__reserved 1U 4158 #define XHC_RH2HSC0__reserved_L 1U 4159 #define XHC_RH2HSC0__reserved_R 1U 4160 #define XHC_RH2HSC0__reserved_WIDTH 1U 4161 #define XHC_RH2HSC0__reserved_RESETVALUE 0x0U 4162 #define XHC_RH2HSC0__STB 0U 4163 #define XHC_RH2HSC0__STB_L 0U 4164 #define XHC_RH2HSC0__STB_R 0U 4165 #define XHC_RH2HSC0__STB_WIDTH 1U 4166 #define XHC_RH2HSC0__STB_RESETVALUE 0x0U 4167 #define XHC_RH2HSC0__RESERVED_L 15U 4168 #define XHC_RH2HSC0__RESERVED_R 8U 4169 #define XHC_RH2HSC0_WIDTH 32U 4170 #define XHC_RH2HSC0__WIDTH 32U 4171 #define XHC_RH2HSC0_ALL_L 31U 4172 #define XHC_RH2HSC0_ALL_R 0U 4173 #define XHC_RH2HSC0__ALL_L 31U 4174 #define XHC_RH2HSC0__ALL_R 0U 4175 #define XHC_RH2HSC0_DATAMASK 0xffff00ffU 4176 #define XHC_RH2HSC0_RDWRMASK 0x0000ff00U 4177 #define XHC_RH2HSC0_RESETVALUE 0x00000000U 4178 4179 #define XHC_RH2HSR0_OFFSET 0xd14U 4180 #define XHC_RH2HSR0_BASE 0xd14U 4181 #define XHC_RH2HSR0__C2U_L 31U 4182 #define XHC_RH2HSR0__C2U_R 24U 4183 #define XHC_RH2HSR0__C2U_WIDTH 8U 4184 #define XHC_RH2HSR0__C2U_RESETVALUE 0x00U 4185 #define XHC_RH2HSR0__C1U_L 23U 4186 #define XHC_RH2HSR0__C1U_R 16U 4187 #define XHC_RH2HSR0__C1U_WIDTH 8U 4188 #define XHC_RH2HSR0__C1U_RESETVALUE 0x00U 4189 #define XHC_RH2HSR0__reserved_L 15U 4190 #define XHC_RH2HSR0__reserved_R 8U 4191 #define XHC_RH2HSR0__reserved_WIDTH 8U 4192 #define XHC_RH2HSR0__reserved_RESETVALUE 0x00U 4193 #define XHC_RH2HSR0__RTY_L 7U 4194 #define XHC_RH2HSR0__RTY_R 0U 4195 #define XHC_RH2HSR0__RTY_WIDTH 8U 4196 #define XHC_RH2HSR0__RTY_RESETVALUE 0x00U 4197 #define XHC_RH2HSR0_WIDTH 32U 4198 #define XHC_RH2HSR0__WIDTH 32U 4199 #define XHC_RH2HSR0_ALL_L 31U 4200 #define XHC_RH2HSR0_ALL_R 0U 4201 #define XHC_RH2HSR0__ALL_L 31U 4202 #define XHC_RH2HSR0__ALL_R 0U 4203 #define XHC_RH2HSR0_DATAMASK 0xffffffffU 4204 #define XHC_RH2HSR0_RDWRMASK 0x00000000U 4205 #define XHC_RH2HSR0_RESETVALUE 0x00000000U 4206 4207 #define XHC_RH2HSC1_OFFSET 0xd18U 4208 #define XHC_RH2HSC1_BASE 0xd18U 4209 #define XHC_RH2HSC1__TMR_L 31U 4210 #define XHC_RH2HSC1__TMR_R 16U 4211 #define XHC_RH2HSC1__TMR_WIDTH 16U 4212 #define XHC_RH2HSC1__TMR_RESETVALUE 0x0000U 4213 #define XHC_RH2HSC1__RSL_L 7U 4214 #define XHC_RH2HSC1__RSL_R 6U 4215 #define XHC_RH2HSC1__RSL_WIDTH 2U 4216 #define XHC_RH2HSC1__RSL_RESETVALUE 0x0U 4217 #define XHC_RH2HSC1__AS_M_L 5U 4218 #define XHC_RH2HSC1__AS_M_R 4U 4219 #define XHC_RH2HSC1__AS_M_WIDTH 2U 4220 #define XHC_RH2HSC1__AS_M_RESETVALUE 0x0U 4221 #define XHC_RH2HSC1__CMD_L 3U 4222 #define XHC_RH2HSC1__CMD_R 2U 4223 #define XHC_RH2HSC1__CMD_WIDTH 2U 4224 #define XHC_RH2HSC1__CMD_RESETVALUE 0x0U 4225 #define XHC_RH2HSC1__reserved 1U 4226 #define XHC_RH2HSC1__reserved_L 1U 4227 #define XHC_RH2HSC1__reserved_R 1U 4228 #define XHC_RH2HSC1__reserved_WIDTH 1U 4229 #define XHC_RH2HSC1__reserved_RESETVALUE 0x0U 4230 #define XHC_RH2HSC1__STB 0U 4231 #define XHC_RH2HSC1__STB_L 0U 4232 #define XHC_RH2HSC1__STB_R 0U 4233 #define XHC_RH2HSC1__STB_WIDTH 1U 4234 #define XHC_RH2HSC1__STB_RESETVALUE 0x0U 4235 #define XHC_RH2HSC1__RESERVED_L 15U 4236 #define XHC_RH2HSC1__RESERVED_R 8U 4237 #define XHC_RH2HSC1_WIDTH 32U 4238 #define XHC_RH2HSC1__WIDTH 32U 4239 #define XHC_RH2HSC1_ALL_L 31U 4240 #define XHC_RH2HSC1_ALL_R 0U 4241 #define XHC_RH2HSC1__ALL_L 31U 4242 #define XHC_RH2HSC1__ALL_R 0U 4243 #define XHC_RH2HSC1_DATAMASK 0xffff00ffU 4244 #define XHC_RH2HSC1_RDWRMASK 0x0000ff00U 4245 #define XHC_RH2HSC1_RESETVALUE 0x00000000U 4246 4247 #define XHC_RH2HSR1_OFFSET 0xd1cU 4248 #define XHC_RH2HSR1_BASE 0xd1cU 4249 #define XHC_RH2HSR1__C2U_L 31U 4250 #define XHC_RH2HSR1__C2U_R 24U 4251 #define XHC_RH2HSR1__C2U_WIDTH 8U 4252 #define XHC_RH2HSR1__C2U_RESETVALUE 0x00U 4253 #define XHC_RH2HSR1__C1U_L 23U 4254 #define XHC_RH2HSR1__C1U_R 16U 4255 #define XHC_RH2HSR1__C1U_WIDTH 8U 4256 #define XHC_RH2HSR1__C1U_RESETVALUE 0x00U 4257 #define XHC_RH2HSR1__reserved_L 15U 4258 #define XHC_RH2HSR1__reserved_R 8U 4259 #define XHC_RH2HSR1__reserved_WIDTH 8U 4260 #define XHC_RH2HSR1__reserved_RESETVALUE 0x00U 4261 #define XHC_RH2HSR1__RTY_L 7U 4262 #define XHC_RH2HSR1__RTY_R 0U 4263 #define XHC_RH2HSR1__RTY_WIDTH 8U 4264 #define XHC_RH2HSR1__RTY_RESETVALUE 0x00U 4265 #define XHC_RH2HSR1_WIDTH 32U 4266 #define XHC_RH2HSR1__WIDTH 32U 4267 #define XHC_RH2HSR1_ALL_L 31U 4268 #define XHC_RH2HSR1_ALL_R 0U 4269 #define XHC_RH2HSR1__ALL_L 31U 4270 #define XHC_RH2HSR1__ALL_R 0U 4271 #define XHC_RH2HSR1_DATAMASK 0xffffffffU 4272 #define XHC_RH2HSR1_RDWRMASK 0x00000000U 4273 #define XHC_RH2HSR1_RESETVALUE 0x00000000U 4274 4275 #define XHC_RH2HSC2_OFFSET 0xd20U 4276 #define XHC_RH2HSC2_BASE 0xd20U 4277 #define XHC_RH2HSC2__TMR_L 31U 4278 #define XHC_RH2HSC2__TMR_R 16U 4279 #define XHC_RH2HSC2__TMR_WIDTH 16U 4280 #define XHC_RH2HSC2__TMR_RESETVALUE 0x0000U 4281 #define XHC_RH2HSC2__RSL_L 7U 4282 #define XHC_RH2HSC2__RSL_R 6U 4283 #define XHC_RH2HSC2__RSL_WIDTH 2U 4284 #define XHC_RH2HSC2__RSL_RESETVALUE 0x0U 4285 #define XHC_RH2HSC2__AS_M_L 5U 4286 #define XHC_RH2HSC2__AS_M_R 4U 4287 #define XHC_RH2HSC2__AS_M_WIDTH 2U 4288 #define XHC_RH2HSC2__AS_M_RESETVALUE 0x0U 4289 #define XHC_RH2HSC2__CMD_L 3U 4290 #define XHC_RH2HSC2__CMD_R 2U 4291 #define XHC_RH2HSC2__CMD_WIDTH 2U 4292 #define XHC_RH2HSC2__CMD_RESETVALUE 0x0U 4293 #define XHC_RH2HSC2__reserved 1U 4294 #define XHC_RH2HSC2__reserved_L 1U 4295 #define XHC_RH2HSC2__reserved_R 1U 4296 #define XHC_RH2HSC2__reserved_WIDTH 1U 4297 #define XHC_RH2HSC2__reserved_RESETVALUE 0x0U 4298 #define XHC_RH2HSC2__STB 0U 4299 #define XHC_RH2HSC2__STB_L 0U 4300 #define XHC_RH2HSC2__STB_R 0U 4301 #define XHC_RH2HSC2__STB_WIDTH 1U 4302 #define XHC_RH2HSC2__STB_RESETVALUE 0x0U 4303 #define XHC_RH2HSC2__RESERVED_L 15U 4304 #define XHC_RH2HSC2__RESERVED_R 8U 4305 #define XHC_RH2HSC2_WIDTH 32U 4306 #define XHC_RH2HSC2__WIDTH 32U 4307 #define XHC_RH2HSC2_ALL_L 31U 4308 #define XHC_RH2HSC2_ALL_R 0U 4309 #define XHC_RH2HSC2__ALL_L 31U 4310 #define XHC_RH2HSC2__ALL_R 0U 4311 #define XHC_RH2HSC2_DATAMASK 0xffff00ffU 4312 #define XHC_RH2HSC2_RDWRMASK 0x0000ff00U 4313 #define XHC_RH2HSC2_RESETVALUE 0x00000000U 4314 4315 #define XHC_RH2HSR2_OFFSET 0xd24U 4316 #define XHC_RH2HSR2_BASE 0xd24U 4317 #define XHC_RH2HSR2__C2U_L 31U 4318 #define XHC_RH2HSR2__C2U_R 24U 4319 #define XHC_RH2HSR2__C2U_WIDTH 8U 4320 #define XHC_RH2HSR2__C2U_RESETVALUE 0x00U 4321 #define XHC_RH2HSR2__C1U_L 23U 4322 #define XHC_RH2HSR2__C1U_R 16U 4323 #define XHC_RH2HSR2__C1U_WIDTH 8U 4324 #define XHC_RH2HSR2__C1U_RESETVALUE 0x00U 4325 #define XHC_RH2HSR2__reserved_L 15U 4326 #define XHC_RH2HSR2__reserved_R 8U 4327 #define XHC_RH2HSR2__reserved_WIDTH 8U 4328 #define XHC_RH2HSR2__reserved_RESETVALUE 0x00U 4329 #define XHC_RH2HSR2__RTY_L 7U 4330 #define XHC_RH2HSR2__RTY_R 0U 4331 #define XHC_RH2HSR2__RTY_WIDTH 8U 4332 #define XHC_RH2HSR2__RTY_RESETVALUE 0x00U 4333 #define XHC_RH2HSR2_WIDTH 32U 4334 #define XHC_RH2HSR2__WIDTH 32U 4335 #define XHC_RH2HSR2_ALL_L 31U 4336 #define XHC_RH2HSR2_ALL_R 0U 4337 #define XHC_RH2HSR2__ALL_L 31U 4338 #define XHC_RH2HSR2__ALL_R 0U 4339 #define XHC_RH2HSR2_DATAMASK 0xffffffffU 4340 #define XHC_RH2HSR2_RDWRMASK 0x00000000U 4341 #define XHC_RH2HSR2_RESETVALUE 0x00000000U 4342 4343 #define XHC_RH2HSC3_OFFSET 0xd28U 4344 #define XHC_RH2HSC3_BASE 0xd28U 4345 #define XHC_RH2HSC3__TMR_L 31U 4346 #define XHC_RH2HSC3__TMR_R 16U 4347 #define XHC_RH2HSC3__TMR_WIDTH 16U 4348 #define XHC_RH2HSC3__TMR_RESETVALUE 0x0000U 4349 #define XHC_RH2HSC3__RSL_L 7U 4350 #define XHC_RH2HSC3__RSL_R 6U 4351 #define XHC_RH2HSC3__RSL_WIDTH 2U 4352 #define XHC_RH2HSC3__RSL_RESETVALUE 0x0U 4353 #define XHC_RH2HSC3__AS_M_L 5U 4354 #define XHC_RH2HSC3__AS_M_R 4U 4355 #define XHC_RH2HSC3__AS_M_WIDTH 2U 4356 #define XHC_RH2HSC3__AS_M_RESETVALUE 0x0U 4357 #define XHC_RH2HSC3__CMD_L 3U 4358 #define XHC_RH2HSC3__CMD_R 2U 4359 #define XHC_RH2HSC3__CMD_WIDTH 2U 4360 #define XHC_RH2HSC3__CMD_RESETVALUE 0x0U 4361 #define XHC_RH2HSC3__reserved 1U 4362 #define XHC_RH2HSC3__reserved_L 1U 4363 #define XHC_RH2HSC3__reserved_R 1U 4364 #define XHC_RH2HSC3__reserved_WIDTH 1U 4365 #define XHC_RH2HSC3__reserved_RESETVALUE 0x0U 4366 #define XHC_RH2HSC3__STB 0U 4367 #define XHC_RH2HSC3__STB_L 0U 4368 #define XHC_RH2HSC3__STB_R 0U 4369 #define XHC_RH2HSC3__STB_WIDTH 1U 4370 #define XHC_RH2HSC3__STB_RESETVALUE 0x0U 4371 #define XHC_RH2HSC3__RESERVED_L 15U 4372 #define XHC_RH2HSC3__RESERVED_R 8U 4373 #define XHC_RH2HSC3_WIDTH 32U 4374 #define XHC_RH2HSC3__WIDTH 32U 4375 #define XHC_RH2HSC3_ALL_L 31U 4376 #define XHC_RH2HSC3_ALL_R 0U 4377 #define XHC_RH2HSC3__ALL_L 31U 4378 #define XHC_RH2HSC3__ALL_R 0U 4379 #define XHC_RH2HSC3_DATAMASK 0xffff00ffU 4380 #define XHC_RH2HSC3_RDWRMASK 0x0000ff00U 4381 #define XHC_RH2HSC3_RESETVALUE 0x00000000U 4382 4383 #define XHC_RH2HSR3_OFFSET 0xd2cU 4384 #define XHC_RH2HSR3_BASE 0xd2cU 4385 #define XHC_RH2HSR3__C2U_L 31U 4386 #define XHC_RH2HSR3__C2U_R 24U 4387 #define XHC_RH2HSR3__C2U_WIDTH 8U 4388 #define XHC_RH2HSR3__C2U_RESETVALUE 0x00U 4389 #define XHC_RH2HSR3__C1U_L 23U 4390 #define XHC_RH2HSR3__C1U_R 16U 4391 #define XHC_RH2HSR3__C1U_WIDTH 8U 4392 #define XHC_RH2HSR3__C1U_RESETVALUE 0x00U 4393 #define XHC_RH2HSR3__reserved_L 15U 4394 #define XHC_RH2HSR3__reserved_R 8U 4395 #define XHC_RH2HSR3__reserved_WIDTH 8U 4396 #define XHC_RH2HSR3__reserved_RESETVALUE 0x00U 4397 #define XHC_RH2HSR3__RTY_L 7U 4398 #define XHC_RH2HSR3__RTY_R 0U 4399 #define XHC_RH2HSR3__RTY_WIDTH 8U 4400 #define XHC_RH2HSR3__RTY_RESETVALUE 0x00U 4401 #define XHC_RH2HSR3_WIDTH 32U 4402 #define XHC_RH2HSR3__WIDTH 32U 4403 #define XHC_RH2HSR3_ALL_L 31U 4404 #define XHC_RH2HSR3_ALL_R 0U 4405 #define XHC_RH2HSR3__ALL_L 31U 4406 #define XHC_RH2HSR3__ALL_R 0U 4407 #define XHC_RH2HSR3_DATAMASK 0xffffffffU 4408 #define XHC_RH2HSR3_RDWRMASK 0x00000000U 4409 #define XHC_RH2HSR3_RESETVALUE 0x00000000U 4410 4411 #define XHC_ECHU2P_OFFSET 0xd30U 4412 #define XHC_ECHU2P_BASE 0xd30U 4413 #define XHC_ECHU2P__reserved_L 31U 4414 #define XHC_ECHU2P__reserved_R 16U 4415 #define XHC_ECHU2P__reserved_WIDTH 16U 4416 #define XHC_ECHU2P__reserved_RESETVALUE 0x0000U 4417 #define XHC_ECHU2P__NCP_L 15U 4418 #define XHC_ECHU2P__NCP_R 8U 4419 #define XHC_ECHU2P__NCP_WIDTH 8U 4420 #define XHC_ECHU2P__NCP_RESETVALUE 0x04U 4421 #define XHC_ECHU2P__CID_L 7U 4422 #define XHC_ECHU2P__CID_R 0U 4423 #define XHC_ECHU2P__CID_WIDTH 8U 4424 #define XHC_ECHU2P__CID_RESETVALUE 0xcaU 4425 #define XHC_ECHU2P_WIDTH 32U 4426 #define XHC_ECHU2P__WIDTH 32U 4427 #define XHC_ECHU2P_ALL_L 31U 4428 #define XHC_ECHU2P_ALL_R 0U 4429 #define XHC_ECHU2P__ALL_L 31U 4430 #define XHC_ECHU2P__ALL_R 0U 4431 #define XHC_ECHU2P_DATAMASK 0xffffffffU 4432 #define XHC_ECHU2P_RDWRMASK 0x00000000U 4433 #define XHC_ECHU2P_RESETVALUE 0x000004caU 4434 4435 #define XHC_U2PVER_OFFSET 0xd34U 4436 #define XHC_U2PVER_BASE 0xd34U 4437 #define XHC_U2PVER__MAJ_L 31U 4438 #define XHC_U2PVER__MAJ_R 28U 4439 #define XHC_U2PVER__MAJ_WIDTH 4U 4440 #define XHC_U2PVER__MAJ_RESETVALUE 0x0U 4441 #define XHC_U2PVER__MIN_L 27U 4442 #define XHC_U2PVER__MIN_R 24U 4443 #define XHC_U2PVER__MIN_WIDTH 4U 4444 #define XHC_U2PVER__MIN_RESETVALUE 0x0U 4445 #define XHC_U2PVER__RLS_L 23U 4446 #define XHC_U2PVER__RLS_R 20U 4447 #define XHC_U2PVER__RLS_WIDTH 4U 4448 #define XHC_U2PVER__RLS_RESETVALUE 0x0U 4449 #define XHC_U2PVER__reserved_L 19U 4450 #define XHC_U2PVER__reserved_R 0U 4451 #define XHC_U2PVER__reserved_WIDTH 20U 4452 #define XHC_U2PVER__reserved_RESETVALUE 0x00000U 4453 #define XHC_U2PVER_WIDTH 32U 4454 #define XHC_U2PVER__WIDTH 32U 4455 #define XHC_U2PVER_ALL_L 31U 4456 #define XHC_U2PVER_ALL_R 0U 4457 #define XHC_U2PVER__ALL_L 31U 4458 #define XHC_U2PVER__ALL_R 0U 4459 #define XHC_U2PVER_DATAMASK 0xffffffffU 4460 #define XHC_U2PVER_RDWRMASK 0x00000000U 4461 #define XHC_U2PVER_RESETVALUE 0x00000000U 4462 4463 #define XHC_U2PMGN_OFFSET 0xd38U 4464 #define XHC_U2PMGN_BASE 0xd38U 4465 #define XHC_U2PMGN__MGN_L 31U 4466 #define XHC_U2PMGN__MGN_R 0U 4467 #define XHC_U2PMGN__MGN_WIDTH 32U 4468 #define XHC_U2PMGN__MGN_RESETVALUE 0x4b534b4dU 4469 #define XHC_U2PMGN_WIDTH 32U 4470 #define XHC_U2PMGN__WIDTH 32U 4471 #define XHC_U2PMGN_ALL_L 31U 4472 #define XHC_U2PMGN_ALL_R 0U 4473 #define XHC_U2PMGN__ALL_L 31U 4474 #define XHC_U2PMGN__ALL_R 0U 4475 #define XHC_U2PMGN_DATAMASK 0xffffffffU 4476 #define XHC_U2PMGN_RDWRMASK 0x00000000U 4477 #define XHC_U2PMGN_RESETVALUE 0x4b534b4dU 4478 4479 #define XHC_ECHRSV2_OFFSET 0xd40U 4480 #define XHC_ECHRSV2_BASE 0xd40U 4481 #define XHC_ECHRSV2__reserved_L 31U 4482 #define XHC_ECHRSV2__reserved_R 16U 4483 #define XHC_ECHRSV2__reserved_WIDTH 16U 4484 #define XHC_ECHRSV2__reserved_RESETVALUE 0x0000U 4485 #define XHC_ECHRSV2__NCP_L 15U 4486 #define XHC_ECHRSV2__NCP_R 8U 4487 #define XHC_ECHRSV2__NCP_WIDTH 8U 4488 #define XHC_ECHRSV2__NCP_RESETVALUE 0x00U 4489 #define XHC_ECHRSV2__CID_L 7U 4490 #define XHC_ECHRSV2__CID_R 0U 4491 #define XHC_ECHRSV2__CID_WIDTH 8U 4492 #define XHC_ECHRSV2__CID_RESETVALUE 0xffU 4493 #define XHC_ECHRSV2_WIDTH 32U 4494 #define XHC_ECHRSV2__WIDTH 32U 4495 #define XHC_ECHRSV2_ALL_L 31U 4496 #define XHC_ECHRSV2_ALL_R 0U 4497 #define XHC_ECHRSV2__ALL_L 31U 4498 #define XHC_ECHRSV2__ALL_R 0U 4499 #define XHC_ECHRSV2_DATAMASK 0xffffffffU 4500 #define XHC_ECHRSV2_RDWRMASK 0x00000000U 4501 #define XHC_ECHRSV2_RESETVALUE 0x000000ffU 4502 4503 #define XHC_ECHIRA_OFFSET 0xf90U 4504 #define XHC_ECHIRA_BASE 0xf90U 4505 #define XHC_ECHIRA__reserved_L 31U 4506 #define XHC_ECHIRA__reserved_R 16U 4507 #define XHC_ECHIRA__reserved_WIDTH 16U 4508 #define XHC_ECHIRA__reserved_RESETVALUE 0x0000U 4509 #define XHC_ECHIRA__NCP_L 15U 4510 #define XHC_ECHIRA__NCP_R 8U 4511 #define XHC_ECHIRA__NCP_WIDTH 8U 4512 #define XHC_ECHIRA__NCP_RESETVALUE 0x04U 4513 #define XHC_ECHIRA__CID_L 7U 4514 #define XHC_ECHIRA__CID_R 0U 4515 #define XHC_ECHIRA__CID_WIDTH 8U 4516 #define XHC_ECHIRA__CID_RESETVALUE 0xfdU 4517 #define XHC_ECHIRA_WIDTH 32U 4518 #define XHC_ECHIRA__WIDTH 32U 4519 #define XHC_ECHIRA_ALL_L 31U 4520 #define XHC_ECHIRA_ALL_R 0U 4521 #define XHC_ECHIRA__ALL_L 31U 4522 #define XHC_ECHIRA__ALL_R 0U 4523 #define XHC_ECHIRA_DATAMASK 0xffffffffU 4524 #define XHC_ECHIRA_RDWRMASK 0x00000000U 4525 #define XHC_ECHIRA_RESETVALUE 0x000004fdU 4526 4527 #define XHC_IRAADR_OFFSET 0xf98U 4528 #define XHC_IRAADR_BASE 0xf98U 4529 #define XHC_IRAADR__ADR_L 23U 4530 #define XHC_IRAADR__ADR_R 2U 4531 #define XHC_IRAADR__ADR_WIDTH 22U 4532 #define XHC_IRAADR__ADR_RESETVALUE 0x0U 4533 #define XHC_IRAADR__reserved 1U 4534 #define XHC_IRAADR__reserved_L 1U 4535 #define XHC_IRAADR__reserved_R 1U 4536 #define XHC_IRAADR__reserved_WIDTH 1U 4537 #define XHC_IRAADR__reserved_RESETVALUE 0x0U 4538 #define XHC_IRAADR__MOD 0U 4539 #define XHC_IRAADR__MOD_L 0U 4540 #define XHC_IRAADR__MOD_R 0U 4541 #define XHC_IRAADR__MOD_WIDTH 1U 4542 #define XHC_IRAADR__MOD_RESETVALUE 0x0U 4543 #define XHC_IRAADR__RESERVED_L 31U 4544 #define XHC_IRAADR__RESERVED_R 24U 4545 #define XHC_IRAADR_WIDTH 24U 4546 #define XHC_IRAADR__WIDTH 24U 4547 #define XHC_IRAADR_ALL_L 23U 4548 #define XHC_IRAADR_ALL_R 0U 4549 #define XHC_IRAADR__ALL_L 23U 4550 #define XHC_IRAADR__ALL_R 0U 4551 #define XHC_IRAADR_DATAMASK 0x00ffffffU 4552 #define XHC_IRAADR_RDWRMASK 0xff000000U 4553 #define XHC_IRAADR_RESETVALUE 0x000000U 4554 4555 #define XHC_IRADAT_OFFSET 0xf9cU 4556 #define XHC_IRADAT_BASE 0xf9cU 4557 #define XHC_IRADAT__DAT_L 31U 4558 #define XHC_IRADAT__DAT_R 0U 4559 #define XHC_IRADAT__DAT_WIDTH 32U 4560 #define XHC_IRADAT__DAT_RESETVALUE 0x00000000U 4561 #define XHC_IRADAT_WIDTH 32U 4562 #define XHC_IRADAT__WIDTH 32U 4563 #define XHC_IRADAT_ALL_L 31U 4564 #define XHC_IRADAT_ALL_R 0U 4565 #define XHC_IRADAT__ALL_L 31U 4566 #define XHC_IRADAT__ALL_R 0U 4567 #define XHC_IRADAT_DATAMASK 0xffffffffU 4568 #define XHC_IRADAT_RDWRMASK 0x00000000U 4569 #define XHC_IRADAT_RESETVALUE 0x00000000U 4570 4571 4572 #define XHC_ECHHST_OFFSET 0xfa0U 4573 #define XHC_ECHHST_BASE 0xfa0U 4574 #define XHC_ECHHST__CCC 31U 4575 #define XHC_ECHHST__CCC_L 31U 4576 #define XHC_ECHHST__CCC_R 31U 4577 #define XHC_ECHHST__CCC_WIDTH 1U 4578 #define XHC_ECHHST__CCC_RESETVALUE 0x1U 4579 #define XHC_ECHHST__PME 30U 4580 #define XHC_ECHHST__PME_L 30U 4581 #define XHC_ECHHST__PME_R 30U 4582 #define XHC_ECHHST__PME_WIDTH 1U 4583 #define XHC_ECHHST__PME_RESETVALUE 0x0U 4584 #define XHC_ECHHST__AUX_L 29U 4585 #define XHC_ECHHST__AUX_R 24U 4586 #define XHC_ECHHST__AUX_WIDTH 6U 4587 #define XHC_ECHHST__AUX_RESETVALUE 0x0U 4588 #define XHC_ECHHST__IRA 20U 4589 #define XHC_ECHHST__IRA_L 20U 4590 #define XHC_ECHHST__IRA_R 20U 4591 #define XHC_ECHHST__IRA_WIDTH 1U 4592 #define XHC_ECHHST__IRA_RESETVALUE 0x0U 4593 #define XHC_ECHHST__ULS 19U 4594 #define XHC_ECHHST__ULS_L 19U 4595 #define XHC_ECHHST__ULS_R 19U 4596 #define XHC_ECHHST__ULS_WIDTH 1U 4597 #define XHC_ECHHST__ULS_RESETVALUE 0x0U 4598 #define XHC_ECHHST__reserved 18U 4599 #define XHC_ECHHST__reserved_L 18U 4600 #define XHC_ECHHST__reserved_R 18U 4601 #define XHC_ECHHST__reserved_WIDTH 1U 4602 #define XHC_ECHHST__reserved_RESETVALUE 0x0U 4603 #define XHC_ECHHST__TEDA 17U 4604 #define XHC_ECHHST__TEDA_L 17U 4605 #define XHC_ECHHST__TEDA_R 17U 4606 #define XHC_ECHHST__TEDA_WIDTH 1U 4607 #define XHC_ECHHST__TEDA_RESETVALUE 0x0U 4608 #define XHC_ECHHST__FSW 16U 4609 #define XHC_ECHHST__FSW_L 16U 4610 #define XHC_ECHHST__FSW_R 16U 4611 #define XHC_ECHHST__FSW_WIDTH 1U 4612 #define XHC_ECHHST__FSW_RESETVALUE 0x1U 4613 #define XHC_ECHHST__NCP_L 15U 4614 #define XHC_ECHHST__NCP_R 8U 4615 #define XHC_ECHHST__NCP_WIDTH 8U 4616 #define XHC_ECHHST__NCP_RESETVALUE 0x04U 4617 #define XHC_ECHHST__CID_L 7U 4618 #define XHC_ECHHST__CID_R 0U 4619 #define XHC_ECHHST__CID_WIDTH 8U 4620 #define XHC_ECHHST__CID_RESETVALUE 0xfcU 4621 #define XHC_ECHHST__RESERVED_L 23U 4622 #define XHC_ECHHST__RESERVED_R 21U 4623 #define XHC_ECHHST_WIDTH 32U 4624 #define XHC_ECHHST__WIDTH 32U 4625 #define XHC_ECHHST_ALL_L 31U 4626 #define XHC_ECHHST_ALL_R 0U 4627 #define XHC_ECHHST__ALL_L 31U 4628 #define XHC_ECHHST__ALL_R 0U 4629 #define XHC_ECHHST_DATAMASK 0xff1fffffU 4630 #define XHC_ECHHST_RDWRMASK 0x00e00000U 4631 #define XHC_ECHHST_RESETVALUE 0x800104fcU 4632 4633 #define XHC_HSTDBG_OFFSET 0xfa4U 4634 #define XHC_HSTDBG_BASE 0xfa4U 4635 #define XHC_HSTDBG__ETE 31U 4636 #define XHC_HSTDBG__ETE_L 31U 4637 #define XHC_HSTDBG__ETE_R 31U 4638 #define XHC_HSTDBG__ETE_WIDTH 1U 4639 #define XHC_HSTDBG__ETE_RESETVALUE 0x0U 4640 #define XHC_HSTDBG__reserved_L 30U 4641 #define XHC_HSTDBG__reserved_R 16U 4642 #define XHC_HSTDBG__reserved_WIDTH 15U 4643 #define XHC_HSTDBG__reserved_RESETVALUE 0x0U 4644 #define XHC_HSTDBG__OUTP_L 15U 4645 #define XHC_HSTDBG__OUTP_R 8U 4646 #define XHC_HSTDBG__OUTP_WIDTH 8U 4647 #define XHC_HSTDBG__OUTP_RESETVALUE 0x00U 4648 #define XHC_HSTDBG__INP_L 7U 4649 #define XHC_HSTDBG__INP_R 0U 4650 #define XHC_HSTDBG__INP_WIDTH 8U 4651 #define XHC_HSTDBG__INP_RESETVALUE 0x00U 4652 #define XHC_HSTDBG_WIDTH 32U 4653 #define XHC_HSTDBG__WIDTH 32U 4654 #define XHC_HSTDBG_ALL_L 31U 4655 #define XHC_HSTDBG_ALL_R 0U 4656 #define XHC_HSTDBG__ALL_L 31U 4657 #define XHC_HSTDBG__ALL_R 0U 4658 #define XHC_HSTDBG_DATAMASK 0xffffffffU 4659 #define XHC_HSTDBG_RDWRMASK 0x00000000U 4660 #define XHC_HSTDBG_RESETVALUE 0x00000000U 4661 4662 #define XHC_HSTNPL_OFFSET 0xfa8U 4663 #define XHC_HSTNPL_BASE 0xfa8U 4664 #define XHC_HSTNPL__NPL_L 31U 4665 #define XHC_HSTNPL__NPL_R 9U 4666 #define XHC_HSTNPL__NPL_WIDTH 23U 4667 #define XHC_HSTNPL__NPL_RESETVALUE 0x0U 4668 #define XHC_HSTNPL__reserved_L 8U 4669 #define XHC_HSTNPL__reserved_R 0U 4670 #define XHC_HSTNPL__reserved_WIDTH 9U 4671 #define XHC_HSTNPL__reserved_RESETVALUE 0x0U 4672 #define XHC_HSTNPL_WIDTH 32U 4673 #define XHC_HSTNPL__WIDTH 32U 4674 #define XHC_HSTNPL_ALL_L 31U 4675 #define XHC_HSTNPL_ALL_R 0U 4676 #define XHC_HSTNPL__ALL_L 31U 4677 #define XHC_HSTNPL__ALL_R 0U 4678 #define XHC_HSTNPL_DATAMASK 0xffffffffU 4679 #define XHC_HSTNPL_RDWRMASK 0x00000000U 4680 #define XHC_HSTNPL_RESETVALUE 0x00000000U 4681 4682 #define XHC_HSTNPH_OFFSET 0xfacU 4683 #define XHC_HSTNPH_BASE 0xfacU 4684 #define XHC_HSTNPH__NPH_L 31U 4685 #define XHC_HSTNPH__NPH_R 0U 4686 #define XHC_HSTNPH__NPH_WIDTH 32U 4687 #define XHC_HSTNPH__NPH_RESETVALUE 0x00000000U 4688 #define XHC_HSTNPH_WIDTH 32U 4689 #define XHC_HSTNPH__WIDTH 32U 4690 #define XHC_HSTNPH_ALL_L 31U 4691 #define XHC_HSTNPH_ALL_R 0U 4692 #define XHC_HSTNPH__ALL_L 31U 4693 #define XHC_HSTNPH__ALL_R 0U 4694 #define XHC_HSTNPH_DATAMASK 0xffffffffU 4695 #define XHC_HSTNPH_RDWRMASK 0x00000000U 4696 #define XHC_HSTNPH_RESETVALUE 0x00000000U 4697 4698 #define XHC_ECHRBV_OFFSET 0xfb0U 4699 #define XHC_ECHRBV_BASE 0xfb0U 4700 #define XHC_ECHRBV__MAJ_L 31U 4701 #define XHC_ECHRBV__MAJ_R 28U 4702 #define XHC_ECHRBV__MAJ_WIDTH 4U 4703 #define XHC_ECHRBV__MAJ_RESETVALUE 0x0U 4704 #define XHC_ECHRBV__MIN_L 27U 4705 #define XHC_ECHRBV__MIN_R 24U 4706 #define XHC_ECHRBV__MIN_WIDTH 4U 4707 #define XHC_ECHRBV__MIN_RESETVALUE 0x0U 4708 #define XHC_ECHRBV__RLS_L 23U 4709 #define XHC_ECHRBV__RLS_R 16U 4710 #define XHC_ECHRBV__RLS_WIDTH 8U 4711 #define XHC_ECHRBV__RLS_RESETVALUE 0x00U 4712 #define XHC_ECHRBV__NCP_L 15U 4713 #define XHC_ECHRBV__NCP_R 8U 4714 #define XHC_ECHRBV__NCP_WIDTH 8U 4715 #define XHC_ECHRBV__NCP_RESETVALUE 0x00U 4716 #define XHC_ECHRBV__CID_L 7U 4717 #define XHC_ECHRBV__CID_R 0U 4718 #define XHC_ECHRBV__CID_WIDTH 8U 4719 #define XHC_ECHRBV__CID_RESETVALUE 0xfeU 4720 #define XHC_ECHRBV_WIDTH 32U 4721 #define XHC_ECHRBV__WIDTH 32U 4722 #define XHC_ECHRBV_ALL_L 31U 4723 #define XHC_ECHRBV_ALL_R 0U 4724 #define XHC_ECHRBV__ALL_L 31U 4725 #define XHC_ECHRBV__ALL_R 0U 4726 #define XHC_ECHRBV_DATAMASK 0xffffffffU 4727 #define XHC_ECHRBV_RDWRMASK 0x00000000U 4728 #define XHC_ECHRBV_RESETVALUE 0x000000feU 4729 4730 #define XHC_RBVPDT_OFFSET 0xfb4U 4731 #define XHC_RBVPDT_BASE 0xfb4U 4732 #define XHC_RBVPDT__VDR_L 31U 4733 #define XHC_RBVPDT__VDR_R 16U 4734 #define XHC_RBVPDT__VDR_WIDTH 16U 4735 #define XHC_RBVPDT__VDR_RESETVALUE 0x0a5cU 4736 #define XHC_RBVPDT__PDT_L 15U 4737 #define XHC_RBVPDT__PDT_R 0U 4738 #define XHC_RBVPDT__PDT_WIDTH 16U 4739 #define XHC_RBVPDT__PDT_RESETVALUE 0x0000U 4740 #define XHC_RBVPDT_WIDTH 32U 4741 #define XHC_RBVPDT__WIDTH 32U 4742 #define XHC_RBVPDT_ALL_L 31U 4743 #define XHC_RBVPDT_ALL_R 0U 4744 #define XHC_RBVPDT__ALL_L 31U 4745 #define XHC_RBVPDT__ALL_R 0U 4746 #define XHC_RBVPDT_DATAMASK 0xffffffffU 4747 #define XHC_RBVPDT_RDWRMASK 0x00000000U 4748 #define XHC_RBVPDT_RESETVALUE 0x0a5c0000U 4749 4750 #define XHC_RBVMGN_OFFSET 0xfbcU 4751 #define XHC_RBVMGN_BASE 0xfbcU 4752 #define XHC_RBVMGN__MGN_L 31U 4753 #define XHC_RBVMGN__MGN_R 0U 4754 #define XHC_RBVMGN__MGN_WIDTH 32U 4755 #define XHC_RBVMGN__MGN_RESETVALUE 0x52535354U 4756 #define XHC_RBVMGN_WIDTH 32U 4757 #define XHC_RBVMGN__WIDTH 32U 4758 #define XHC_RBVMGN_ALL_L 31U 4759 #define XHC_RBVMGN_ALL_R 0U 4760 #define XHC_RBVMGN__ALL_L 31U 4761 #define XHC_RBVMGN__ALL_R 0U 4762 #define XHC_RBVMGN_DATAMASK 0xffffffffU 4763 #define XHC_RBVMGN_RDWRMASK 0x00000000U 4764 #define XHC_RBVMGN_RESETVALUE 0x52535354U 4765 4766 /* PORTSC field defines */ 4767 #define XHC_PORTSC__PS_LINK_STATE_U0 0U 4768 #define XHC_PORTSC__PS_LINK_STATE_U1 1U 4769 #define XHC_PORTSC__PS_LINK_STATE_U2 2U 4770 #define XHC_PORTSC__PS_LINK_STATE_U3 3U 4771 #define XHC_PORTSC__PS_LINK_STATE_DISABLED 4U 4772 #define XHC_PORTSC__PS_LINK_STATE_RX_DETECT 5U 4773 #define XHC_PORTSC__PS_LINK_STATE_INACTIVE 6U 4774 #define XHC_PORTSC__PS_LINK_STATE_POLLING 7U 4775 #define XHC_PORTSC__PS_LINK_STATE_RECOVERY 8U 4776 #define XHC_PORTSC__PS_LINK_STATE_HOT_RESET 9U 4777 #define XHC_PORTSC__PS_LINK_STATE_COMPLIANCE 10U 4778 #define XHC_PORTSC__PS_LINK_STATE_TEST 11U 4779 #define XHC_PORTSC__PS_LINK_STATE_RESUME 15U 4780 4781 #define XHC_PORTSC__PS_SPEED_UNDEFINED 0U 4782 #define XHC_PORTSC__PS_FS 1U 4783 #define XHC_PORTSC__PS_LS 2U 4784 #define XHC_PORTSC__PS_HS 3U 4785 #define XHC_PORTSC__PS_SS 4U 4786 4787 /* macros and inline functions */ 4788 4789 /* write 64bit ptr 'p' to destination 'd' with offset 'v' */ WRITE64_REG_PTRL(uint32_t r,uint32_t * p)4790inline void WRITE64_REG_PTRL(uint32_t r, uint32_t *p) 4791 { 4792 uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r); 4793 4794 *ptr = (uint32_t) ((uint64_t) p & (uint64_t) 0xffffffffU); 4795 } 4796 WRITE64_REG_PTRH(uint32_t r,uint32_t * p)4797inline void WRITE64_REG_PTRH(uint32_t r, uint32_t *p) 4798 { 4799 uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r); 4800 4801 *ptr = (uint32_t) ((uint64_t) p >> 32U); 4802 } 4803 4804 #define XHC_REG_RD(addr) mmio_read_32(XHC_BASE + addr) 4805 4806 #define XHC_REG_WR(addr, val) mmio_write_32(XHC_BASE+addr, val) 4807 4808 #endif /* USBH_XHCI_REGS_H */ 4809 4810