1 /*
2 * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_FEATURES_H
8 #define ARCH_FEATURES_H
9
10 #include <stdbool.h>
11
12 #include <arch_helpers.h>
13 #include <common/feat_detect.h>
14
15 #define ISOLATE_FIELD(reg, feat, mask) \
16 ((unsigned int)(((reg) >> (feat)) & mask))
17
18 #define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
19 static inline bool is_ ## name ## _supported(void) \
20 { \
21 if ((guard) == FEAT_STATE_DISABLED) { \
22 return false; \
23 } \
24 if ((guard) == FEAT_STATE_ALWAYS) { \
25 return true; \
26 } \
27 return read_func(); \
28 }
29
30 #define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
31 static inline bool is_ ## name ## _present(void) \
32 { \
33 return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
34 ? true : false; \
35 }
36
37 #define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
38 CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
39 CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
40
41
42 /* +----------------------------+
43 * | Features supported |
44 * +----------------------------+
45 * | GENTIMER |
46 * +----------------------------+
47 * | FEAT_PAN |
48 * +----------------------------+
49 * | FEAT_VHE |
50 * +----------------------------+
51 * | FEAT_TTCNP |
52 * +----------------------------+
53 * | FEAT_UAO |
54 * +----------------------------+
55 * | FEAT_PACQARMA3 |
56 * +----------------------------+
57 * | FEAT_PAUTH |
58 * +----------------------------+
59 * | FEAT_TTST |
60 * +----------------------------+
61 * | FEAT_BTI |
62 * +----------------------------+
63 * | FEAT_MTE2 |
64 * +----------------------------+
65 * | FEAT_SSBS |
66 * +----------------------------+
67 * | FEAT_NMI |
68 * +----------------------------+
69 * | FEAT_GCS |
70 * +----------------------------+
71 * | FEAT_EBEP |
72 * +----------------------------+
73 * | FEAT_SEBEP |
74 * +----------------------------+
75 * | FEAT_SEL2 |
76 * +----------------------------+
77 * | FEAT_TWED |
78 * +----------------------------+
79 * | FEAT_FGT |
80 * +----------------------------+
81 * | FEAT_EC/ECV2 |
82 * +----------------------------+
83 * | FEAT_RNG |
84 * +----------------------------+
85 * | FEAT_TCR2 |
86 * +----------------------------+
87 * | FEAT_S2POE |
88 * +----------------------------+
89 * | FEAT_S1POE |
90 * +----------------------------+
91 * | FEAT_S2PIE |
92 * +----------------------------+
93 * | FEAT_S1PIE |
94 * +----------------------------+
95 * | FEAT_AMU/AMUV1P1 |
96 * +----------------------------+
97 * | FEAT_MPAM |
98 * +----------------------------+
99 * | FEAT_HCX |
100 * +----------------------------+
101 * | FEAT_RNG_TRAP |
102 * +----------------------------+
103 * | FEAT_RME |
104 * +----------------------------+
105 * | FEAT_SB |
106 * +----------------------------+
107 * | FEAT_CSV2/CSV3 |
108 * +----------------------------+
109 * | FEAT_SPE |
110 * +----------------------------+
111 * | FEAT_SVE |
112 * +----------------------------+
113 * | FEAT_RAS |
114 * +----------------------------+
115 * | FEAT_DIT |
116 * +----------------------------+
117 * | FEAT_SYS_REG_TRACE |
118 * +----------------------------+
119 * | FEAT_TRF |
120 * +----------------------------+
121 * | FEAT_NV/NV2 |
122 * +----------------------------+
123 * | FEAT_BRBE |
124 * +----------------------------+
125 * | FEAT_TRBE |
126 * +----------------------------+
127 * | FEAT_SME/SME2 |
128 * +----------------------------+
129 * | FEAT_PMUV3 |
130 * +----------------------------+
131 * | FEAT_MTPMU |
132 * +----------------------------+
133 */
134
is_armv7_gentimer_present(void)135 static inline bool is_armv7_gentimer_present(void)
136 {
137 /* The Generic Timer is always present in an ARMv8-A implementation */
138 return true;
139 }
140
141 /* FEAT_PAN: Privileged access never */
142 CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
143 ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN)
144
145 /* FEAT_VHE: Virtualization Host Extensions */
146 CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
147 ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE)
148
149 /* FEAT_TTCNP: Translation table common not private */
150 CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
151 ID_AA64MMFR2_EL1_CNP_MASK, 1U)
152
153 /* FEAT_UAO: User access override */
154 CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
155 ID_AA64MMFR2_EL1_UAO_MASK, 1U)
156
157 /* If any of the fields is not zero, QARMA3 algorithm is present */
158 CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
159 ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
160 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
161
162 /* PAUTH */
is_armv8_3_pauth_present(void)163 static inline bool is_armv8_3_pauth_present(void)
164 {
165 uint64_t mask_id_aa64isar1 =
166 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
167 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
168 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
169 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
170
171 /*
172 * If any of the fields is not zero or QARMA3 is present,
173 * PAuth is present
174 */
175 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
176 is_feat_pacqarma3_present());
177 }
178
179 /* FEAT_TTST: Small translation tables */
180 CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
181 ID_AA64MMFR2_EL1_ST_MASK, 1U)
182
183 /* FEAT_BTI: Branch target identification */
CREATE_FEATURE_PRESENT(feat_bti,id_aa64pfr1_el1,ID_AA64PFR1_EL1_BT_SHIFT,ID_AA64PFR1_EL1_BT_MASK,BTI_IMPLEMENTED)184 CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
185 ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
186
187 /* FEAT_MTE2: Memory tagging extension */
188 CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
189 ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2)
190
191 /* FEAT_SSBS: Speculative store bypass safe */
192 CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
193 ID_AA64PFR1_EL1_SSBS_MASK, 1U)
194
195 /* FEAT_NMI: Non-maskable interrupts */
196 CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
197 ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED)
198
199 /* FEAT_EBEP */
200 CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
201 ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED)
202
203 /* FEAT_SEBEP */
204 CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
205 ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED)
206
207 /* FEAT_SEL2: Secure EL2 */
208 CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
209 ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2)
210
211 /* FEAT_TWED: Delayed trapping of WFE */
212 CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
213 ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED)
214
215 /* FEAT_FGT: Fine-grained traps */
216 CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
217 ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
218
219 /* FEAT_ECV: Enhanced Counter Virtualization */
220 CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
221 ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
222 CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
223 ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
224
225 /* FEAT_RNG: Random number generator */
226 CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
227 ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG)
228
229 /* FEAT_TCR2: Support TCR2_ELx regs */
230 CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
231 ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2)
232
233 /* FEAT_S2POE */
234 CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
235 ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE)
236
237 /* FEAT_S1POE */
238 CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
239 ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
240
241 static inline bool is_feat_sxpoe_supported(void)
242 {
243 return is_feat_s1poe_supported() || is_feat_s2poe_supported();
244 }
245
246 /* FEAT_S2PIE */
247 CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
248 ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE)
249
250 /* FEAT_S1PIE */
251 CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
252 ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
253
is_feat_sxpie_supported(void)254 static inline bool is_feat_sxpie_supported(void)
255 {
256 return is_feat_s1pie_supported() || is_feat_s2pie_supported();
257 }
258
259 /* FEAT_GCS: Guarded Control Stack */
260 CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
261 ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS)
262
263 /* FEAT_AMU: Activity Monitors Extension */
264 CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
265 ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU)
266
267 /* FEAT_AMUV1P1: AMU Extension v1.1 */
CREATE_FEATURE_FUNCS(feat_amuv1p1,id_aa64pfr0_el1,ID_AA64PFR0_AMU_SHIFT,ID_AA64PFR0_AMU_MASK,ID_AA64PFR0_AMU_V1P1,ENABLE_FEAT_AMUv1p1)268 CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
269 ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
270
271 /*
272 * Return MPAM version:
273 *
274 * 0x00: None Armv8.0 or later
275 * 0x01: v0.1 Armv8.4 or later
276 * 0x10: v1.0 Armv8.2 or later
277 * 0x11: v1.1 Armv8.4 or later
278 *
279 */
280 static inline bool is_feat_mpam_present(void)
281 {
282 unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
283 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
284 ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
285 & ID_AA64PFR1_MPAM_FRAC_MASK));
286 return ret;
287 }
288
CREATE_FEATURE_SUPPORTED(feat_mpam,is_feat_mpam_present,ENABLE_FEAT_MPAM)289 CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
290
291 /* FEAT_HCX: Extended Hypervisor Configuration Register */
292 CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
293 ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
294
295 /* FEAT_RNG_TRAP: Trapping support */
296 CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
297 ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED)
298
299 /* Return the RME version, zero if not supported. */
300 CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT,
301 ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME)
302
303 /* FEAT_SB: Speculation barrier instruction */
304 CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
305 ID_AA64ISAR1_SB_MASK, 1U)
306
307 /*
308 * FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
309 * of id_aa64pfr0_el1 register and can be used to check for below features:
310 * FEAT_CSV2_2: Cache Speculation Variant CSV2_2.
311 * FEAT_CSV2_3: Cache Speculation Variant CSV2_3.
312 * 0b0000 - Feature FEAT_CSV2 is not implemented.
313 * 0b0001 - Feature FEAT_CSV2 is implemented, but FEAT_CSV2_2 and FEAT_CSV2_3
314 * are not implemented.
315 * 0b0010 - Feature FEAT_CSV2_2 is implemented but FEAT_CSV2_3 is not
316 * implemented.
317 * 0b0011 - Feature FEAT_CSV2_3 is implemented.
318 */
319
320 CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
321 ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
322 CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
323 ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
324
325 /* FEAT_SPE: Statistical Profiling Extension */
326 CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
327 ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS)
328
329 /* FEAT_SVE: Scalable Vector Extension */
330 CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
331 ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS)
332
333 /* FEAT_RAS: Reliability, Accessibility, Serviceability */
334 CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
335 ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS)
336
337 /* FEAT_DIT: Data Independent Timing instructions */
338 CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
339 ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
340
341 /* FEAT_SYS_REG_TRACE */
342 CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT,
343 ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
344
345 /* FEAT_TRF: TraceFilter */
346 CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
347 ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
348
349 /* FEAT_NV2: Enhanced Nested Virtualization */
350 CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
351 ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U)
352 CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
353 ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
354
355 /* FEAT_BRBE: Branch Record Buffer Extension */
356 CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
357 ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS)
358
359 /* FEAT_TRBE: Trace Buffer Extension */
360 CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
361 ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS)
362
363 /* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
364 CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
365 ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U)
366
367 /* FEAT_SMEx: Scalar Matrix Extension */
368 CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
369 ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS)
370
371 CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
372 ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
373
374 /*******************************************************************************
375 * Function to get hardware granularity support
376 ******************************************************************************/
377
378 static inline bool is_feat_tgran4K_present(void)
379 {
380 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
381 ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
382 return (tgranx < 8U);
383 }
384
CREATE_FEATURE_PRESENT(feat_tgran16K,id_aa64mmfr0_el1,ID_AA64MMFR0_EL1_TGRAN16_SHIFT,ID_AA64MMFR0_EL1_TGRAN16_MASK,TGRAN16_IMPLEMENTED)385 CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
386 ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
387
388 static inline bool is_feat_tgran64K_present(void)
389 {
390 unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
391 ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
392 return (tgranx < 8U);
393 }
394
395 /* FEAT_PMUV3 */
396 CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
397 ID_AA64DFR0_PMUVER_MASK, 1U)
398
399 /* FEAT_MTPMU */
is_feat_mtpmu_present(void)400 static inline bool is_feat_mtpmu_present(void)
401 {
402 unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
403 ID_AA64DFR0_MTPMU_MASK);
404 return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
405 }
406
407 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
408
409 #endif /* ARCH_FEATURES_H */
410