1/*
2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <platform_def.h>
11
12#if TARGET_FLAVOUR_FVP
13#define LIT_CAPACITY			406
14#define MID_CAPACITY			912
15#else /* TARGET_FLAVOUR_FPGA */
16#define LIT_CAPACITY			280
17#define MID_CAPACITY			775
18/* this is an area optimized configuration of the big core */
19#define BIG2_CAPACITY			930
20#endif /* TARGET_FLAVOUR_FPGA */
21#define BIG_CAPACITY			1024
22
23#define INT_MBOX_RX			317
24#define MHU_TX_ADDR			45000000 /* hex */
25#define MHU_RX_ADDR			45010000 /* hex */
26#define MPAM_ADDR			0x1 0x00010000 /* 0x1_0001_0000 */
27#define UARTCLK_FREQ			5000000
28
29#define DPU_ADDR			2cc00000
30#define DPU_IRQ				69
31
32#include "tc-common.dtsi"
33#if TARGET_FLAVOUR_FVP
34#include "tc-fvp.dtsi"
35#else
36#include "tc-fpga.dtsi"
37#endif /* TARGET_FLAVOUR_FVP */
38#include "tc-base.dtsi"
39
40/ {
41	cpus {
42#if TARGET_FLAVOUR_FPGA
43		cpu-map {
44			cluster0 {
45				core8 {
46					cpu = <&CPU8>;
47				};
48				core9 {
49					cpu = <&CPU9>;
50				};
51				core10 {
52					cpu = <&CPU10>;
53				};
54				core11 {
55					cpu = <&CPU11>;
56				};
57				core12 {
58					cpu = <&CPU12>;
59				};
60				core13 {
61					cpu = <&CPU13>;
62				};
63			};
64		};
65#endif
66
67		CPU2:cpu@200 {
68			clocks = <&scmi_dvfs 0>;
69			capacity-dmips-mhz = <LIT_CAPACITY>;
70		};
71
72		CPU3:cpu@300 {
73			clocks = <&scmi_dvfs 0>;
74			capacity-dmips-mhz = <LIT_CAPACITY>;
75		};
76
77		CPU6:cpu@600 {
78			clocks = <&scmi_dvfs 1>;
79			capacity-dmips-mhz = <MID_CAPACITY>;
80		};
81
82		CPU7:cpu@700 {
83			clocks = <&scmi_dvfs 1>;
84			capacity-dmips-mhz = <MID_CAPACITY>;
85		};
86
87#if TARGET_FLAVOUR_FPGA
88		CPU8:cpu@800 {
89			device_type = "cpu";
90			compatible = "arm,armv8";
91			reg = <0x800>;
92			enable-method = "psci";
93			clocks = <&scmi_dvfs 1>;
94			capacity-dmips-mhz = <MID_CAPACITY>;
95			amu = <&amu>;
96			supports-mpmm;
97		};
98
99		CPU9:cpu@900 {
100			device_type = "cpu";
101			compatible = "arm,armv8";
102			reg = <0x900>;
103			enable-method = "psci";
104			clocks = <&scmi_dvfs 2>;
105			capacity-dmips-mhz = <BIG2_CAPACITY>;
106			amu = <&amu>;
107			supports-mpmm;
108		};
109
110		CPU10:cpu@A00 {
111			device_type = "cpu";
112			compatible = "arm,armv8";
113			reg = <0xA00>;
114			enable-method = "psci";
115			clocks = <&scmi_dvfs 2>;
116			capacity-dmips-mhz = <BIG2_CAPACITY>;
117			amu = <&amu>;
118			supports-mpmm;
119		};
120
121		CPU11:cpu@B00 {
122			device_type = "cpu";
123			compatible = "arm,armv8";
124			reg = <0xB00>;
125			enable-method = "psci";
126			clocks = <&scmi_dvfs 2>;
127			capacity-dmips-mhz = <BIG2_CAPACITY>;
128			amu = <&amu>;
129			supports-mpmm;
130		};
131
132		CPU12:cpu@C00 {
133			device_type = "cpu";
134			compatible = "arm,armv8";
135			reg = <0xC00>;
136			enable-method = "psci";
137			clocks = <&scmi_dvfs 3>;
138			capacity-dmips-mhz = <BIG_CAPACITY>;
139			amu = <&amu>;
140			supports-mpmm;
141		};
142
143		CPU13:cpu@D00 {
144			device_type = "cpu";
145			compatible = "arm,armv8";
146			reg = <0xD00>;
147			enable-method = "psci";
148			clocks = <&scmi_dvfs 3>;
149			capacity-dmips-mhz = <BIG_CAPACITY>;
150			amu = <&amu>;
151			supports-mpmm;
152		};
153#endif
154	};
155
156#if TARGET_FLAVOUR_FPGA
157	ete8 {
158		compatible = "arm,embedded-trace-extension";
159		cpu = <&CPU8>;
160	};
161
162	ete9 {
163		compatible = "arm,embedded-trace-extension";
164		cpu = <&CPU9>;
165	};
166
167	ete10 {
168		compatible = "arm,embedded-trace-extension";
169		cpu = <&CPU10>;
170	};
171
172	ete11 {
173		compatible = "arm,embedded-trace-extension";
174		cpu = <&CPU11>;
175	};
176
177	ete12 {
178		compatible = "arm,embedded-trace-extension";
179		cpu = <&CPU12>;
180	};
181
182	ete13 {
183		compatible = "arm,embedded-trace-extension";
184		cpu = <&CPU13>;
185	};
186#endif /* TARGET_FLAVOUR_FPGA */
187
188	cpu-pmu {
189#if TARGET_FLAVOUR_FPGA
190		interrupt-affinity = <&CPU0>,  <&CPU1>,  <&CPU2>,  <&CPU3>,
191				     <&CPU4>,  <&CPU5>,  <&CPU6>,  <&CPU7>,
192				     <&CPU8>,  <&CPU9>,  <&CPU10>, <&CPU11>,
193				     <&CPU12>, <&CPU13>;
194#else
195		interrupt-affinity = <&CPU0>,  <&CPU1>,  <&CPU2>,  <&CPU3>,
196				     <&CPU4>,  <&CPU5>,  <&CPU6>,  <&CPU7>;
197#endif
198	};
199
200	cmn-pmu {
201		compatible = "arm,ci-700";
202		reg = <0x0 0x50000000 0x0 0x10000000>;
203		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
204	};
205
206	mbox_db_rx: mhu@MHU_RX_ADDR {
207		arm,mhuv2-protocols = <0 1>;
208	};
209
210	mbox_db_tx: mhu@MHU_TX_ADDR {
211		arm,mhuv2-protocols = <0 1>;
212	};
213
214	dp0: display@DPU_ADDR {
215#if TC_SCMI_PD_CTRL_EN
216		power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
217#endif
218	};
219};
220