1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <[email protected]> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp25-clks.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/reset/stm32mp25-resets.h>
10
11/ {
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-a35";
21			device_type = "cpu";
22			reg = <0>;
23			enable-method = "psci";
24		};
25	};
26
27	clocks {
28		clk_hse: clk-hse {
29			#clock-cells = <0>;
30			compatible = "fixed-clock";
31			clock-frequency = <48000000>;
32		};
33
34		clk_hsi: clk-hsi {
35			#clock-cells = <0>;
36			compatible = "fixed-clock";
37			clock-frequency = <64000000>;
38		};
39
40		clk_lse: clk-lse {
41			#clock-cells = <0>;
42			compatible = "fixed-clock";
43			clock-frequency = <32768>;
44		};
45
46		clk_lsi: clk-lsi {
47			#clock-cells = <0>;
48			compatible = "fixed-clock";
49			clock-frequency = <32000>;
50		};
51
52		clk_msi: clk-msi {
53			#clock-cells = <0>;
54			compatible = "fixed-clock";
55			clock-frequency = <16000000>;
56		};
57	};
58
59	intc: interrupt-controller@4ac00000 {
60		compatible = "arm,cortex-a7-gic";
61		#interrupt-cells = <3>;
62		#address-cells = <1>;
63		interrupt-controller;
64		reg = <0x0 0x4ac10000 0x0 0x1000>,
65		      <0x0 0x4ac20000 0x0 0x2000>,
66		      <0x0 0x4ac40000 0x0 0x2000>,
67		      <0x0 0x4ac60000 0x0 0x2000>;
68	};
69
70	timer {
71		compatible = "arm,armv8-timer";
72		interrupt-parent = <&intc>;
73		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
76			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77		always-on;
78	};
79
80	soc@0 {
81		compatible = "simple-bus";
82		#address-cells = <1>;
83		#size-cells = <1>;
84		interrupt-parent = <&intc>;
85		ranges = <0x0 0x0 0x0 0x80000000>;
86
87		rifsc: rifsc@42080000 {
88			compatible = "st,stm32mp25-rifsc";
89			reg = <0x42080000 0x1000>;
90			#address-cells = <1>;
91			#size-cells = <1>;
92
93			usart2: serial@400e0000 {
94				compatible = "st,stm32h7-uart";
95				reg = <0x400e0000 0x400>;
96				clocks = <&rcc CK_KER_USART2>;
97				resets = <&rcc USART2_R>;
98				status = "disabled";
99			};
100		};
101
102		bsec: efuse@44000000 {
103			compatible = "st,stm32mp25-bsec";
104			reg = <0x44000000 0x400>;
105			#address-cells = <1>;
106			#size-cells = <1>;
107
108			uid_otp: uid-otp@14 {
109				reg = <0x14 0xc>;
110			};
111			part_number_otp: part-number-otp@24 {
112				reg = <0x24 0x4>;
113			};
114			nand_otp: otp16@40 {
115				reg = <0x40 0x4>;
116			};
117			lifecycle2_otp: otp18@48 {
118				reg = <0x48 0x4>;
119			};
120			nand2_otp: otp20@50 {
121				reg = <0x50 0x4>;
122			};
123			package_otp: package-otp@1e8 {
124				reg = <0x1e8 0x1>;
125			};
126			hconf1_otp: otp124@1f0 {
127				reg = <0x1f0 0x4>;
128			};
129			pkh_otp: otp144@240 {
130				reg = <0x240 0x20>;
131			};
132			oem_fip_enc_key: otp260@410 {
133				reg = <0x410 0x20>;
134			};
135		};
136
137		rcc: rcc@44200000 {
138			compatible = "st,stm32mp25-rcc";
139			reg = <0x44200000 0x10000>;
140			#clock-cells = <1>;
141			#reset-cells = <1>;
142		};
143
144		pwr: pwr@44210000 {
145			compatible = "st,stm32mp25-pwr";
146			reg = <0x44210000 0x400>;
147
148			vddio1: vddio1 {
149				regulator-name = "vddio1";
150			};
151
152			vddio2: vddio2 {
153				regulator-name = "vddio2";
154			};
155
156			vddio3: vddio3 {
157				regulator-name = "vddio3";
158			};
159
160			vddio4: vddio4 {
161				regulator-name = "vddio4";
162			};
163
164			vddio: vddio {
165				regulator-name = "vddio";
166			};
167		};
168
169		syscfg: syscon@44230000 {
170			compatible = "st,stm32mp25-syscfg", "syscon";
171			reg = <0x44230000 0x10000>;
172		};
173
174		pinctrl: pinctrl@44240000 {
175			#address-cells = <1>;
176			#size-cells = <1>;
177			compatible = "st,stm32mp257-pinctrl";
178			ranges = <0 0x44240000 0xa0400>;
179			pins-are-numbered;
180
181			gpioa: gpio@44240000 {
182				gpio-controller;
183				#gpio-cells = <2>;
184				interrupt-controller;
185				#interrupt-cells = <2>;
186				reg = <0x0 0x400>;
187				clocks = <&rcc CK_BUS_GPIOA>;
188				st,bank-name = "GPIOA";
189				status = "disabled";
190			};
191
192			gpiob: gpio@44250000 {
193				gpio-controller;
194				#gpio-cells = <2>;
195				interrupt-controller;
196				#interrupt-cells = <2>;
197				reg = <0x10000 0x400>;
198				clocks = <&rcc CK_BUS_GPIOB>;
199				st,bank-name = "GPIOB";
200				status = "disabled";
201			};
202
203			gpioc: gpio@44260000 {
204				gpio-controller;
205				#gpio-cells = <2>;
206				interrupt-controller;
207				#interrupt-cells = <2>;
208				reg = <0x20000 0x400>;
209				clocks = <&rcc CK_BUS_GPIOC>;
210				st,bank-name = "GPIOC";
211				status = "disabled";
212			};
213
214			gpiod: gpio@44270000 {
215				gpio-controller;
216				#gpio-cells = <2>;
217				interrupt-controller;
218				#interrupt-cells = <2>;
219				reg = <0x30000 0x400>;
220				clocks = <&rcc CK_BUS_GPIOD>;
221				st,bank-name = "GPIOD";
222				status = "disabled";
223			};
224
225			gpioe: gpio@44280000 {
226				gpio-controller;
227				#gpio-cells = <2>;
228				interrupt-controller;
229				#interrupt-cells = <2>;
230				reg = <0x40000 0x400>;
231				clocks = <&rcc CK_BUS_GPIOE>;
232				st,bank-name = "GPIOE";
233				status = "disabled";
234			};
235
236			gpiof: gpio@44290000 {
237				gpio-controller;
238				#gpio-cells = <2>;
239				interrupt-controller;
240				#interrupt-cells = <2>;
241				reg = <0x50000 0x400>;
242				clocks = <&rcc CK_BUS_GPIOF>;
243				st,bank-name = "GPIOF";
244				status = "disabled";
245			};
246
247			gpiog: gpio@442a0000 {
248				gpio-controller;
249				#gpio-cells = <2>;
250				interrupt-controller;
251				#interrupt-cells = <2>;
252				reg = <0x60000 0x400>;
253				clocks = <&rcc CK_BUS_GPIOG>;
254				st,bank-name = "GPIOG";
255				status = "disabled";
256			};
257
258			gpioh: gpio@442b0000 {
259				gpio-controller;
260				#gpio-cells = <2>;
261				interrupt-controller;
262				#interrupt-cells = <2>;
263				reg = <0x70000 0x400>;
264				clocks = <&rcc CK_BUS_GPIOH>;
265				st,bank-name = "GPIOH";
266				status = "disabled";
267			};
268
269			gpioi: gpio@442c0000 {
270				gpio-controller;
271				#gpio-cells = <2>;
272				interrupt-controller;
273				#interrupt-cells = <2>;
274				reg = <0x80000 0x400>;
275				clocks = <&rcc CK_BUS_GPIOI>;
276				st,bank-name = "GPIOI";
277				status = "disabled";
278			};
279
280			gpioj: gpio@442d0000 {
281				gpio-controller;
282				#gpio-cells = <2>;
283				interrupt-controller;
284				#interrupt-cells = <2>;
285				reg = <0x90000 0x400>;
286				clocks = <&rcc CK_BUS_GPIOJ>;
287				st,bank-name = "GPIOJ";
288				status = "disabled";
289			};
290
291			gpiok: gpio@442e0000 {
292				gpio-controller;
293				#gpio-cells = <2>;
294				interrupt-controller;
295				#interrupt-cells = <2>;
296				reg = <0xa0000 0x400>;
297				clocks = <&rcc CK_BUS_GPIOK>;
298				st,bank-name = "GPIOK";
299				status = "disabled";
300			};
301		};
302
303		pinctrl_z: pinctrl@46200000 {
304			#address-cells = <1>;
305			#size-cells = <1>;
306			compatible = "st,stm32mp257-z-pinctrl";
307			ranges = <0 0x46200000 0x400>;
308			pins-are-numbered;
309
310			gpioz: gpio@46200000 {
311				gpio-controller;
312				#gpio-cells = <2>;
313				interrupt-controller;
314				#interrupt-cells = <2>;
315				reg = <0 0x400>;
316				clocks = <&rcc CK_BUS_GPIOZ>;
317				st,bank-name = "GPIOZ";
318				st,bank-ioport = <11>;
319				status = "disabled";
320			};
321
322		};
323	};
324};
325