1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2/*
3 * ARM Ltd. Fast Models
4 *
5 * Architecture Envelope Model (AEM) ARMv8-A
6 * ARMAEMv8AMPCT
7 *
8 * RTSM_VE_AEMv8A.lisa
9 *
10 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
11 */
12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <services/sdei_flags.h>
15
16#define LEVEL	0
17#define EDGE	2
18#define SDEI_NORMAL	0x70
19#define HIGHEST_SEC	0
20
21#include "rtsm_ve-motherboard.dtsi"
22
23/ {
24	model = "FVP Base";
25	compatible = "arm,fvp-base", "arm,vexpress";
26	interrupt-parent = <&gic>;
27	#address-cells = <2>;
28	#size-cells = <2>;
29
30	chosen {
31		stdout-path = "serial0:115200n8";
32#if (ENABLE_RME == 1)
33		bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
34#endif
35	};
36
37	aliases {
38		serial0 = &v2m_serial0;
39		serial1 = &v2m_serial1;
40		serial2 = &v2m_serial2;
41		serial3 = &v2m_serial3;
42	};
43
44	psci {
45		compatible = "arm,psci-1.0", "arm,psci-0.2";
46		method = "smc";
47		max-pwr-lvl = <2>;
48	};
49
50#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
51	firmware {
52#if SDEI_IN_FCONF
53		sdei {
54			compatible = "arm,sdei-1.0";
55			method = "smc";
56			private_event_count = <3>;
57			shared_event_count = <3>;
58			/*
59			 * Each event descriptor has typically 3 fields:
60			 * 1. Event number
61			 * 2. Interrupt number the event is bound to or
62			 *    if event is dynamic, specified as SDEI_DYN_IRQ
63			 * 3. Bit map of event flags
64			 */
65			private_events =	<1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
66						<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
67						<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
68			shared_events =		<2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
69						<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
70						<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
71		};
72#endif /* SDEI_IN_FCONF */
73
74#if SEC_INT_DESC_IN_FCONF
75		sec_interrupts {
76			compatible = "arm,secure_interrupt_desc";
77			/* Number of G0 and G1 secure interrupts defined by the platform */
78			g0_intr_cnt = <2>;
79			g1s_intr_cnt = <9>;
80			/*
81			 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
82			 * terminology. Each interrupt property descriptor has 3 fields:
83			 * 1. Interrupt number
84			 * 2. Interrupt priority
85			 * 3. Type of interrupt (Edge or Level configured)
86			 */
87			g0_intr_desc =	< 8 SDEI_NORMAL EDGE>,
88					<14 HIGHEST_SEC EDGE>;
89
90			g1s_intr_desc =	< 9 HIGHEST_SEC EDGE>,
91					<10 HIGHEST_SEC EDGE>,
92					<11 HIGHEST_SEC EDGE>,
93					<12 HIGHEST_SEC EDGE>,
94					<13 HIGHEST_SEC EDGE>,
95					<15 HIGHEST_SEC EDGE>,
96					<29 HIGHEST_SEC LEVEL>,
97					<56 HIGHEST_SEC LEVEL>,
98					<57 HIGHEST_SEC LEVEL>;
99		};
100#endif /* SEC_INT_DESC_IN_FCONF */
101	};
102#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
103
104	cpus {
105		#address-cells = <2>;
106		#size-cells = <0>;
107
108		CPU_MAP
109
110		idle-states {
111			entry-method = "psci";
112
113			CPU_SLEEP_0: cpu-sleep-0 {
114				compatible = "arm,idle-state";
115				local-timer-stop;
116				arm,psci-suspend-param = <0x0010000>;
117				entry-latency-us = <40>;
118				exit-latency-us = <100>;
119				min-residency-us = <150>;
120			};
121
122			CLUSTER_SLEEP_0: cluster-sleep-0 {
123				compatible = "arm,idle-state";
124				local-timer-stop;
125				arm,psci-suspend-param = <0x1010000>;
126				entry-latency-us = <500>;
127				exit-latency-us = <1000>;
128				min-residency-us = <2500>;
129			};
130		};
131
132		CPUS
133
134		L2_0: l2-cache0 {
135			compatible = "cache";
136		};
137	};
138
139	memory@80000000 {
140		device_type = "memory";
141#if (ENABLE_RME == 1)
142		reg = <0x00000000 0x80000000 0 0x7C000000>,
143		      <0x00000008 0x80000000 0 0x80000000>;
144#else
145		reg = <0x00000000 0x80000000 0 0x7F000000>,
146		      <0x00000008 0x80000000 0 0x80000000>;
147#endif
148	};
149
150	reserved-memory {
151		#address-cells = <2>;
152		#size-cells = <2>;
153		ranges;
154
155		/* Chipselect 2,00000000 is physically at 0x18000000 */
156		vram: vram@18000000 {
157			/* 8 MB of designated video RAM */
158			compatible = "shared-dma-pool";
159			reg = <0x00000000 0x18000000 0 0x00800000>;
160			no-map;
161		};
162	};
163
164	timer {
165		compatible = "arm,armv8-timer";
166		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
167			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
168			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
169			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
170		clock-frequency = <100000000>;
171	};
172
173	timer@2a810000 {
174			compatible = "arm,armv7-timer-mem";
175			reg = <0x0 0x2a810000 0x0 0x10000>;
176			clock-frequency = <100000000>;
177			#address-cells = <1>;
178			#size-cells = <1>;
179			ranges = <0x0 0x0 0x2a810000 0x100000>;
180
181			frame@2a830000 {
182				frame-number = <1>;
183				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
184				reg = <0x20000 0x10000>;
185			};
186	};
187
188	pmu {
189		compatible = "arm,armv8-pmuv3";
190		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
191	};
192
193	panel {
194		compatible = "arm,rtsm-display";
195		port {
196			panel_in: endpoint {
197				remote-endpoint = <&clcd_pads>;
198			};
199		};
200	};
201
202	bus@8000000 {
203		#interrupt-cells = <1>;
204		interrupt-map-mask = <0 0 63>;
205		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
206				<0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
207				<0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
208				<0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
209				<0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
210				<0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
211				<0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
212				<0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
213				<0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
214				<0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
215				<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
216				<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
217				<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
218				<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
219				<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
220				<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
221				<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
222				<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
223				<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
224				<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
225				<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
226				<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
227				<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
228				<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
229				<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
230				<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
231				<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
232				<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
233				<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
234				<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
235				<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
236				<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
237				<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
238				<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
239				<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
240				<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
241				<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
242				<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
243				<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
244				<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
245				<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
246				<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
247				<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
248				<0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
249				<0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
250				<0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
251	};
252};
253