1 /*
2 * Copyright 2018-2021 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <plat_tzc380.h>
9
10 #pragma weak populate_tzc380_reg_list
11
12 #ifdef DEFAULT_TZASC_CONFIG
13 /*
14 * Typical Memory map of DRAM0
15 * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
16 * | |
17 * | |
18 * | Non-SECURE REGION |
19 * | |
20 * | |
21 * | |
22 * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
23 * |-----------------NXP_SECURE_DRAM_ADDR--------------------|
24 * | |
25 * | |
26 * | |
27 * | SECURE REGION (= 64MB) |
28 * | |
29 * | |
30 * | |
31 * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
32 * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
33 * | |
34 * | Secure EL1 Payload SHARED REGION (= 2MB) |
35 * | |
36 * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
37 *
38 *
39 *
40 * Typical Memory map of DRAM1
41 * |---------------------NXP_DRAM1_ADDR----------------------|
42 * | |
43 * | |
44 * | Non-SECURE REGION |
45 * | |
46 * | |
47 * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
48 *
49 *
50 * Typical Memory map of DRAM2
51 * |---------------------NXP_DRAM2_ADDR----------------------|
52 * | |
53 * | |
54 * | Non-SECURE REGION |
55 * | |
56 * | |
57 * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
58 */
59
60 /*****************************************************************************
61 * This function sets up access permissions on memory regions
62 *
63 * Input:
64 * tzc380_reg_list : TZC380 Region List
65 * dram_idx : DRAM index
66 * list_idx : TZC380 Region List Index
67 * dram_start_addr : Start address of DRAM at dram_idx.
68 * dram_size : Size of DRAM at dram_idx.
69 * secure_dram_sz : Secure DRAM Size
70 * shrd_dram_sz : Shared DRAM Size
71 *
72 * Out:
73 * list_idx : last populated index + 1
74 *
75 ****************************************************************************/
populate_tzc380_reg_list(struct tzc380_reg * tzc380_reg_list,int dram_idx,int list_idx,uint64_t dram_start_addr,uint64_t dram_size,uint32_t secure_dram_sz,uint32_t shrd_dram_sz)76 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
77 int dram_idx, int list_idx,
78 uint64_t dram_start_addr,
79 uint64_t dram_size,
80 uint32_t secure_dram_sz,
81 uint32_t shrd_dram_sz)
82 {
83 /* Region 0: Default region marked as Non-Secure */
84 if (list_idx == 0) {
85 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
86 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
87 tzc380_reg_list[list_idx].addr = UL(0x0);
88 tzc380_reg_list[list_idx].size = 0x0;
89 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
90 list_idx++;
91 }
92 /* Continue with list entries for index > 0 */
93 if (dram_idx == 0) {
94 /*
95 * Region 1: Secure Region on DRAM 1 for 2MB out of 2MB,
96 * excluding 0 sub-region(=256KB).
97 */
98 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
99 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
100 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
101 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_2M;
102 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
103 list_idx++;
104
105 /*
106 * Region 2: Secure Region on DRAM 1 for 54MB out of 64MB,
107 * excluding 1 sub-rgion(=8MB) of 8MB.
108 */
109 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
110 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
111 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + shrd_dram_sz;
112 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_64M;
113 tzc380_reg_list[list_idx].sub_mask = 0x80; /* Disable sub-region 7 */
114 list_idx++;
115
116 /*
117 * Region 3: Secure Region on DRAM 1 for 6MB out of 8MB,
118 * excluding 2 sub-rgion(=1MB) of 2MB.
119 */
120 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
121 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
122 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
123 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_8M;
124 tzc380_reg_list[list_idx].sub_mask = 0xC0; /* Disable sub-region 6 & 7 */
125 list_idx++;
126
127 }
128
129 return list_idx;
130 }
131 #else
populate_tzc380_reg_list(struct tzc380_reg * tzc380_reg_list,int dram_idx,int list_idx,uint64_t dram_start_addr,uint64_t dram_size,uint32_t secure_dram_sz,uint32_t shrd_dram_sz)132 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
133 int dram_idx, int list_idx,
134 uint64_t dram_start_addr,
135 uint64_t dram_size,
136 uint32_t secure_dram_sz,
137 uint32_t shrd_dram_sz)
138 {
139 ERROR("tzc380_reg_list used is not a default list\n");
140 ERROR("%s needs to be over-written.\n", __func__);
141 return 0;
142 }
143 #endif /* DEFAULT_TZASC_CONFIG */
144
145
mem_access_setup(uintptr_t base,uint32_t total_regions,struct tzc380_reg * tzc380_reg_list)146 void mem_access_setup(uintptr_t base, uint32_t total_regions,
147 struct tzc380_reg *tzc380_reg_list)
148 {
149 uint32_t indx = 0;
150 unsigned int attr_value;
151
152 VERBOSE("Configuring TrustZone Controller tzc380\n");
153
154 tzc380_init(base);
155
156 tzc380_set_action(TZC_ACTION_NONE);
157
158 for (indx = 0; indx < total_regions; indx++) {
159 attr_value = tzc380_reg_list[indx].secure |
160 TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) |
161 TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) |
162 tzc380_reg_list[indx].enabled;
163
164 tzc380_configure_region(indx, tzc380_reg_list[indx].addr,
165 attr_value);
166 }
167
168 tzc380_set_action(TZC_ACTION_ERR);
169 }
170