1 /*
2 * Copyright (c) 2016 - 2020, Broadcom
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <inttypes.h>
8 #include <stddef.h>
9 #include <stdint.h>
10 #include <stdlib.h>
11 #include <string.h>
12
13 #include <arch_helpers.h>
14 #include <lib/mmio.h>
15
16 #include "bcm_emmc.h"
17 #include "emmc_chal_types.h"
18 #include "emmc_csl_sdprot.h"
19 #include "emmc_chal_sd.h"
20 #include "emmc_csl_sdcmd.h"
21 #include "emmc_csl_sd.h"
22 #include "emmc_pboot_hal_memory_drv.h"
23
24 #define SD_CARD_BUSY 0x80000000
25 #define SD_CARD_RETRY_LIMIT 1000
26 #define SD_CARD_HIGH_SPEED_PS 13
27 #define SD_CHK_HIGH_SPEED_MODE 0x00FFFFF1
28 #define SD_SET_HIGH_SPEED_MODE 0x80FFFFF1
29 #define SD_MMC_ENABLE_HIGH_SPEED 0x03b90100 //0x03b90103
30 #define SD_MMC_8BIT_MODE 0x03b70200
31 #define SD_MMC_4BIT_MODE 0x03b70100
32 #define SD_MMC_1BIT_MODE 0x03b70000
33
34 #define SD_MMC_BOOT_8BIT_MODE 0x03b10200
35 #define SD_MMC_BOOT_4BIT_MODE 0x03b10100
36 #define SD_MMC_BOOT_1BIT_MODE 0x03b10000
37 #define SDIO_HW_EMMC_EXT_CSD_BOOT_CNF 0X03B30000
38
39 #ifdef USE_EMMC_FIP_TOC_CACHE
40 /*
41 * Cache size mirrors the size of the global eMMC temp buffer
42 * which is used for non-image body reads such as headers, ToC etc.
43 */
44 #define CACHE_SIZE ((EMMC_BLOCK_SIZE) * 2)
45 #define PARTITION_BLOCK_ADDR ((PLAT_FIP_ATTEMPT_OFFSET)/(EMMC_BLOCK_SIZE))
46
47 static uint32_t cached_partition_block;
48 static uint8_t cached_block[CACHE_SIZE];
49 #endif
50
51 static int set_card_data_width(struct sd_handle *handle, int width);
52 static int abort_err(struct sd_handle *handle);
53 static int err_recovery(struct sd_handle *handle, uint32_t errors);
54 static int xfer_data(struct sd_handle *handle, uint32_t mode, uint32_t addr,
55 uint32_t length, uint8_t *base);
56
set_boot_config(struct sd_handle * handle,uint32_t config)57 int set_boot_config(struct sd_handle *handle, uint32_t config)
58 {
59 return mmc_cmd6(handle, SDIO_HW_EMMC_EXT_CSD_BOOT_CNF | config);
60 }
61
process_csd_mmc_speed(struct sd_handle * handle,uint32_t csd_mmc_speed)62 void process_csd_mmc_speed(struct sd_handle *handle, uint32_t csd_mmc_speed)
63 {
64 uint32_t div_ctrl_setting;
65
66 /* CSD field TRAN_SPEED:
67 * Bits [2:0] 0 = 100 KHz
68 * 1 = 1 MHz
69 * 2 = 10 MHz
70 * 3 = 100 MHz
71 * 4...7 Reserved.
72 * Bits [6:3] 0 = Reserved
73 * 1 = 1.0
74 * 2 = 1.2
75 * 3 = 1.3
76 * 4 = 1.5
77 * 5 = 2.0
78 * 6 = 2.6
79 * 7 = 3.0
80 * 8 = 3.5
81 * 9 = 4.0
82 * A = 4.5
83 * B = 5.2
84 * C = 5.5
85 * D = 6.0
86 * E = 7.0
87 * F = 8.0
88 * For cards supporting version 4.0, 4.1, and 4.2 of the standard,
89 * the value shall be 20 MHz (0x2A).
90 * For cards supporting version 4.3 , the value shall be 26 MHz (0x32)
91 */
92
93 switch (csd_mmc_speed & 0x7F) {
94 case 0x2A:
95 EMMC_TRACE("Speeding up eMMC clock to 20MHz\n");
96 div_ctrl_setting =
97 chal_sd_freq_2_div_ctrl_setting(20 * 1000 * 1000);
98 break;
99 case 0x32:
100 EMMC_TRACE("Speeding up eMMC clock to 26MHz\n");
101 div_ctrl_setting =
102 chal_sd_freq_2_div_ctrl_setting(26 * 1000 * 1000);
103 break;
104 default:
105 /* Unknown */
106 return;
107 }
108
109 chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 0);
110
111 chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 1);
112
113 SD_US_DELAY(1000);
114 }
115
116
117 /*
118 * The function changes SD/SDIO/MMC card data width if
119 * the card support configurable data width. The host controller
120 * and the card has to be in the same bus data width.
121 */
set_card_data_width(struct sd_handle * handle,int width)122 int set_card_data_width(struct sd_handle *handle, int width)
123 {
124 uint32_t data_width = 0;
125 int is_valid_arg = 1;
126 int rc = SD_FAIL;
127 char *bitwidth_str = " ";
128 char *result_str = "failed";
129
130 switch (width) {
131 #ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
132 case SD_BUS_DATA_WIDTH_8BIT:
133 data_width = SD_MMC_8BIT_MODE;
134 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
135 bitwidth_str = "8_BIT";
136 #endif
137 break;
138 #endif
139 case SD_BUS_DATA_WIDTH_4BIT:
140 data_width = SD_MMC_4BIT_MODE;
141 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
142 bitwidth_str = "4_BIT";
143 #endif
144 break;
145
146 case SD_BUS_DATA_WIDTH_1BIT:
147 data_width = SD_MMC_1BIT_MODE;
148 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
149 bitwidth_str = "1_BIT";
150 #endif
151 break;
152
153 default:
154 is_valid_arg = 0;
155 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
156 bitwidth_str = "unknown";
157 #endif
158 break;
159 }
160
161 if (is_valid_arg) {
162 rc = mmc_cmd6(handle, data_width);
163 if (rc == SD_OK) {
164 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
165 result_str = "succeeded";
166 #endif
167 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
168 width);
169 } else {
170 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
171 result_str = "failed";
172 #endif
173 }
174 } else {
175 rc = SD_FAIL;
176 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
177 result_str = "ignored";
178 #endif
179 }
180
181 VERBOSE("SDIO Data Width(%s) %s.\n", bitwidth_str, result_str);
182
183 return rc;
184 }
185
186
187 /*
188 * Error handling routine. Does abort data
189 * transmission if error is found.
190 */
abort_err(struct sd_handle * handle)191 static int abort_err(struct sd_handle *handle)
192 {
193 uint32_t present, options, event, rel = 0;
194 struct sd_resp cmdRsp;
195
196 handle->device->ctrl.argReg = 0;
197 handle->device->ctrl.cmdIndex = SD_CMD_STOP_TRANSMISSION;
198
199 options = (SD_CMD_STOP_TRANSMISSION << 24) |
200 (SD_CMDR_RSP_TYPE_R1b_5b << SD_CMDR_RSP_TYPE_S) |
201 SD4_EMMC_TOP_CMD_CRC_EN_MASK |
202 SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
203
204 chal_sd_send_cmd((CHAL_HANDLE *) handle->device,
205 handle->device->ctrl.cmdIndex,
206 handle->device->ctrl.argReg, options);
207
208 event = wait_for_event(handle,
209 SD4_EMMC_TOP_INTR_CMDDONE_MASK |
210 SD_ERR_INTERRUPTS,
211 handle->device->cfg.wfe_retry);
212
213 if (event & SD_CMD_ERROR_INT) {
214 rel = SD_ERROR_NON_RECOVERABLE;
215 } else {
216 if (event & SD_DAT_TIMEOUT) {
217 return SD_ERROR_NON_RECOVERABLE;
218 }
219
220 chal_sd_get_response((CHAL_HANDLE *) handle->device,
221 (uint32_t *)&cmdRsp);
222
223 process_cmd_response(handle, handle->device->ctrl.cmdIndex,
224 cmdRsp.data.r2.rsp1, cmdRsp.data.r2.rsp2,
225 cmdRsp.data.r2.rsp3, cmdRsp.data.r2.rsp4,
226 &cmdRsp);
227
228 SD_US_DELAY(2000);
229
230 present =
231 chal_sd_get_present_status((CHAL_HANDLE *) handle->device);
232
233 if ((present & 0x00F00000) == 0x00F00000)
234 rel = SD_ERROR_RECOVERABLE;
235 else
236 rel = SD_ERROR_NON_RECOVERABLE;
237 }
238
239 return rel;
240 }
241
242
243 /*
244 * The function handles real data transmission on both DMA and
245 * none DMA mode, In None DMA mode the data transfer starts
246 * when the command is sent to the card, data has to be written
247 * into the host controllers buffer at this time one block
248 * at a time.
249 * In DMA mode, the real data transfer is done by the DMA engine
250 * and this functions just waits for the data transfer to complete.
251 *
252 */
process_data_xfer(struct sd_handle * handle,uint8_t * buffer,uint32_t addr,uint32_t length,int dir)253 int process_data_xfer(struct sd_handle *handle, uint8_t *buffer, uint32_t addr,
254 uint32_t length, int dir)
255 {
256 if (dir == SD_XFER_HOST_TO_CARD) {
257 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
258 if (handle->device->cfg.dma == SD_DMA_OFF) {
259 /*
260 * In NON DMA mode, the real data xfer starts from here
261 */
262 if (write_buffer(handle, length, buffer))
263 return SD_WRITE_ERROR;
264 } else {
265 wait_for_event(handle,
266 SD4_EMMC_TOP_INTR_TXDONE_MASK |
267 SD_ERR_INTERRUPTS,
268 handle->device->cfg.wfe_retry);
269
270 if (handle->device->ctrl.cmdStatus == SD_OK)
271 return SD_OK;
272
273 check_error(handle, handle->device->ctrl.cmdStatus);
274 return SD_WRITE_ERROR;
275 }
276 #else
277 return SD_WRITE_ERROR;
278 #endif
279 } else { /* SD_XFER_CARD_TO_HOST */
280
281 if (handle->device->cfg.dma == SD_DMA_OFF) {
282 /* In NON DMA mode, the real data
283 * transfer starts from here
284 */
285 if (read_buffer(handle, length, buffer))
286 return SD_READ_ERROR;
287
288 } else { /* for DMA mode */
289
290 /*
291 * once the data transmission is done
292 * copy data to the host buffer.
293 */
294 wait_for_event(handle,
295 SD4_EMMC_TOP_INTR_TXDONE_MASK |
296 SD_ERR_INTERRUPTS,
297 handle->device->cfg.wfe_retry);
298
299 if (handle->device->ctrl.cmdStatus == SD_OK)
300 return SD_OK;
301
302 check_error(handle, handle->device->ctrl.cmdStatus);
303 return SD_READ_ERROR;
304 }
305 }
306 return SD_OK;
307 }
308
309
310 /*
311 * The function sets block size for the next SD/SDIO/MMC
312 * card read/write command.
313 */
select_blk_sz(struct sd_handle * handle,uint16_t size)314 int select_blk_sz(struct sd_handle *handle, uint16_t size)
315 {
316 return sd_cmd16(handle, size);
317 }
318
319
320 /*
321 * The function initializes the SD/SDIO/MMC/CEATA and detects
322 * the card according to the flag of detection.
323 * Once this function is called, the card is put into ready state
324 * so application can do data transfer to and from the card.
325 */
init_card(struct sd_handle * handle,int detection)326 int init_card(struct sd_handle *handle, int detection)
327 {
328 /*
329 * After Reset, eMMC comes up in 1 Bit Data Width by default.
330 * Set host side to match.
331 */
332 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
333 SD_BUS_DATA_WIDTH_1BIT);
334
335 #ifdef USE_EMMC_FIP_TOC_CACHE
336 cached_partition_block = 0;
337 #endif
338 handle->device->ctrl.present = 0; /* init card present to be no card */
339
340 init_mmc_card(handle);
341
342 handle->device->ctrl.present = 1; /* card is detected */
343
344 /* switch the data width back */
345 if (handle->card->type != SD_CARD_MMC)
346 return SD_FAIL;
347
348 /*
349 * Dynamically set Data Width to highest supported value.
350 * Try different data width settings (highest to lowest).
351 * Verify each setting by reading EXT_CSD and comparing
352 * against the EXT_CSD contents previously read in call to
353 * init_mmc_card() earlier. Stop at first verified data width
354 * setting.
355 */
356 {
357 #define EXT_CSD_PROPERTIES_SECTION_START_INDEX 192
358 #define EXT_CSD_PROPERTIES_SECTION_END_INDEX 511
359 uint8_t buffer[EXT_CSD_SIZE];
360 #ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
361 /* Try 8 Bit Data Width */
362 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
363 SD_BUS_DATA_WIDTH_8BIT);
364 if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_8BIT)) &&
365 (!mmc_cmd8(handle, buffer)) &&
366 (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
367 &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
368 EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
369
370 return SD_OK;
371 #endif
372 /* Fall back to 4 Bit Data Width */
373 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
374 SD_BUS_DATA_WIDTH_4BIT);
375 if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_4BIT)) &&
376 (!mmc_cmd8(handle, buffer)) &&
377 (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
378 &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
379 EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
380
381 return SD_OK;
382
383 /* Fall back to 1 Bit Data Width */
384 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
385 SD_BUS_DATA_WIDTH_1BIT);
386 /* Just use 1 Bit Data Width then. */
387 if (!set_card_data_width(handle, SD_BUS_DATA_WIDTH_1BIT))
388 return SD_OK;
389
390 }
391 return SD_CARD_INIT_ERROR;
392 }
393
394
395 /*
396 * The function handles MMC/CEATA card initialization.
397 */
init_mmc_card(struct sd_handle * handle)398 int init_mmc_card(struct sd_handle *handle)
399 {
400 uint32_t ocr = 0, newOcr, rc, limit = 0;
401 uint32_t cmd1_option = 0x40300000;
402 uint32_t sec_count;
403
404 handle->card->type = SD_CARD_MMC;
405
406 do {
407 SD_US_DELAY(1000);
408 newOcr = 0;
409 ocr = 0;
410 rc = sd_cmd1(handle, cmd1_option, &newOcr);
411 limit++;
412
413 if (rc == SD_OK)
414 ocr = newOcr;
415
416 } while (((ocr & SD_CARD_BUSY) == 0) && (limit < SD_CARD_RETRY_LIMIT));
417
418 if (limit >= SD_CARD_RETRY_LIMIT) {
419 handle->card->type = SD_CARD_UNKNOWN;
420 EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
421 return SD_CARD_UNKNOWN;
422 }
423
424 /* Save the ocr register */
425 handle->device->ctrl.ocr = ocr;
426
427 /* Ready State */
428 rc = sd_cmd2(handle);
429 if (rc != SD_OK) {
430 handle->card->type = SD_CARD_UNKNOWN;
431 return SD_CARD_UNKNOWN;
432 }
433
434 rc = sd_cmd3(handle);
435 if (rc != SD_OK) {
436 handle->card->type = SD_CARD_UNKNOWN;
437 return SD_CARD_UNKNOWN;
438 }
439 /* read CSD */
440 rc = sd_cmd9(handle, &emmc_global_vars_ptr->cardData);
441 if (rc != SD_OK) {
442 handle->card->type = SD_CARD_UNKNOWN;
443 return SD_CARD_UNKNOWN;
444 }
445
446 /* Increase clock frequency according to what the card advertises */
447 EMMC_TRACE("From CSD... cardData.csd.mmc.speed = 0x%X\n",
448 emmc_global_vars_ptr->cardData.csd.mmc.speed);
449 process_csd_mmc_speed(handle,
450 emmc_global_vars_ptr->cardData.csd.mmc.speed);
451
452 /* goto transfer mode */
453 rc = sd_cmd7(handle, handle->device->ctrl.rca);
454 if (rc != SD_OK) {
455 handle->card->type = SD_CARD_UNKNOWN;
456 return SD_CARD_UNKNOWN;
457 }
458
459 rc = mmc_cmd8(handle, emmc_global_buf_ptr->u.Ext_CSD_storage);
460 if (rc == SD_OK) {
461 /* calcul real capacity */
462 sec_count = emmc_global_buf_ptr->u.Ext_CSD_storage[212] |
463 emmc_global_buf_ptr->u.Ext_CSD_storage[213] << 8 |
464 emmc_global_buf_ptr->u.Ext_CSD_storage[214] << 16 |
465 emmc_global_buf_ptr->u.Ext_CSD_storage[215] << 24;
466
467 EMMC_TRACE("Device density = %ldMBytes\n",
468 handle->card->size / (1024 * 1024));
469
470 if (sec_count > 0) {
471 handle->card->size = (uint64_t)sec_count * 512;
472
473 EMMC_TRACE("Updated Device density = %ldMBytes\n",
474 handle->card->size / (1024 * 1024));
475 }
476
477 if (sec_count > (2u * 1024 * 1024 * 1024) / 512) {
478 handle->device->ctrl.ocr |= SD_CARD_HIGH_CAPACITY;
479 handle->device->cfg.blockSize = 512;
480 }
481
482 if (handle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
483 EMMC_TRACE("Sector addressing\n");
484 } else {
485 EMMC_TRACE("Byte addressing\n");
486 }
487
488 EMMC_TRACE("Ext_CSD_storage[162]: 0x%02X Ext_CSD_storage[179]: 0x%02X\n",
489 emmc_global_buf_ptr->u.Ext_CSD_storage[162],
490 emmc_global_buf_ptr->u.Ext_CSD_storage[179]);
491 }
492
493 return handle->card->type;
494 }
495
496
497 /*
498 * The function send reset command to the card.
499 * The card will be in ready status after the reset.
500 */
reset_card(struct sd_handle * handle)501 int reset_card(struct sd_handle *handle)
502 {
503 int res = SD_OK;
504
505 /* on reset, card's RCA should return to 0 */
506 handle->device->ctrl.rca = 0;
507
508 res = sd_cmd0(handle);
509
510 if (res != SD_OK)
511 return SD_RESET_ERROR;
512
513 return res;
514 }
515
516
517 /*
518 * The function sends command to the card and starts
519 * data transmission.
520 */
xfer_data(struct sd_handle * handle,uint32_t mode,uint32_t addr,uint32_t length,uint8_t * base)521 static int xfer_data(struct sd_handle *handle,
522 uint32_t mode,
523 uint32_t addr, uint32_t length, uint8_t *base)
524 {
525 int rc = SD_OK;
526
527 VERBOSE("XFER: dest: 0x%" PRIx64 ", addr: 0x%x, size: 0x%x bytes\n",
528 (uint64_t)base, addr, length);
529
530 if ((length / handle->device->cfg.blockSize) > 1) {
531 if (mode == SD_OP_READ) {
532 inv_dcache_range((uintptr_t)base, (uint64_t)length);
533 rc = sd_cmd18(handle, addr, length, base);
534 } else {
535 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
536 flush_dcache_range((uintptr_t)base, (uint64_t)length);
537 rc = sd_cmd25(handle, addr, length, base);
538 #else
539 rc = SD_DATA_XFER_ERROR;
540 #endif
541 }
542 } else {
543 if (mode == SD_OP_READ) {
544 inv_dcache_range((uintptr_t)base, (uint64_t)length);
545 rc = sd_cmd17(handle, addr,
546 handle->device->cfg.blockSize, base);
547 } else {
548 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
549 flush_dcache_range((uintptr_t)base, (uint64_t)length);
550 rc = sd_cmd24(handle, addr,
551 handle->device->cfg.blockSize, base);
552 #else
553 rc = SD_DATA_XFER_ERROR;
554 #endif
555 }
556 }
557
558 if (rc != SD_OK)
559 return SD_DATA_XFER_ERROR;
560
561 return SD_OK;
562 }
563
564 #ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
erase_card(struct sd_handle * handle,uint32_t addr,uint32_t blocks)565 int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks)
566 {
567 uint32_t end_addr;
568
569 INFO("ERASE: addr: 0x%x, num of sectors: 0x%x\n", addr, blocks);
570
571 if (sd_cmd35(handle, addr) != SD_OK)
572 return SD_FAIL;
573
574 end_addr = addr + blocks - 1;
575 if (sd_cmd36(handle, end_addr) != SD_OK)
576 return SD_FAIL;
577
578 if (sd_cmd38(handle) != SD_OK)
579 return SD_FAIL;
580
581 return SD_OK;
582 }
583 #endif
584
585 /*
586 * The function reads block data from a card.
587 */
588 #ifdef USE_EMMC_FIP_TOC_CACHE
read_block(struct sd_handle * handle,uint8_t * dst,uint32_t addr,uint32_t len)589 int read_block(struct sd_handle *handle,
590 uint8_t *dst, uint32_t addr, uint32_t len)
591 {
592 int rel = SD_OK;
593
594 /*
595 * Avoid doing repeated reads of the partition block
596 * by caching.
597 */
598 if (cached_partition_block &&
599 addr == PARTITION_BLOCK_ADDR &&
600 len == CACHE_SIZE) {
601 memcpy(dst, cached_block, len);
602 } else {
603 rel = xfer_data(handle, SD_OP_READ, addr, len, dst);
604
605 if (len == CACHE_SIZE && addr == PARTITION_BLOCK_ADDR) {
606 cached_partition_block = 1;
607 memcpy(cached_block, dst, len);
608 }
609 }
610
611 return rel;
612 }
613 #else
read_block(struct sd_handle * handle,uint8_t * dst,uint32_t addr,uint32_t len)614 int read_block(struct sd_handle *handle,
615 uint8_t *dst, uint32_t addr, uint32_t len)
616 {
617 return xfer_data(handle, SD_OP_READ, addr, len, dst);
618 }
619 #endif
620
621 #ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
622
623 /*
624 * The function writes block data to a card.
625 */
write_block(struct sd_handle * handle,uint8_t * src,uint32_t addr,uint32_t len)626 int write_block(struct sd_handle *handle,
627 uint8_t *src, uint32_t addr, uint32_t len)
628 {
629 int rel = SD_OK;
630
631 /*
632 * Current HC has problem to get response of cmd16 after cmd12,
633 * the delay is necessary to sure the next cmd16 will not be timed out.
634 * The delay has to be at least 4 ms.
635 * The code removed cmd16 and use cmd13 to get card status before
636 * sending cmd18 or cmd25 to make sure the card is ready and thus
637 * no need to have delay here.
638 */
639
640 rel = xfer_data(handle, SD_OP_WRITE, addr, len, src);
641
642 EMMC_TRACE("wr_blk addr:0x%08X src:0x%08X len:0x%08X result:%d\n",
643 addr, src, len, rel);
644
645 return rel;
646 }
647
648
649 /*
650 * The function is called to write one block data directly to
651 * a card's data buffer.
652 * it is used in Non-DMA mode for card data transmission.
653 */
write_buffer(struct sd_handle * handle,uint32_t length,uint8_t * data)654 int write_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
655 {
656 uint32_t rem, blockSize, event;
657 uint8_t *pData = data;
658
659 blockSize = handle->device->cfg.blockSize;
660 rem = length;
661
662 if (rem == 0)
663 return SD_OK;
664
665 while (rem > 0) {
666
667 event = wait_for_event(handle,
668 SD4_EMMC_TOP_INTR_BWRDY_MASK |
669 SD_ERR_INTERRUPTS,
670 handle->device->cfg.wfe_retry);
671
672 if (handle->device->ctrl.cmdStatus) {
673 check_error(handle, handle->device->ctrl.cmdStatus);
674 return SD_WRITE_ERROR;
675 }
676
677 if (rem >= blockSize)
678 chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
679 blockSize, pData);
680 else
681 chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
682 rem, pData);
683
684 if (rem > blockSize) {
685 rem -= blockSize;
686 pData += blockSize;
687 } else {
688 pData += rem;
689 rem = 0;
690 }
691 }
692
693 if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
694 SD4_EMMC_TOP_INTR_TXDONE_MASK) {
695 event = wait_for_event(handle,
696 SD4_EMMC_TOP_INTR_TXDONE_MASK |
697 SD_ERR_INTERRUPTS,
698 handle->device->cfg.wfe_retry);
699
700 if (handle->device->ctrl.cmdStatus != SD_OK) {
701 check_error(handle, handle->device->ctrl.cmdStatus);
702 return SD_WRITE_ERROR;
703 }
704 } else {
705 handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
706 }
707
708 return SD_OK;
709 }
710 #endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */
711
712
713 /*
714 * The function is called to read maximal one block data
715 * directly from a card
716 * It is used in Non-DMA mode for card data transmission.
717 */
read_buffer(struct sd_handle * handle,uint32_t length,uint8_t * data)718 int read_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
719 {
720 uint32_t rem, blockSize, event = 0;
721 uint8_t *pData = data;
722
723 blockSize = handle->device->cfg.blockSize;
724 rem = length;
725
726 if (rem == 0)
727 return SD_OK;
728
729 while (rem > 0) {
730 event = wait_for_event(handle,
731 SD4_EMMC_TOP_INTR_BRRDY_MASK |
732 SD_ERR_INTERRUPTS,
733 handle->device->cfg.wfe_retry);
734
735 if (handle->device->ctrl.cmdStatus) {
736 check_error(handle, handle->device->ctrl.cmdStatus);
737 return SD_READ_ERROR;
738 }
739
740 if (rem >= blockSize)
741 chal_sd_read_buffer((CHAL_HANDLE *) handle->device,
742 blockSize, pData);
743 else
744 chal_sd_read_buffer((CHAL_HANDLE *) handle->device, rem,
745 pData);
746
747 if (rem > blockSize) {
748 rem -= blockSize;
749 pData += blockSize;
750 } else {
751 pData += rem;
752 rem = 0;
753 }
754 }
755
756 /* In case, there are extra data in the SD FIFO, just dump them. */
757 chal_sd_dump_fifo((CHAL_HANDLE *) handle->device);
758
759 if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
760 SD4_EMMC_TOP_INTR_TXDONE_MASK) {
761 event = wait_for_event(handle, SD4_EMMC_TOP_INTR_TXDONE_MASK,
762 handle->device->cfg.wfe_retry);
763
764 if (handle->device->ctrl.cmdStatus) {
765 check_error(handle, handle->device->ctrl.cmdStatus);
766 return SD_READ_ERROR;
767 }
768 } else {
769 handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
770 }
771
772 return SD_OK;
773 }
774
775
776 /*
777 * Error handling routine.
778 * The function just reset the DAT
779 * and CMD line if an error occures during data transmission.
780 */
check_error(struct sd_handle * handle,uint32_t ints)781 int check_error(struct sd_handle *handle, uint32_t ints)
782 {
783 uint32_t rel;
784
785 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
786 SD_ERR_INTERRUPTS, 0);
787
788 if (ints & SD4_EMMC_TOP_INTR_CMDERROR_MASK) {
789
790 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
791 SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
792 rel = abort_err(handle);
793
794 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
795 SD4_EMMC_TOP_CTRL1_DATRST_MASK);
796 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
797 SD_ERR_INTERRUPTS, 1);
798
799 return (rel == SD_ERROR_NON_RECOVERABLE) ?
800 SD_ERROR_NON_RECOVERABLE : SD_ERROR_RECOVERABLE;
801 } else {
802 rel = err_recovery(handle, ints);
803 }
804
805 chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
806 SD_ERR_INTERRUPTS, 1);
807
808 return rel;
809 }
810
811
812 /*
813 * Error recovery routine.
814 * Try to recover from the error.
815 */
err_recovery(struct sd_handle * handle,uint32_t errors)816 static int err_recovery(struct sd_handle *handle, uint32_t errors)
817 {
818 uint32_t rel = 0;
819
820 /*
821 * In case of timeout error, the cmd line and data line maybe
822 * still active or stuck at atcitve so it is needed to reset
823 * either data line or cmd line to make sure a new cmd can be sent.
824 */
825
826 if (errors & SD_CMD_ERROR_INT)
827 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
828 SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
829
830 if (errors & SD_DAT_ERROR_INT)
831 chal_sd_reset_line((CHAL_HANDLE *) handle->device,
832 SD4_EMMC_TOP_CTRL1_DATRST_MASK);
833
834 /* Abort transaction by sending out stop command */
835 if ((handle->device->ctrl.cmdIndex == 18) ||
836 (handle->device->ctrl.cmdIndex == 25))
837 rel = abort_err(handle);
838
839 return rel;
840 }
841
842
843 /*
844 * The function is called to read one block data directly from a card.
845 * It is used in Non-DMA mode for card data transmission.
846 */
process_cmd_response(struct sd_handle * handle,uint32_t cmdIndex,uint32_t rsp0,uint32_t rsp1,uint32_t rsp2,uint32_t rsp3,struct sd_resp * resp)847 int process_cmd_response(struct sd_handle *handle,
848 uint32_t cmdIndex,
849 uint32_t rsp0,
850 uint32_t rsp1,
851 uint32_t rsp2, uint32_t rsp3, struct sd_resp *resp)
852 {
853 int result = SD_OK;
854
855 /* R6 */
856 uint32_t rca = (rsp0 >> 16) & 0xffff;
857 uint32_t cardStatus = rsp0;
858
859 /* R4 */
860 uint32_t cBit = (rsp0 >> 31) & 0x1;
861 uint32_t funcs = (rsp0 >> 28) & 0x7;
862 uint32_t memPresent = (rsp0 >> 27) & 0x1;
863
864 resp->r1 = 0x3f;
865 resp->cardStatus = cardStatus;
866
867 if (cmdIndex == SD_CMD_IO_SEND_OP_COND) {
868 resp->data.r4.cardReady = cBit;
869 resp->data.r4.funcs = funcs;
870 resp->data.r4.memPresent = memPresent;
871 resp->data.r4.ocr = cardStatus;
872 }
873
874 if (cmdIndex == SD_CMD_MMC_SET_RCA) {
875 resp->data.r6.rca = rca;
876 resp->data.r6.cardStatus = cardStatus & 0xFFFF;
877 }
878
879 if (cmdIndex == SD_CMD_SELECT_DESELECT_CARD) {
880 resp->data.r7.rca = rca;
881 }
882
883 if (cmdIndex == SD_CMD_IO_RW_DIRECT) {
884 if (((rsp0 >> 16) & 0xffff) != 0)
885 result = SD_CMD_ERR_INVALID_RESPONSE;
886
887 resp->data.r5.data = rsp0 & 0xff;
888 }
889
890 if (cmdIndex == SD_CMD_IO_RW_EXTENDED) {
891 if (((rsp0 >> 16) & 0xffff) != 0)
892 result = SD_CMD_ERR_INVALID_RESPONSE;
893
894 resp->data.r5.data = rsp0 & 0xff;
895 }
896
897 if (cmdIndex == SD_ACMD_SD_SEND_OP_COND ||
898 cmdIndex == SD_CMD_SEND_OPCOND)
899 resp->data.r3.ocr = cardStatus;
900
901 if (cmdIndex == SD_CMD_SEND_CSD ||
902 cmdIndex == SD_CMD_SEND_CID ||
903 cmdIndex == SD_CMD_ALL_SEND_CID) {
904 resp->data.r2.rsp4 = rsp3;
905 resp->data.r2.rsp3 = rsp2;
906 resp->data.r2.rsp2 = rsp1;
907 resp->data.r2.rsp1 = rsp0;
908 }
909
910 if ((cmdIndex == SD_CMD_READ_EXT_CSD) &&
911 (handle->card->type == SD_CARD_SD)) {
912 if ((resp->cardStatus & 0xAA) != 0xAA) {
913 result = SD_CMD_ERR_INVALID_RESPONSE;
914 }
915 }
916
917 return result;
918 }
919
920
921 /*
922 * The function sets DMA buffer and data length, process
923 * block size and the number of blocks to be transferred.
924 * It returns the DMA buffer address.
925 * It copies dma data from user buffer to the DMA buffer
926 * if the operation is to write data to the SD card.
927 */
data_xfer_setup(struct sd_handle * handle,uint8_t * data,uint32_t length,int dir)928 void data_xfer_setup(struct sd_handle *handle, uint8_t *data, uint32_t length,
929 int dir)
930 {
931 chal_sd_setup_xfer((CHAL_HANDLE *)handle->device, data, length, dir);
932 }
933
934
935 /*
936 * The function does soft reset the host SD controller. After
937 * the function call all host controller's register are reset
938 * to default vallue;
939 *
940 * Note This function only resets the host controller it does not
941 * reset the controller's handler.
942 */
reset_host_ctrl(struct sd_handle * handle)943 int reset_host_ctrl(struct sd_handle *handle)
944 {
945 chal_sd_stop();
946
947 return SD_OK;
948 }
949
pstate_log(struct sd_handle * handle)950 static void pstate_log(struct sd_handle *handle)
951 {
952 ERROR("PSTATE: 0x%x\n", mmio_read_32
953 (handle->device->ctrl.sdRegBaseAddr +
954 SD4_EMMC_TOP_PSTATE_SD4_OFFSET));
955 ERROR("ERRSTAT: 0x%x\n", mmio_read_32
956 (handle->device->ctrl.sdRegBaseAddr +
957 SD4_EMMC_TOP_ERRSTAT_OFFSET));
958 }
959
960 /*
961 * The function waits for one or a group of interrupts specified
962 * by mask. The function returns if any one the interrupt status
963 * is set. If interrupt mode is not enabled then it will poll
964 * the interrupt status register until a interrupt status is set
965 * an error interrupt happens. If interrupt mode is enabled then
966 * this function should be called after the interrupt
967 * is received by ISR routine.
968 */
wait_for_event(struct sd_handle * handle,uint32_t mask,uint32_t retry)969 uint32_t wait_for_event(struct sd_handle *handle,
970 uint32_t mask, uint32_t retry)
971 {
972 uint32_t regval, cmd12, time = 0;
973
974 handle->device->ctrl.cmdStatus = 0; /* no error */
975 EMMC_TRACE("%s %d mask:0x%x timeout:%d irq_status:0x%x\n",
976 __func__, __LINE__, mask, retry,
977 chal_sd_get_irq_status((CHAL_HANDLE *)handle->device));
978
979 /* Polling mode */
980 do {
981 regval = chal_sd_get_irq_status((CHAL_HANDLE *)handle->device);
982
983 if (regval & SD4_EMMC_TOP_INTR_DMAIRQ_MASK) {
984 chal_sd_set_dma_addr((CHAL_HANDLE *)handle->device,
985 (uintptr_t)
986 chal_sd_get_dma_addr((CHAL_HANDLE *)
987 handle->device));
988 chal_sd_clear_irq((CHAL_HANDLE *)handle->device,
989 SD4_EMMC_TOP_INTR_DMAIRQ_MASK);
990 }
991
992 if (time++ > retry) {
993 ERROR("EMMC: No response (cmd%d) after %dus.\n",
994 handle->device->ctrl.cmdIndex,
995 time * EMMC_WFE_RETRY_DELAY_US);
996 handle->device->ctrl.cmdStatus = SD_CMD_MISSING;
997 pstate_log(handle);
998 ERROR("EMMC: INT[0x%x]\n", regval);
999 break;
1000 }
1001
1002 if (regval & SD4_EMMC_TOP_INTR_CTOERR_MASK) {
1003 ERROR("EMMC: Cmd%d timeout INT[0x%x]\n",
1004 handle->device->ctrl.cmdIndex, regval);
1005 handle->device->ctrl.cmdStatus =
1006 SD4_EMMC_TOP_INTR_CTOERR_MASK;
1007 pstate_log(handle);
1008 break;
1009 }
1010 if (regval & SD_CMD_ERROR_FLAGS) {
1011 ERROR("EMMC: Cmd%d error INT[0x%x]\n",
1012 handle->device->ctrl.cmdIndex, regval);
1013 handle->device->ctrl.cmdStatus = SD_CMD_ERROR_FLAGS;
1014 pstate_log(handle);
1015 break;
1016 }
1017
1018 cmd12 = chal_sd_get_atuo12_error((CHAL_HANDLE *)handle->device);
1019 if (cmd12) {
1020 ERROR("EMMC: Cmd%d auto cmd12 err:0x%x\n",
1021 handle->device->ctrl.cmdIndex, cmd12);
1022 handle->device->ctrl.cmdStatus = cmd12;
1023 pstate_log(handle);
1024 break;
1025 }
1026
1027 if (SD_DATA_ERROR_FLAGS & regval) {
1028 ERROR("EMMC: Data for cmd%d error, INT[0x%x]\n",
1029 handle->device->ctrl.cmdIndex, regval);
1030 handle->device->ctrl.cmdStatus =
1031 (SD_DATA_ERROR_FLAGS & regval);
1032 pstate_log(handle);
1033 break;
1034 }
1035
1036 if ((regval & mask) == 0)
1037 udelay(EMMC_WFE_RETRY_DELAY_US);
1038
1039 } while ((regval & mask) == 0);
1040
1041 /* clear the interrupt since it is processed */
1042 chal_sd_clear_irq((CHAL_HANDLE *)handle->device, (regval & mask));
1043
1044 return (regval & mask);
1045 }
1046
set_config(struct sd_handle * handle,uint32_t speed,uint32_t retry,uint32_t dma,uint32_t dmaBound,uint32_t blkSize,uint32_t wfe_retry)1047 int32_t set_config(struct sd_handle *handle, uint32_t speed, uint32_t retry,
1048 uint32_t dma, uint32_t dmaBound, uint32_t blkSize,
1049 uint32_t wfe_retry)
1050 {
1051 int32_t rel = 0;
1052
1053 if (handle == NULL)
1054 return SD_FAIL;
1055
1056 handle->device->cfg.wfe_retry = wfe_retry;
1057
1058 rel = chal_sd_config((CHAL_HANDLE *)handle->device, speed, retry,
1059 dmaBound, blkSize, dma);
1060 return rel;
1061
1062 }
1063
mmc_cmd1(struct sd_handle * handle)1064 int mmc_cmd1(struct sd_handle *handle)
1065 {
1066 uint32_t newOcr, res;
1067 uint32_t cmd1_option = MMC_OCR_OP_VOLT | MMC_OCR_SECTOR_ACCESS_MODE;
1068
1069 /*
1070 * After Reset, eMMC comes up in 1 Bit Data Width by default.
1071 * Set host side to match.
1072 */
1073 chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
1074 SD_BUS_DATA_WIDTH_1BIT);
1075
1076 #ifdef USE_EMMC_FIP_TOC_CACHE
1077 cached_partition_block = 0;
1078 #endif
1079 handle->device->ctrl.present = 0; /* init card present to be no card */
1080
1081 handle->card->type = SD_CARD_MMC;
1082
1083 res = sd_cmd1(handle, cmd1_option, &newOcr);
1084
1085 if (res != SD_OK) {
1086 EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
1087 res = SD_CARD_UNKNOWN;
1088 }
1089 return res;
1090 }
1091