1Porting Guide 2============= 3 4Introduction 5------------ 6 7Porting Trusted Firmware-A (TF-A) to a new platform involves making some 8mandatory and optional modifications for both the cold and warm boot paths. 9Modifications consist of: 10 11- Implementing a platform-specific function or variable, 12- Setting up the execution context in a certain way, or 13- Defining certain constants (for example #defines). 14 15The platform-specific functions and variables are declared in 16``include/plat/common/platform.h``. The firmware provides a default 17implementation of variables and functions to fulfill the optional requirements 18in order to ease the porting effort. Each platform port can use them as is or 19provide their own implementation if the default implementation is inadequate. 20 21 .. note:: 22 23 TF-A historically provided default implementations of platform interfaces 24 as *weak* functions. This practice is now discouraged and new platform 25 interfaces as they get introduced in the code base should be *strongly* 26 defined. We intend to convert existing weak functions over time. Until 27 then, you will find references to *weak* functions in this document. 28 29Please review the :ref:`Threat Model` documents as part of the porting 30effort. Some platform interfaces play a key role in mitigating against some of 31the threats. Failing to fulfill these expectations could undermine the security 32guarantees offered by TF-A. These platform responsibilities are highlighted in 33the threat assessment section, under the "`Mitigations implemented?`" box for 34each threat. 35 36Some modifications are common to all Boot Loader (BL) stages. Section 2 37discusses these in detail. The subsequent sections discuss the remaining 38modifications for each BL stage in detail. 39 40Please refer to the :ref:`Platform Ports Policy` for the policy regarding 41compatibility and deprecation of these porting interfaces. 42 43Only Arm development platforms (such as FVP and Juno) may use the 44functions/definitions in ``include/plat/arm/common/`` and the corresponding 45source files in ``plat/arm/common/``. This is done so that there are no 46dependencies between platforms maintained by different people/companies. If you 47want to use any of the functionality present in ``plat/arm`` files, please 48propose a patch that moves the code to ``plat/common`` so that it can be 49discussed. 50 51Common modifications 52-------------------- 53 54This section covers the modifications that should be made by the platform for 55each BL stage to correctly port the firmware stack. They are categorized as 56either mandatory or optional. 57 58Common mandatory modifications 59------------------------------ 60 61A platform port must enable the Memory Management Unit (MMU) as well as the 62instruction and data caches for each BL stage. Setting up the translation 63tables is the responsibility of the platform port because memory maps differ 64across platforms. A memory translation library (see ``lib/xlat_tables_v2/``) is 65provided to help in this setup. 66 67Note that although this library supports non-identity mappings, this is intended 68only for re-mapping peripheral physical addresses and allows platforms with high 69I/O addresses to reduce their virtual address space. All other addresses 70corresponding to code and data must currently use an identity mapping. 71 72Also, the only translation granule size supported in TF-A is 4KB, as various 73parts of the code assume that is the case. It is not possible to switch to 7416 KB or 64 KB granule sizes at the moment. 75 76In Arm standard platforms, each BL stage configures the MMU in the 77platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 78an identity mapping for all addresses. 79 80If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 81block of identity mapped secure memory with Device-nGnRE attributes aligned to 82page boundary (4K) for each BL stage. All sections which allocate coherent 83memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a 84section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its 85possible for the firmware to place variables in it using the following C code 86directive: 87 88:: 89 90 __section(".bakery_lock") 91 92Or alternatively the following assembler code directive: 93 94:: 95 96 .section .bakery_lock 97 98The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are 99used to allocate any data structures that are accessed both when a CPU is 100executing with its MMU and caches enabled, and when it's running with its MMU 101and caches disabled. Examples are given below. 102 103The following variables, functions and constants must be defined by the platform 104for the firmware to work correctly. 105 106.. _platform_def_mandatory: 107 108File : platform_def.h [mandatory] 109~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 110 111Each platform must ensure that a header file of this name is in the system 112include path with the following constants defined. This will require updating 113the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. 114 115Platform ports may optionally use the file ``include/plat/common/common_def.h``, 116which provides typical values for some of the constants below. These values are 117likely to be suitable for all platform ports. 118 119- **#define : PLATFORM_LINKER_FORMAT** 120 121 Defines the linker format used by the platform, for example 122 ``elf64-littleaarch64``. 123 124- **#define : PLATFORM_LINKER_ARCH** 125 126 Defines the processor architecture for the linker by the platform, for 127 example ``aarch64``. 128 129- **#define : PLATFORM_STACK_SIZE** 130 131 Defines the normal stack memory available to each CPU. This constant is used 132 by ``plat/common/aarch64/platform_mp_stack.S`` and 133 ``plat/common/aarch64/platform_up_stack.S``. 134 135- **#define : CACHE_WRITEBACK_GRANULE** 136 137 Defines the size in bytes of the largest cache line across all the cache 138 levels in the platform. 139 140- **#define : FIRMWARE_WELCOME_STR** 141 142 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 143 function. 144 145- **#define : PLATFORM_CORE_COUNT** 146 147 Defines the total number of CPUs implemented by the platform across all 148 clusters in the system. 149 150- **#define : PLAT_NUM_PWR_DOMAINS** 151 152 Defines the total number of nodes in the power domain topology 153 tree at all the power domain levels used by the platform. 154 This macro is used by the PSCI implementation to allocate 155 data structures to represent power domain topology. 156 157- **#define : PLAT_MAX_PWR_LVL** 158 159 Defines the maximum power domain level that the power management operations 160 should apply to. More often, but not always, the power domain level 161 corresponds to affinity level. This macro allows the PSCI implementation 162 to know the highest power domain level that it should consider for power 163 management operations in the system that the platform implements. For 164 example, the Base AEM FVP implements two clusters with a configurable 165 number of CPUs and it reports the maximum power domain level as 1. 166 167- **#define : PLAT_MAX_OFF_STATE** 168 169 Defines the local power state corresponding to the deepest power down 170 possible at every power domain level in the platform. The local power 171 states for each level may be sparsely allocated between 0 and this value 172 with 0 being reserved for the RUN state. The PSCI implementation uses this 173 value to initialize the local power states of the power domain nodes and 174 to specify the requested power state for a PSCI_CPU_OFF call. 175 176- **#define : PLAT_MAX_RET_STATE** 177 178 Defines the local power state corresponding to the deepest retention state 179 possible at every power domain level in the platform. This macro should be 180 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the 181 PSCI implementation to distinguish between retention and power down local 182 power states within PSCI_CPU_SUSPEND call. 183 184- **#define : PLAT_MAX_PWR_LVL_STATES** 185 186 Defines the maximum number of local power states per power domain level 187 that the platform supports. The default value of this macro is 2 since 188 most platforms just support a maximum of two local power states at each 189 power domain level (power-down and retention). If the platform needs to 190 account for more local power states, then it must redefine this macro. 191 192 Currently, this macro is used by the Generic PSCI implementation to size 193 the array used for PSCI_STAT_COUNT/RESIDENCY accounting. 194 195- **#define : BL1_RO_BASE** 196 197 Defines the base address in secure ROM where BL1 originally lives. Must be 198 aligned on a page-size boundary. 199 200- **#define : BL1_RO_LIMIT** 201 202 Defines the maximum address in secure ROM that BL1's actual content (i.e. 203 excluding any data section allocated at runtime) can occupy. 204 205- **#define : BL1_RW_BASE** 206 207 Defines the base address in secure RAM where BL1's read-write data will live 208 at runtime. Must be aligned on a page-size boundary. 209 210- **#define : BL1_RW_LIMIT** 211 212 Defines the maximum address in secure RAM that BL1's read-write data can 213 occupy at runtime. 214 215- **#define : BL2_BASE** 216 217 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 218 Must be aligned on a page-size boundary. This constant is not applicable 219 when BL2_IN_XIP_MEM is set to '1'. 220 221- **#define : BL2_LIMIT** 222 223 Defines the maximum address in secure RAM that the BL2 image can occupy. 224 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 225 226- **#define : BL2_RO_BASE** 227 228 Defines the base address in secure XIP memory where BL2 RO section originally 229 lives. Must be aligned on a page-size boundary. This constant is only needed 230 when BL2_IN_XIP_MEM is set to '1'. 231 232- **#define : BL2_RO_LIMIT** 233 234 Defines the maximum address in secure XIP memory that BL2's actual content 235 (i.e. excluding any data section allocated at runtime) can occupy. This 236 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 237 238- **#define : BL2_RW_BASE** 239 240 Defines the base address in secure RAM where BL2's read-write data will live 241 at runtime. Must be aligned on a page-size boundary. This constant is only 242 needed when BL2_IN_XIP_MEM is set to '1'. 243 244- **#define : BL2_RW_LIMIT** 245 246 Defines the maximum address in secure RAM that BL2's read-write data can 247 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 248 to '1'. 249 250- **#define : BL31_BASE** 251 252 Defines the base address in secure RAM where BL2 loads the BL31 binary 253 image. Must be aligned on a page-size boundary. 254 255- **#define : BL31_LIMIT** 256 257 Defines the maximum address in secure RAM that the BL31 image can occupy. 258 259- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE** 260 261 Defines the maximum message size between AP and RSE. Need to define if 262 platform supports RSE. 263 264For every image, the platform must define individual identifiers that will be 265used by BL1 or BL2 to load the corresponding image into memory from non-volatile 266storage. For the sake of performance, integer numbers will be used as 267identifiers. The platform will use those identifiers to return the relevant 268information about the image to be loaded (file handler, load address, 269authentication information, etc.). The following image identifiers are 270mandatory: 271 272- **#define : BL2_IMAGE_ID** 273 274 BL2 image identifier, used by BL1 to load BL2. 275 276- **#define : BL31_IMAGE_ID** 277 278 BL31 image identifier, used by BL2 to load BL31. 279 280- **#define : BL33_IMAGE_ID** 281 282 BL33 image identifier, used by BL2 to load BL33. 283 284If Trusted Board Boot is enabled, the following certificate identifiers must 285also be defined: 286 287- **#define : TRUSTED_BOOT_FW_CERT_ID** 288 289 BL2 content certificate identifier, used by BL1 to load the BL2 content 290 certificate. 291 292- **#define : TRUSTED_KEY_CERT_ID** 293 294 Trusted key certificate identifier, used by BL2 to load the trusted key 295 certificate. 296 297- **#define : SOC_FW_KEY_CERT_ID** 298 299 BL31 key certificate identifier, used by BL2 to load the BL31 key 300 certificate. 301 302- **#define : SOC_FW_CONTENT_CERT_ID** 303 304 BL31 content certificate identifier, used by BL2 to load the BL31 content 305 certificate. 306 307- **#define : NON_TRUSTED_FW_KEY_CERT_ID** 308 309 BL33 key certificate identifier, used by BL2 to load the BL33 key 310 certificate. 311 312- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** 313 314 BL33 content certificate identifier, used by BL2 to load the BL33 content 315 certificate. 316 317- **#define : FWU_CERT_ID** 318 319 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the 320 FWU content certificate. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U_IMAGE_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP_BL2U_IMAGE_ID** 343 344 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP_BL2U. 346 347 .. note:: 348 TF-A does not provide source code for this image. 349 350If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must 351also be defined: 352 353- **#define : NS_BL1U_BASE** 354 355 Defines the base address in non-secure ROM where NS_BL1U executes. 356 Must be aligned on a page-size boundary. 357 358 .. note:: 359 TF-A does not provide source code for this image. 360 361- **#define : NS_BL1U_IMAGE_ID** 362 363 NS_BL1U image identifier, used by BL1 to fetch an image descriptor 364 corresponding to NS_BL1U. 365 366If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also 367be defined: 368 369- **#define : NS_BL2U_BASE** 370 371 Defines the base address in non-secure memory where NS_BL2U executes. 372 Must be aligned on a page-size boundary. 373 374 .. note:: 375 TF-A does not provide source code for this image. 376 377- **#define : NS_BL2U_IMAGE_ID** 378 379 NS_BL2U image identifier, used by BL1 to fetch an image descriptor 380 corresponding to NS_BL2U. 381 382For the the Firmware update capability of TRUSTED BOARD BOOT, the following 383macros may also be defined: 384 385- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** 386 387 Total number of images that can be loaded simultaneously. If the platform 388 doesn't specify any value, it defaults to 10. 389 390If a SCP_BL2 image is supported by the platform, the following constants must 391also be defined: 392 393- **#define : SCP_BL2_IMAGE_ID** 394 395 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory 396 from platform storage before being transferred to the SCP. 397 398- **#define : SCP_FW_KEY_CERT_ID** 399 400 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key 401 certificate (mandatory when Trusted Board Boot is enabled). 402 403- **#define : SCP_FW_CONTENT_CERT_ID** 404 405 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 406 content certificate (mandatory when Trusted Board Boot is enabled). 407 408If a BL32 image is supported by the platform, the following constants must 409also be defined: 410 411- **#define : BL32_IMAGE_ID** 412 413 BL32 image identifier, used by BL2 to load BL32. 414 415- **#define : TRUSTED_OS_FW_KEY_CERT_ID** 416 417 BL32 key certificate identifier, used by BL2 to load the BL32 key 418 certificate (mandatory when Trusted Board Boot is enabled). 419 420- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** 421 422 BL32 content certificate identifier, used by BL2 to load the BL32 content 423 certificate (mandatory when Trusted Board Boot is enabled). 424 425- **#define : BL32_BASE** 426 427 Defines the base address in secure memory where BL2 loads the BL32 binary 428 image. Must be aligned on a page-size boundary. 429 430- **#define : BL32_LIMIT** 431 432 Defines the maximum address that the BL32 image can occupy. 433 434If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 435platform, the following constants must also be defined: 436 437- **#define : TSP_SEC_MEM_BASE** 438 439 Defines the base address of the secure memory used by the TSP image on the 440 platform. This must be at the same address or below ``BL32_BASE``. 441 442- **#define : TSP_SEC_MEM_SIZE** 443 444 Defines the size of the secure memory used by the BL32 image on the 445 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully 446 accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` 447 and ``BL32_LIMIT``. 448 449- **#define : TSP_IRQ_SEC_PHY_TIMER** 450 451 Defines the ID of the secure physical generic timer interrupt used by the 452 TSP's interrupt handling code. 453 454If the platform port uses the translation table library code, the following 455constants must also be defined: 456 457- **#define : PLAT_XLAT_TABLES_DYNAMIC** 458 459 Optional flag that can be set per-image to enable the dynamic allocation of 460 regions even when the MMU is enabled. If not defined, only static 461 functionality will be available, if defined and set to 1 it will also 462 include the dynamic functionality. 463 464- **#define : MAX_XLAT_TABLES** 465 466 Defines the maximum number of translation tables that are allocated by the 467 translation table library code. To minimize the amount of runtime memory 468 used, choose the smallest value needed to map the required virtual addresses 469 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 470 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 471 as well. 472 473- **#define : MAX_MMAP_REGIONS** 474 475 Defines the maximum number of regions that are allocated by the translation 476 table library code. A region consists of physical base address, virtual base 477 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 478 defined in the ``mmap_region_t`` structure. The platform defines the regions 479 that should be mapped. Then, the translation table library will create the 480 corresponding tables and descriptors at runtime. To minimize the amount of 481 runtime memory used, choose the smallest value needed to register the 482 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 483 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 484 the dynamic regions as well. 485 486- **#define : PLAT_VIRT_ADDR_SPACE_SIZE** 487 488 Defines the total size of the virtual address space in bytes. For example, 489 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 490 491- **#define : PLAT_PHY_ADDR_SPACE_SIZE** 492 493 Defines the total size of the physical address space in bytes. For example, 494 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 495 496If the platform port uses the IO storage framework, the following constants 497must also be defined: 498 499- **#define : MAX_IO_DEVICES** 500 501 Defines the maximum number of registered IO devices. Attempting to register 502 more devices than this value using ``io_register_device()`` will fail with 503 -ENOMEM. 504 505- **#define : MAX_IO_HANDLES** 506 507 Defines the maximum number of open IO handles. Attempting to open more IO 508 entities than this value using ``io_open()`` will fail with -ENOMEM. 509 510- **#define : MAX_IO_BLOCK_DEVICES** 511 512 Defines the maximum number of registered IO block devices. Attempting to 513 register more devices this value using ``io_dev_open()`` will fail 514 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. 515 With this macro, multiple block devices could be supported at the same 516 time. 517 518If the platform needs to allocate data within the per-cpu data framework in 519BL31, it should define the following macro. Currently this is only required if 520the platform decides not to use the coherent memory section by undefining the 521``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 522required memory within the the per-cpu data to minimize wastage. 523 524- **#define : PLAT_PCPU_DATA_SIZE** 525 526 Defines the memory (in bytes) to be reserved within the per-cpu data 527 structure for use by the platform layer. 528 529The following constants are optional. They should be defined when the platform 530memory layout implies some image overlaying like in Arm standard platforms. 531 532- **#define : BL31_PROGBITS_LIMIT** 533 534 Defines the maximum address in secure RAM that the BL31's progbits sections 535 can occupy. 536 537- **#define : TSP_PROGBITS_LIMIT** 538 539 Defines the maximum address that the TSP's progbits sections can occupy. 540 541If the platform supports OS-initiated mode, i.e. the build option 542``PSCI_OS_INIT_MODE`` is enabled, and if the platform's maximum power domain 543level for PSCI_CPU_SUSPEND differs from ``PLAT_MAX_PWR_LVL``, the following 544constant must be defined. 545 546- **#define : PLAT_MAX_CPU_SUSPEND_PWR_LVL** 547 548 Defines the maximum power domain level that PSCI_CPU_SUSPEND should apply to. 549 550If the platform port uses the PL061 GPIO driver, the following constant may 551optionally be defined: 552 553- **PLAT_PL061_MAX_GPIOS** 554 Maximum number of GPIOs required by the platform. This allows control how 555 much memory is allocated for PL061 GPIO controllers. The default value is 556 557 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) 558 559If the platform port uses the partition driver, the following constant may 560optionally be defined: 561 562- **PLAT_PARTITION_MAX_ENTRIES** 563 Maximum number of partition entries required by the platform. This allows 564 control how much memory is allocated for partition entries. The default 565 value is 128. 566 For example, define the build flag in ``platform.mk``: 567 PLAT_PARTITION_MAX_ENTRIES := 12 568 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) 569 570- **PLAT_PARTITION_BLOCK_SIZE** 571 The size of partition block. It could be either 512 bytes or 4096 bytes. 572 The default value is 512. 573 For example, define the build flag in ``platform.mk``: 574 PLAT_PARTITION_BLOCK_SIZE := 4096 575 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) 576 577If the platform port uses the Arm® Ethos™-N NPU driver, the following 578configuration must be performed: 579 580- The NPU SiP service handler must be hooked up. This consists of both the 581 initial setup (``ethosn_smc_setup``) and the handler itself 582 (``ethosn_smc_handler``) 583 584If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support 585enabled, the following constants and configuration must also be defined: 586 587- **ETHOSN_NPU_PROT_FW_NSAID** 588 589 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to 590 access the protected memory that contains the NPU's firmware. 591 592- **ETHOSN_NPU_PROT_DATA_RW_NSAID** 593 594 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 595 read/write access to the protected memory that contains inference data. 596 597- **ETHOSN_NPU_PROT_DATA_RO_NSAID** 598 599 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 600 read-only access to the protected memory that contains inference data. 601 602- **ETHOSN_NPU_NS_RW_DATA_NSAID** 603 604 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 605 read/write access to the non-protected memory. 606 607- **ETHOSN_NPU_NS_RO_DATA_NSAID** 608 609 Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for 610 read-only access to the non-protected memory. 611 612- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** 613 614 Defines the physical address range that the NPU's firmware will be loaded 615 into and executed from. 616 617- Configure the platforms TrustZone Controller (TZC) with appropriate regions 618 of protected memory. At minimum this must include a region for the NPU's 619 firmware code and a region for protected inference data, and these must be 620 accessible using the NSAIDs defined above. 621 622- Include the NPU firmware and certificates in the FIP. 623 624- Provide FCONF entries to configure the image source for the NPU firmware 625 and certificates. 626 627- Add MMU mappings such that: 628 629 - BL2 can write the NPU firmware into the region defined by 630 ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` 631 - BL31 (SiP service) can read the NPU firmware from the same region 632 633- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images 634 loaded by BL2. 635 636Please see the reference implementation code for the Juno platform as an example. 637 638 639The following constant is optional. It should be defined to override the default 640behaviour of the ``assert()`` function (for example, to save memory). 641 642- **PLAT_LOG_LEVEL_ASSERT** 643 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 644 ``assert()`` prints the name of the file, the line number and the asserted 645 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 646 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 647 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 648 defined, it defaults to ``LOG_LEVEL``. 649 650If the platform port uses the DRTM feature, the following constants must be 651defined: 652 653- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** 654 655 Maximum Event Log size used by the platform. Platform can decide the maximum 656 size of the Event Log buffer, depending upon the highest hash algorithm 657 chosen and the number of components selected to measure during the DRTM 658 execution flow. 659 660- **#define : PLAT_DRTM_MMAP_ENTRIES** 661 662 Number of the MMAP entries used by the DRTM implementation to calculate the 663 size of address map region of the platform. 664 665File : plat_macros.S [mandatory] 666~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 667 668Each platform must ensure a file of this name is in the system include path with 669the following macro defined. In the Arm development platforms, this file is 670found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 671 672- **Macro : plat_crash_print_regs** 673 674 This macro allows the crash reporting routine to print relevant platform 675 registers in case of an unhandled exception in BL31. This aids in debugging 676 and this macro can be defined to be empty in case register reporting is not 677 desired. 678 679 For instance, GIC or interconnect registers may be helpful for 680 troubleshooting. 681 682Handling Reset 683-------------- 684 685BL1 by default implements the reset vector where execution starts from a cold 686or warm boot. BL31 can be optionally set as a reset vector using the 687``RESET_TO_BL31`` make variable. 688 689For each CPU, the reset vector code is responsible for the following tasks: 690 691#. Distinguishing between a cold boot and a warm boot. 692 693#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 694 the CPU is placed in a platform-specific state until the primary CPU 695 performs the necessary steps to remove it from this state. 696 697#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 698 specific address in the BL31 image in the same processor mode as it was 699 when released from reset. 700 701The following functions need to be implemented by the platform port to enable 702reset vector code to perform the above tasks. 703 704Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] 705~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 706 707:: 708 709 Argument : void 710 Return : uintptr_t 711 712This function is called with the MMU and caches disabled 713(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 714distinguishing between a warm and cold reset for the current CPU using 715platform-specific means. If it's a warm reset, then it returns the warm 716reset entrypoint point provided to ``plat_setup_psci_ops()`` during 717BL31 initialization. If it's a cold reset then this function must return zero. 718 719This function does not follow the Procedure Call Standard used by the 720Application Binary Interface for the Arm 64-bit architecture. The caller should 721not assume that callee saved registers are preserved across a call to this 722function. 723 724This function fulfills requirement 1 and 3 listed above. 725 726Note that for platforms that support programming the reset address, it is 727expected that a CPU will start executing code directly at the right address, 728both on a cold and warm reset. In this case, there is no need to identify the 729type of reset nor to query the warm reset entrypoint. Therefore, implementing 730this function is not required on such platforms. 731 732Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735:: 736 737 Argument : void 738 739This function is called with the MMU and data caches disabled. It is responsible 740for placing the executing secondary CPU in a platform-specific state until the 741primary CPU performs the necessary actions to bring it out of that state and 742allow entry into the OS. This function must not return. 743 744In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 745itself off. The primary CPU is responsible for powering up the secondary CPUs 746when normal world software requires them. When booting an EL3 payload instead, 747they stay powered on and are put in a holding pen until their mailbox gets 748populated. 749 750This function fulfills requirement 2 above. 751 752Note that for platforms that can't release secondary CPUs out of reset, only the 753primary CPU will execute the cold boot code. Therefore, implementing this 754function is not required on such platforms. 755 756Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] 757~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 758 759:: 760 761 Argument : void 762 Return : unsigned int 763 764This function identifies whether the current CPU is the primary CPU or a 765secondary CPU. A return value of zero indicates that the CPU is not the 766primary CPU, while a non-zero return value indicates that the CPU is the 767primary CPU. 768 769Note that for platforms that can't release secondary CPUs out of reset, only the 770primary CPU will execute the cold boot code. Therefore, there is no need to 771distinguish between primary and secondary CPUs and implementing this function is 772not required. 773 774Function : platform_mem_init() [mandatory] 775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 776 777:: 778 779 Argument : void 780 Return : void 781 782This function is called before any access to data is made by the firmware, in 783order to carry out any essential memory initialization. 784 785Function: plat_get_rotpk_info() 786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 787 788:: 789 790 Argument : void *, void **, unsigned int *, unsigned int * 791 Return : int 792 793This function is mandatory when Trusted Board Boot is enabled. It returns a 794pointer to the ROTPK stored in the platform (or a hash of it) and its length. 795The ROTPK must be encoded in DER format according to the following ASN.1 796structure: 797 798:: 799 800 AlgorithmIdentifier ::= SEQUENCE { 801 algorithm OBJECT IDENTIFIER, 802 parameters ANY DEFINED BY algorithm OPTIONAL 803 } 804 805 SubjectPublicKeyInfo ::= SEQUENCE { 806 algorithm AlgorithmIdentifier, 807 subjectPublicKey BIT STRING 808 } 809 810In case the function returns a hash of the key: 811 812:: 813 814 DigestInfo ::= SEQUENCE { 815 digestAlgorithm AlgorithmIdentifier, 816 digest OCTET STRING 817 } 818 819The function returns 0 on success. Any other value is treated as error by the 820Trusted Board Boot. The function also reports extra information related 821to the ROTPK in the flags parameter: 822 823:: 824 825 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 826 hash. 827 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 828 verification while the platform ROTPK is not deployed. 829 When this flag is set, the function does not need to 830 return a platform ROTPK, and the authentication 831 framework uses the ROTPK in the certificate without 832 verifying it against the platform value. This flag 833 must not be used in a deployed production environment. 834 835Function: plat_get_nv_ctr() 836~~~~~~~~~~~~~~~~~~~~~~~~~~~ 837 838:: 839 840 Argument : void *, unsigned int * 841 Return : int 842 843This function is mandatory when Trusted Board Boot is enabled. It returns the 844non-volatile counter value stored in the platform in the second argument. The 845cookie in the first argument may be used to select the counter in case the 846platform provides more than one (for example, on platforms that use the default 847TBBR CoT, the cookie will correspond to the OID values defined in 848TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). 849 850The function returns 0 on success. Any other value means the counter value could 851not be retrieved from the platform. 852 853Function: plat_set_nv_ctr() 854~~~~~~~~~~~~~~~~~~~~~~~~~~~ 855 856:: 857 858 Argument : void *, unsigned int 859 Return : int 860 861This function is mandatory when Trusted Board Boot is enabled. It sets a new 862counter value in the platform. The cookie in the first argument may be used to 863select the counter (as explained in plat_get_nv_ctr()). The second argument is 864the updated counter value to be written to the NV counter. 865 866The function returns 0 on success. Any other value means the counter value could 867not be updated. 868 869Function: plat_set_nv_ctr2() 870~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 871 872:: 873 874 Argument : void *, const auth_img_desc_t *, unsigned int 875 Return : int 876 877This function is optional when Trusted Board Boot is enabled. If this 878interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 879first argument passed is a cookie and is typically used to 880differentiate between a Non Trusted NV Counter and a Trusted NV 881Counter. The second argument is a pointer to an authentication image 882descriptor and may be used to decide if the counter is allowed to be 883updated or not. The third argument is the updated counter value to 884be written to the NV counter. 885 886The function returns 0 on success. Any other value means the counter value 887either could not be updated or the authentication image descriptor indicates 888that it is not allowed to be updated. 889 890Dynamic Root of Trust for Measurement support (in BL31) 891------------------------------------------------------- 892 893The functions mentioned in this section are mandatory, when platform enables 894DRTM_SUPPORT build flag. 895 896Function : plat_get_addr_mmap() 897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 898 899:: 900 901 Argument : void 902 Return : const mmap_region_t * 903 904This function is used to return the address of the platform *address-map* table, 905which describes the regions of normal memory, memory mapped I/O 906and non-volatile memory. 907 908Function : plat_has_non_host_platforms() 909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 910 911:: 912 913 Argument : void 914 Return : bool 915 916This function returns *true* if the platform has any trusted devices capable of 917DMA, otherwise returns *false*. 918 919Function : plat_has_unmanaged_dma_peripherals() 920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 921 922:: 923 924 Argument : void 925 Return : bool 926 927This function returns *true* if platform uses peripherals whose DMA is not 928managed by an SMMU, otherwise returns *false*. 929 930Note - 931If the platform has peripherals that are not managed by the SMMU, then the 932platform should investigate such peripherals to determine whether they can 933be trusted, and such peripherals should be moved under "Non-host platforms" 934if they can be trusted. 935 936Function : plat_get_total_num_smmus() 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939:: 940 941 Argument : void 942 Return : unsigned int 943 944This function returns the total number of SMMUs in the platform. 945 946Function : plat_enumerate_smmus() 947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 948:: 949 950 951 Argument : void 952 Return : const uintptr_t *, size_t 953 954This function returns an array of SMMU addresses and the actual number of SMMUs 955reported by the platform. 956 957Function : plat_drtm_get_dma_prot_features() 958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 959 960:: 961 962 Argument : void 963 Return : const plat_drtm_dma_prot_features_t* 964 965This function returns the address of plat_drtm_dma_prot_features_t structure 966containing the maximum number of protected regions and bitmap with the types 967of DMA protection supported by the platform. 968For more details see section 3.3 Table 6 of `DRTM`_ specification. 969 970Function : plat_drtm_dma_prot_get_max_table_bytes() 971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 972 973:: 974 975 Argument : void 976 Return : uint64_t 977 978This function returns the maximum size of DMA protected regions table in 979bytes. 980 981Function : plat_drtm_get_tpm_features() 982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 983 984:: 985 986 Argument : void 987 Return : const plat_drtm_tpm_features_t* 988 989This function returns the address of *plat_drtm_tpm_features_t* structure 990containing PCR usage schema, TPM-based hash, and firmware hash algorithm 991supported by the platform. 992 993Function : plat_drtm_get_min_size_normal_world_dce() 994~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 995 996:: 997 998 Argument : void 999 Return : uint64_t 1000 1001This function returns the size normal-world DCE of the platform. 1002 1003Function : plat_drtm_get_imp_def_dlme_region_size() 1004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1005 1006:: 1007 1008 Argument : void 1009 Return : uint64_t 1010 1011This function returns the size of implementation defined DLME region 1012of the platform. 1013 1014Function : plat_drtm_get_tcb_hash_table_size() 1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1016 1017:: 1018 1019 Argument : void 1020 Return : uint64_t 1021 1022This function returns the size of TCB hash table of the platform. 1023 1024Function : plat_drtm_get_tcb_hash_features() 1025~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1026 1027:: 1028 1029 Argument : void 1030 Return : uint64_t 1031 1032This function returns the Maximum number of TCB hashes recorded by the 1033platform. 1034For more details see section 3.3 Table 6 of `DRTM`_ specification. 1035 1036Function : plat_drtm_validate_ns_region() 1037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1038 1039:: 1040 1041 Argument : uintptr_t, uintptr_t 1042 Return : int 1043 1044This function validates that given region is within the Non-Secure region 1045of DRAM. This function takes a region start address and size an input 1046arguments, and returns 0 on success and -1 on failure. 1047 1048Function : plat_set_drtm_error() 1049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1050 1051:: 1052 1053 Argument : uint64_t 1054 Return : int 1055 1056This function writes a 64 bit error code received as input into 1057non-volatile storage and returns 0 on success and -1 on failure. 1058 1059Function : plat_get_drtm_error() 1060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1061 1062:: 1063 1064 Argument : uint64_t* 1065 Return : int 1066 1067This function reads a 64 bit error code from the non-volatile storage 1068into the received address, and returns 0 on success and -1 on failure. 1069 1070Common mandatory function modifications 1071--------------------------------------- 1072 1073The following functions are mandatory functions which need to be implemented 1074by the platform port. 1075 1076Function : plat_my_core_pos() 1077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1078 1079:: 1080 1081 Argument : void 1082 Return : unsigned int 1083 1084This function returns the index of the calling CPU which is used as a 1085CPU-specific linear index into blocks of memory (for example while allocating 1086per-CPU stacks). This function will be invoked very early in the 1087initialization sequence which mandates that this function should be 1088implemented in assembly and should not rely on the availability of a C 1089runtime environment. This function can clobber x0 - x8 and must preserve 1090x9 - x29. 1091 1092This function plays a crucial role in the power domain topology framework in 1093PSCI and details of this can be found in 1094:ref:`PSCI Power Domain Tree Structure`. 1095 1096Function : plat_core_pos_by_mpidr() 1097~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1098 1099:: 1100 1101 Argument : u_register_t 1102 Return : int 1103 1104This function validates the ``MPIDR`` of a CPU and converts it to an index, 1105which can be used as a CPU-specific linear index into blocks of memory. In 1106case the ``MPIDR`` is invalid, this function returns -1. This function will only 1107be invoked by BL31 after the power domain topology is initialized and can 1108utilize the C runtime environment. For further details about how TF-A 1109represents the power domain topology and how this relates to the linear CPU 1110index, please refer :ref:`PSCI Power Domain Tree Structure`. 1111 1112Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] 1113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1114 1115:: 1116 1117 Arguments : void **heap_addr, size_t *heap_size 1118 Return : int 1119 1120This function is invoked during Mbed TLS library initialisation to get a heap, 1121by means of a starting address and a size. This heap will then be used 1122internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS 1123must be able to provide a heap to it. 1124 1125A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in 1126which a heap is statically reserved during compile time inside every image 1127(i.e. every BL stage) that utilises Mbed TLS. In this default implementation, 1128the function simply returns the address and size of this "pre-allocated" heap. 1129For a platform to use this default implementation, only a call to the helper 1130from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. 1131 1132However, by writting their own implementation, platforms have the potential to 1133optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is 1134shared between BL1 and BL2 stages and, thus, the necessary space is not reserved 1135twice. 1136 1137On success the function should return 0 and a negative error code otherwise. 1138 1139Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] 1140~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1141 1142:: 1143 1144 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, 1145 size_t *key_len, unsigned int *flags, const uint8_t *img_id, 1146 size_t img_id_len 1147 Return : int 1148 1149This function provides a symmetric key (either SSK or BSSK depending on 1150fw_enc_status) which is invoked during runtime decryption of encrypted 1151firmware images. `plat/common/plat_bl_common.c` provides a dummy weak 1152implementation for testing purposes which must be overridden by the platform 1153trying to implement a real world firmware encryption use-case. 1154 1155It also allows the platform to pass symmetric key identifier rather than 1156actual symmetric key which is useful in cases where the crypto backend provides 1157secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` 1158flag must be set in ``flags``. 1159 1160In addition to above a platform may also choose to provide an image specific 1161symmetric key/identifier using img_id. 1162 1163On success the function should return 0 and a negative error code otherwise. 1164 1165Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. 1166 1167Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] 1168~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1169 1170:: 1171 1172 Argument : const struct fwu_metadata *metadata 1173 Return : void 1174 1175This function is mandatory when PSA_FWU_SUPPORT is enabled. 1176It provides a means to retrieve image specification (offset in 1177non-volatile storage and length) of active/updated images using the passed 1178FWU metadata, and update I/O policies of active/updated images using retrieved 1179image specification information. 1180Further I/O layer operations such as I/O open, I/O read, etc. on these 1181images rely on this function call. 1182 1183In Arm platforms, this function is used to set an I/O policy of the FIP image, 1184container of all active/updated secure and non-secure images. 1185 1186Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] 1187~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1188 1189:: 1190 1191 Argument : unsigned int image_id, uintptr_t *dev_handle, 1192 uintptr_t *image_spec 1193 Return : int 1194 1195This function is mandatory when PSA_FWU_SUPPORT is enabled. It is 1196responsible for setting up the platform I/O policy of the requested metadata 1197image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will 1198be used to load this image from the platform's non-volatile storage. 1199 1200FWU metadata can not be always stored as a raw image in non-volatile storage 1201to define its image specification (offset in non-volatile storage and length) 1202statically in I/O policy. 1203For example, the FWU metadata image is stored as a partition inside the GUID 1204partition table image. Its specification is defined in the partition table 1205that needs to be parsed dynamically. 1206This function provides a means to retrieve such dynamic information to set 1207the I/O policy of the FWU metadata image. 1208Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata 1209image relies on this function call. 1210 1211It returns '0' on success, otherwise a negative error value on error. 1212Alongside, returns device handle and image specification from the I/O policy 1213of the requested FWU metadata image. 1214 1215Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] 1216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1217 1218:: 1219 1220 Argument : void 1221 Return : uint32_t 1222 1223This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the 1224means to retrieve the boot index value from the platform. The boot index is the 1225bank from which the platform has booted the firmware images. 1226 1227By default, the platform will read the metadata structure and try to boot from 1228the active bank. If the platform fails to boot from the active bank due to 1229reasons like an Authentication failure, or on crossing a set number of watchdog 1230resets while booting from the active bank, the platform can then switch to boot 1231from a different bank. This function then returns the bank that the platform 1232should boot its images from. 1233 1234Common optional modifications 1235----------------------------- 1236 1237The following are helper functions implemented by the firmware that perform 1238common platform-specific tasks. A platform may choose to override these 1239definitions. 1240 1241Function : plat_set_my_stack() 1242~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1243 1244:: 1245 1246 Argument : void 1247 Return : void 1248 1249This function sets the current stack pointer to the normal memory stack that 1250has been allocated for the current CPU. For BL images that only require a 1251stack for the primary CPU, the UP version of the function is used. The size 1252of the stack allocated to each CPU is specified by the platform defined 1253constant ``PLATFORM_STACK_SIZE``. 1254 1255Common implementations of this function for the UP and MP BL images are 1256provided in ``plat/common/aarch64/platform_up_stack.S`` and 1257``plat/common/aarch64/platform_mp_stack.S`` 1258 1259Function : plat_get_my_stack() 1260~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1261 1262:: 1263 1264 Argument : void 1265 Return : uintptr_t 1266 1267This function returns the base address of the normal memory stack that 1268has been allocated for the current CPU. For BL images that only require a 1269stack for the primary CPU, the UP version of the function is used. The size 1270of the stack allocated to each CPU is specified by the platform defined 1271constant ``PLATFORM_STACK_SIZE``. 1272 1273Common implementations of this function for the UP and MP BL images are 1274provided in ``plat/common/aarch64/platform_up_stack.S`` and 1275``plat/common/aarch64/platform_mp_stack.S`` 1276 1277Function : plat_report_exception() 1278~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1279 1280:: 1281 1282 Argument : unsigned int 1283 Return : void 1284 1285A platform may need to report various information about its status when an 1286exception is taken, for example the current exception level, the CPU security 1287state (secure/non-secure), the exception type, and so on. This function is 1288called in the following circumstances: 1289 1290- In BL1, whenever an exception is taken. 1291- In BL2, whenever an exception is taken. 1292 1293The default implementation doesn't do anything, to avoid making assumptions 1294about the way the platform displays its status information. 1295 1296For AArch64, this function receives the exception type as its argument. 1297Possible values for exceptions types are listed in the 1298``include/common/bl_common.h`` header file. Note that these constants are not 1299related to any architectural exception code; they are just a TF-A convention. 1300 1301For AArch32, this function receives the exception mode as its argument. 1302Possible values for exception modes are listed in the 1303``include/lib/aarch32/arch.h`` header file. 1304 1305Function : plat_reset_handler() 1306~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1307 1308:: 1309 1310 Argument : void 1311 Return : void 1312 1313A platform may need to do additional initialization after reset. This function 1314allows the platform to do the platform specific initializations. Platform 1315specific errata workarounds could also be implemented here. The API should 1316preserve the values of callee saved registers x19 to x29. 1317 1318The default implementation doesn't do anything. If a platform needs to override 1319the default implementation, refer to the :ref:`Firmware Design` for general 1320guidelines. 1321 1322Function : plat_disable_acp() 1323~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1324 1325:: 1326 1327 Argument : void 1328 Return : void 1329 1330This API allows a platform to disable the Accelerator Coherency Port (if 1331present) during a cluster power down sequence. The default weak implementation 1332doesn't do anything. Since this API is called during the power down sequence, 1333it has restrictions for stack usage and it can use the registers x0 - x17 as 1334scratch registers. It should preserve the value in x18 register as it is used 1335by the caller to store the return address. 1336 1337Function : plat_error_handler() 1338~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1339 1340:: 1341 1342 Argument : int 1343 Return : void 1344 1345This API is called when the generic code encounters an error situation from 1346which it cannot continue. It allows the platform to perform error reporting or 1347recovery actions (for example, reset the system). This function must not return. 1348 1349The parameter indicates the type of error using standard codes from ``errno.h``. 1350Possible errors reported by the generic code are: 1351 1352- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 1353 Board Boot is enabled) 1354- ``-ENOENT``: the requested image or certificate could not be found or an IO 1355 error was detected 1356- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 1357 error is usually an indication of an incorrect array size 1358 1359The default implementation simply spins. 1360 1361Function : plat_panic_handler() 1362~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1363 1364:: 1365 1366 Argument : void 1367 Return : void 1368 1369This API is called when the generic code encounters an unexpected error 1370situation from which it cannot recover. This function must not return, 1371and must be implemented in assembly because it may be called before the C 1372environment is initialized. 1373 1374.. note:: 1375 The address from where it was called is stored in x30 (Link Register). 1376 The default implementation simply spins. 1377 1378Function : plat_system_reset() 1379~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1380 1381:: 1382 1383 Argument : void 1384 Return : void 1385 1386This function is used by the platform to resets the system. It can be used 1387in any specific use-case where system needs to be resetted. For example, 1388in case of DRTM implementation this function reset the system after 1389writing the DRTM error code in the non-volatile storage. This function 1390never returns. Failure in reset results in panic. 1391 1392Function : plat_get_bl_image_load_info() 1393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1394 1395:: 1396 1397 Argument : void 1398 Return : bl_load_info_t * 1399 1400This function returns pointer to the list of images that the platform has 1401populated to load. This function is invoked in BL2 to load the 1402BL3xx images. 1403 1404Function : plat_get_next_bl_params() 1405~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1406 1407:: 1408 1409 Argument : void 1410 Return : bl_params_t * 1411 1412This function returns a pointer to the shared memory that the platform has 1413kept aside to pass TF-A related information that next BL image needs. This 1414function is invoked in BL2 to pass this information to the next BL 1415image. 1416 1417Function : plat_get_stack_protector_canary() 1418~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1419 1420:: 1421 1422 Argument : void 1423 Return : u_register_t 1424 1425This function returns a random value that is used to initialize the canary used 1426when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable 1427value will weaken the protection as the attacker could easily write the right 1428value as part of the attack most of the time. Therefore, it should return a 1429true random number. 1430 1431.. warning:: 1432 For the protection to be effective, the global data need to be placed at 1433 a lower address than the stack bases. Failure to do so would allow an 1434 attacker to overwrite the canary as part of the stack buffer overflow attack. 1435 1436Function : plat_flush_next_bl_params() 1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1438 1439:: 1440 1441 Argument : void 1442 Return : void 1443 1444This function flushes to main memory all the image params that are passed to 1445next image. This function is invoked in BL2 to flush this information 1446to the next BL image. 1447 1448Function : plat_log_get_prefix() 1449~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1450 1451:: 1452 1453 Argument : unsigned int 1454 Return : const char * 1455 1456This function defines the prefix string corresponding to the `log_level` to be 1457prepended to all the log output from TF-A. The `log_level` (argument) will 1458correspond to one of the standard log levels defined in debug.h. The platform 1459can override the common implementation to define a different prefix string for 1460the log output. The implementation should be robust to future changes that 1461increase the number of log levels. 1462 1463Function : plat_get_soc_version() 1464~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1465 1466:: 1467 1468 Argument : void 1469 Return : int32_t 1470 1471This function returns soc version which mainly consist of below fields 1472 1473:: 1474 1475 soc_version[30:24] = JEP-106 continuation code for the SiP 1476 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 1477 soc_version[15:0] = Implementation defined SoC ID 1478 1479Function : plat_get_soc_revision() 1480~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1481 1482:: 1483 1484 Argument : void 1485 Return : int32_t 1486 1487This function returns soc revision in below format 1488 1489:: 1490 1491 soc_revision[0:30] = SOC revision of specific SOC 1492 1493Function : plat_is_smccc_feature_available() 1494~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1495 1496:: 1497 1498 Argument : u_register_t 1499 Return : int32_t 1500 1501This function returns SMC_ARCH_CALL_SUCCESS if the platform supports 1502the SMCCC function specified in the argument; otherwise returns 1503SMC_ARCH_CALL_NOT_SUPPORTED. 1504 1505Function : plat_can_cmo() 1506~~~~~~~~~~~~~~~~~~~~~~~~~ 1507 1508:: 1509 1510 Argument : void 1511 Return : uint64_t 1512 1513When CONDITIONAL_CMO flag is enabled: 1514 1515- This function indicates whether cache management operations should be 1516 performed. It returns 0 if CMOs should be skipped and non-zero 1517 otherwise. 1518- The function must not clobber x1, x2 and x3. It's also not safe to rely on 1519 stack. Otherwise obey AAPCS. 1520 1521Modifications specific to a Boot Loader stage 1522--------------------------------------------- 1523 1524Boot Loader Stage 1 (BL1) 1525------------------------- 1526 1527BL1 implements the reset vector where execution starts from after a cold or 1528warm boot. For each CPU, BL1 is responsible for the following tasks: 1529 1530#. Handling the reset as described in section 2.2 1531 1532#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1533 only this CPU executes the remaining BL1 code, including loading and passing 1534 control to the BL2 stage. 1535 1536#. Identifying and starting the Firmware Update process (if required). 1537 1538#. Loading the BL2 image from non-volatile storage into secure memory at the 1539 address specified by the platform defined constant ``BL2_BASE``. 1540 1541#. Populating a ``meminfo`` structure with the following information in memory, 1542 accessible by BL2 immediately upon entry. 1543 1544 :: 1545 1546 meminfo.total_base = Base address of secure RAM visible to BL2 1547 meminfo.total_size = Size of secure RAM visible to BL2 1548 1549 By default, BL1 places this ``meminfo`` structure at the end of secure 1550 memory visible to BL2. 1551 1552 It is possible for the platform to decide where it wants to place the 1553 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1554 BL2 by overriding the weak default implementation of 1555 ``bl1_plat_handle_post_image_load`` API. 1556 1557The following functions need to be implemented by the platform port to enable 1558BL1 to perform the above tasks. 1559 1560Function : bl1_early_platform_setup() [mandatory] 1561~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1562 1563:: 1564 1565 Argument : void 1566 Return : void 1567 1568This function executes with the MMU and data caches disabled. It is only called 1569by the primary CPU. 1570 1571On Arm standard platforms, this function: 1572 1573- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1574 1575- Initializes a UART (PL011 console), which enables access to the ``printf`` 1576 family of functions in BL1. 1577 1578- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1579 the CCI slave interface corresponding to the cluster that includes the 1580 primary CPU. 1581 1582Function : bl1_plat_arch_setup() [mandatory] 1583~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1584 1585:: 1586 1587 Argument : void 1588 Return : void 1589 1590This function performs any platform-specific and architectural setup that the 1591platform requires. Platform-specific setup might include configuration of 1592memory controllers and the interconnect. 1593 1594In Arm standard platforms, this function enables the MMU. 1595 1596This function helps fulfill requirement 2 above. 1597 1598Function : bl1_platform_setup() [mandatory] 1599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1600 1601:: 1602 1603 Argument : void 1604 Return : void 1605 1606This function executes with the MMU and data caches enabled. It is responsible 1607for performing any remaining platform-specific setup that can occur after the 1608MMU and data cache have been enabled. 1609 1610if support for multiple boot sources is required, it initializes the boot 1611sequence used by plat_try_next_boot_source(). 1612 1613In Arm standard platforms, this function initializes the storage abstraction 1614layer used to load the next bootloader image. 1615 1616This function helps fulfill requirement 4 above. 1617 1618Function : bl1_plat_sec_mem_layout() [mandatory] 1619~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1620 1621:: 1622 1623 Argument : void 1624 Return : meminfo * 1625 1626This function should only be called on the cold boot path. It executes with the 1627MMU and data caches enabled. The pointer returned by this function must point to 1628a ``meminfo`` structure containing the extents and availability of secure RAM for 1629the BL1 stage. 1630 1631:: 1632 1633 meminfo.total_base = Base address of secure RAM visible to BL1 1634 meminfo.total_size = Size of secure RAM visible to BL1 1635 1636This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1637populates a similar structure to tell BL2 the extents of memory available for 1638its own use. 1639 1640This function helps fulfill requirements 4 and 5 above. 1641 1642Function : bl1_plat_prepare_exit() [optional] 1643~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1644 1645:: 1646 1647 Argument : entry_point_info_t * 1648 Return : void 1649 1650This function is called prior to exiting BL1 in response to the 1651``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1652platform specific clean up or bookkeeping operations before transferring 1653control to the next image. It receives the address of the ``entry_point_info_t`` 1654structure passed from BL2. This function runs with MMU disabled. 1655 1656Function : bl1_plat_set_ep_info() [optional] 1657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1658 1659:: 1660 1661 Argument : unsigned int image_id, entry_point_info_t *ep_info 1662 Return : void 1663 1664This function allows platforms to override ``ep_info`` for the given ``image_id``. 1665 1666The default implementation just returns. 1667 1668Function : bl1_plat_get_next_image_id() [optional] 1669~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1670 1671:: 1672 1673 Argument : void 1674 Return : unsigned int 1675 1676This and the following function must be overridden to enable the FWU feature. 1677 1678BL1 calls this function after platform setup to identify the next image to be 1679loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1680with the normal boot sequence, which loads and executes BL2. If the platform 1681returns a different image id, BL1 assumes that Firmware Update is required. 1682 1683The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1684platforms override this function to detect if firmware update is required, and 1685if so, return the first image in the firmware update process. 1686 1687Function : bl1_plat_get_image_desc() [optional] 1688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1689 1690:: 1691 1692 Argument : unsigned int image_id 1693 Return : image_desc_t * 1694 1695BL1 calls this function to get the image descriptor information ``image_desc_t`` 1696for the provided ``image_id`` from the platform. 1697 1698The default implementation always returns a common BL2 image descriptor. Arm 1699standard platforms return an image descriptor corresponding to BL2 or one of 1700the firmware update images defined in the Trusted Board Boot Requirements 1701specification. 1702 1703Function : bl1_plat_handle_pre_image_load() [optional] 1704~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1705 1706:: 1707 1708 Argument : unsigned int image_id 1709 Return : int 1710 1711This function can be used by the platforms to update/use image information 1712corresponding to ``image_id``. This function is invoked in BL1, both in cold 1713boot and FWU code path, before loading the image. 1714 1715Function : bl1_plat_calc_bl2_layout() [optional] 1716~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1717 1718:: 1719 1720 Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout 1721 Return : void 1722 1723This utility function calculates the memory layout of BL2, representing it in a 1724`meminfo_t` structure. The default implementation derives this layout from the 1725positioning of BL1’s RW data at the top of the memory layout. 1726 1727Function : bl1_plat_handle_post_image_load() [optional] 1728~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1729 1730:: 1731 1732 Argument : unsigned int image_id 1733 Return : int 1734 1735This function can be used by the platforms to update/use image information 1736corresponding to ``image_id``. This function is invoked in BL1, both in cold 1737boot and FWU code path, after loading and authenticating the image. 1738 1739The default weak implementation of this function calculates the amount of 1740Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1741structure at the beginning of this free memory and populates it. The address 1742of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1743information to BL2. 1744 1745Function : bl1_plat_fwu_done() [optional] 1746~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1747 1748:: 1749 1750 Argument : unsigned int image_id, uintptr_t image_src, 1751 unsigned int image_size 1752 Return : void 1753 1754BL1 calls this function when the FWU process is complete. It must not return. 1755The platform may override this function to take platform specific action, for 1756example to initiate the normal boot flow. 1757 1758The default implementation spins forever. 1759 1760Function : bl1_plat_mem_check() [mandatory] 1761~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1762 1763:: 1764 1765 Argument : uintptr_t mem_base, unsigned int mem_size, 1766 unsigned int flags 1767 Return : int 1768 1769BL1 calls this function while handling FWU related SMCs, more specifically when 1770copying or authenticating an image. Its responsibility is to ensure that the 1771region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1772that this memory corresponds to either a secure or non-secure memory region as 1773indicated by the security state of the ``flags`` argument. 1774 1775This function can safely assume that the value resulting from the addition of 1776``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1777overflow. 1778 1779This function must return 0 on success, a non-null error code otherwise. 1780 1781The default implementation of this function asserts therefore platforms must 1782override it when using the FWU feature. 1783 1784Boot Loader Stage 2 (BL2) 1785------------------------- 1786 1787The BL2 stage is executed only by the primary CPU, which is determined in BL1 1788using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1789``BL2_BASE``. BL2 executes in Secure EL1 and and invokes 1790``plat_get_bl_image_load_info()`` to retrieve the list of images to load from 1791non-volatile storage to secure/non-secure RAM. After all the images are loaded 1792then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable 1793images to be passed to the next BL image. 1794 1795The following functions must be implemented by the platform port to enable BL2 1796to perform the above tasks. 1797 1798Function : bl2_early_platform_setup2() [mandatory] 1799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1800 1801:: 1802 1803 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1804 Return : void 1805 1806This function executes with the MMU and data caches disabled. It is only called 1807by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments 1808are platform specific. 1809 1810On Arm standard platforms, the arguments received are : 1811 1812 arg0 - Points to load address of FW_CONFIG 1813 1814 arg1 - ``meminfo`` structure populated by BL1. The platform copies 1815 the contents of ``meminfo`` as it may be subsequently overwritten by BL2. 1816 1817On Arm standard platforms, this function also: 1818 1819- Initializes a UART (PL011 console), which enables access to the ``printf`` 1820 family of functions in BL2. 1821 1822- Initializes the storage abstraction layer used to load further bootloader 1823 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1824 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1825 1826Function : bl2_plat_arch_setup() [mandatory] 1827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1828 1829:: 1830 1831 Argument : void 1832 Return : void 1833 1834This function executes with the MMU and data caches disabled. It is only called 1835by the primary CPU. 1836 1837The purpose of this function is to perform any architectural initialization 1838that varies across platforms. 1839 1840On Arm standard platforms, this function enables the MMU. 1841 1842Function : bl2_platform_setup() [mandatory] 1843~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1844 1845:: 1846 1847 Argument : void 1848 Return : void 1849 1850This function may execute with the MMU and data caches enabled if the platform 1851port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1852called by the primary CPU. 1853 1854The purpose of this function is to perform any platform initialization 1855specific to BL2. 1856 1857In Arm standard platforms, this function performs security setup, including 1858configuration of the TrustZone controller to allow non-secure masters access 1859to most of DRAM. Part of DRAM is reserved for secure world use. 1860 1861Function : bl2_plat_handle_pre_image_load() [optional] 1862~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1863 1864:: 1865 1866 Argument : unsigned int 1867 Return : int 1868 1869This function can be used by the platforms to update/use image information 1870for given ``image_id``. This function is currently invoked in BL2 before 1871loading each image. 1872 1873Function : bl2_plat_handle_post_image_load() [optional] 1874~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1875 1876:: 1877 1878 Argument : unsigned int 1879 Return : int 1880 1881This function can be used by the platforms to update/use image information 1882for given ``image_id``. This function is currently invoked in BL2 after 1883loading each image. 1884 1885Function : bl2_plat_preload_setup [optional] 1886~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1887 1888:: 1889 1890 Argument : void 1891 Return : void 1892 1893This optional function performs any BL2 platform initialization 1894required before image loading, that is not done later in 1895bl2_platform_setup(). Specifically, if support for multiple 1896boot sources is required, it initializes the boot sequence used by 1897plat_try_next_boot_source(). 1898 1899Function : plat_try_next_boot_source() [optional] 1900~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1901 1902:: 1903 1904 Argument : void 1905 Return : int 1906 1907This optional function passes to the next boot source in the redundancy 1908sequence. 1909 1910This function moves the current boot redundancy source to the next 1911element in the boot sequence. If there are no more boot sources then it 1912must return 0, otherwise it must return 1. The default implementation 1913of this always returns 0. 1914 1915Boot Loader Stage 2 (BL2) at EL3 1916-------------------------------- 1917 1918When the platform has a non-TF-A Boot ROM it is desirable to jump 1919directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1920execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` 1921document for more information. 1922 1923All mandatory functions of BL2 must be implemented, except the functions 1924bl2_early_platform_setup and bl2_el3_plat_arch_setup, because 1925their work is done now by bl2_el3_early_platform_setup and 1926bl2_el3_plat_arch_setup. These functions should generally implement 1927the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. 1928 1929 1930Function : bl2_el3_early_platform_setup() [mandatory] 1931~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1932 1933:: 1934 1935 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1936 Return : void 1937 1938This function executes with the MMU and data caches disabled. It is only called 1939by the primary CPU. This function receives four parameters which can be used 1940by the platform to pass any needed information from the Boot ROM to BL2. 1941 1942On Arm standard platforms, this function does the following: 1943 1944- Initializes a UART (PL011 console), which enables access to the ``printf`` 1945 family of functions in BL2. 1946 1947- Initializes the storage abstraction layer used to load further bootloader 1948 images. It is necessary to do this early on platforms with a SCP_BL2 image, 1949 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. 1950 1951- Initializes the private variables that define the memory layout used. 1952 1953Function : bl2_el3_plat_arch_setup() [mandatory] 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956:: 1957 1958 Argument : void 1959 Return : void 1960 1961This function executes with the MMU and data caches disabled. It is only called 1962by the primary CPU. 1963 1964The purpose of this function is to perform any architectural initialization 1965that varies across platforms. 1966 1967On Arm standard platforms, this function enables the MMU. 1968 1969Function : bl2_el3_plat_prepare_exit() [optional] 1970~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1971 1972:: 1973 1974 Argument : void 1975 Return : void 1976 1977This function is called prior to exiting BL2 and run the next image. 1978It should be used to perform platform specific clean up or bookkeeping 1979operations before transferring control to the next image. This function 1980runs with MMU disabled. 1981 1982FWU Boot Loader Stage 2 (BL2U) 1983------------------------------ 1984 1985The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1986process and is executed only by the primary CPU. BL1 passes control to BL2U at 1987``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1988 1989#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure 1990 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. 1991 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U 1992 should be copied from. Subsequent handling of the SCP_BL2U image is 1993 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1994 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1995 1996#. Any platform specific setup required to perform the FWU process. For 1997 example, Arm standard platforms initialize the TZC controller so that the 1998 normal world can access DDR memory. 1999 2000The following functions must be implemented by the platform port to enable 2001BL2U to perform the tasks mentioned above. 2002 2003Function : bl2u_early_platform_setup() [mandatory] 2004~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2005 2006:: 2007 2008 Argument : meminfo *mem_info, void *plat_info 2009 Return : void 2010 2011This function executes with the MMU and data caches disabled. It is only 2012called by the primary CPU. The arguments to this function is the address 2013of the ``meminfo`` structure and platform specific info provided by BL1. 2014 2015The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 2016private storage as the original memory may be subsequently overwritten by BL2U. 2017 2018On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 2019to extract SCP_BL2U image information, which is then copied into a private 2020variable. 2021 2022Function : bl2u_plat_arch_setup() [mandatory] 2023~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2024 2025:: 2026 2027 Argument : void 2028 Return : void 2029 2030This function executes with the MMU and data caches disabled. It is only 2031called by the primary CPU. 2032 2033The purpose of this function is to perform any architectural initialization 2034that varies across platforms, for example enabling the MMU (since the memory 2035map differs across platforms). 2036 2037Function : bl2u_platform_setup() [mandatory] 2038~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2039 2040:: 2041 2042 Argument : void 2043 Return : void 2044 2045This function may execute with the MMU and data caches enabled if the platform 2046port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 2047called by the primary CPU. 2048 2049The purpose of this function is to perform any platform initialization 2050specific to BL2U. 2051 2052In Arm standard platforms, this function performs security setup, including 2053configuration of the TrustZone controller to allow non-secure masters access 2054to most of DRAM. Part of DRAM is reserved for secure world use. 2055 2056Function : bl2u_plat_handle_scp_bl2u() [optional] 2057~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2058 2059:: 2060 2061 Argument : void 2062 Return : int 2063 2064This function is used to perform any platform-specific actions required to 2065handle the SCP firmware. Typically it transfers the image into SCP memory using 2066a platform-specific protocol and waits until SCP executes it and signals to the 2067Application Processor (AP) for BL2U execution to continue. 2068 2069This function returns 0 on success, a negative error code otherwise. 2070This function is included if SCP_BL2U_BASE is defined. 2071 2072Boot Loader Stage 3-1 (BL31) 2073---------------------------- 2074 2075During cold boot, the BL31 stage is executed only by the primary CPU. This is 2076determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 2077control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 2078CPUs. BL31 executes at EL3 and is responsible for: 2079 2080#. Re-initializing all architectural and platform state. Although BL1 performs 2081 some of this initialization, BL31 remains resident in EL3 and must ensure 2082 that EL3 architectural and platform state is completely initialized. It 2083 should make no assumptions about the system state when it receives control. 2084 2085#. Passing control to a normal world BL image, pre-loaded at a platform- 2086 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list 2087 populated by BL2 in memory to do this. 2088 2089#. Providing runtime firmware services. Currently, BL31 only implements a 2090 subset of the Power State Coordination Interface (PSCI) API as a runtime 2091 service. See :ref:`psci_in_bl31` below for details of porting the PSCI 2092 implementation. 2093 2094#. Optionally passing control to the BL32 image, pre-loaded at a platform- 2095 specific address by BL2. BL31 exports a set of APIs that allow runtime 2096 services to specify the security state in which the next image should be 2097 executed and run the corresponding image. On ARM platforms, BL31 uses the 2098 ``bl_params`` list populated by BL2 in memory to do this. 2099 2100If BL31 is a reset vector, It also needs to handle the reset as specified in 2101section 2.2 before the tasks described above. 2102 2103The following functions must be implemented by the platform port to enable BL31 2104to perform the above tasks. 2105 2106Function : bl31_early_platform_setup2() [mandatory] 2107~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2108 2109:: 2110 2111 Argument : u_register_t, u_register_t, u_register_t, u_register_t 2112 Return : void 2113 2114This function executes with the MMU and data caches disabled. It is only called 2115by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are 2116platform specific. 2117 2118In Arm standard platforms, the arguments received are : 2119 2120 arg0 - The pointer to the head of `bl_params_t` list 2121 which is list of executable images following BL31, 2122 2123 arg1 - Points to load address of SOC_FW_CONFIG if present 2124 except in case of Arm FVP and Juno platform. 2125 2126 In case of Arm FVP and Juno platform, points to load address 2127 of FW_CONFIG. 2128 2129 arg2 - Points to load address of HW_CONFIG if present 2130 2131 arg3 - A special value to verify platform parameters from BL2 to BL31. Not 2132 used in release builds. 2133 2134The function runs through the `bl_param_t` list and extracts the entry point 2135information for BL32 and BL33. It also performs the following: 2136 2137- Initialize a UART (PL011 console), which enables access to the ``printf`` 2138 family of functions in BL31. 2139 2140- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 2141 CCI slave interface corresponding to the cluster that includes the primary 2142 CPU. 2143 2144Function : bl31_plat_arch_setup() [mandatory] 2145~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2146 2147:: 2148 2149 Argument : void 2150 Return : void 2151 2152This function executes with the MMU and data caches disabled. It is only called 2153by the primary CPU. 2154 2155The purpose of this function is to perform any architectural initialization 2156that varies across platforms. 2157 2158On Arm standard platforms, this function enables the MMU. 2159 2160Function : bl31_platform_setup() [mandatory] 2161~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2162 2163:: 2164 2165 Argument : void 2166 Return : void 2167 2168This function may execute with the MMU and data caches enabled if the platform 2169port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 2170called by the primary CPU. 2171 2172The purpose of this function is to complete platform initialization so that both 2173BL31 runtime services and normal world software can function correctly. 2174 2175On Arm standard platforms, this function does the following: 2176 2177- Initialize the generic interrupt controller. 2178 2179 Depending on the GIC driver selected by the platform, the appropriate GICv2 2180 or GICv3 initialization will be done, which mainly consists of: 2181 2182 - Enable secure interrupts in the GIC CPU interface. 2183 - Disable the legacy interrupt bypass mechanism. 2184 - Configure the priority mask register to allow interrupts of all priorities 2185 to be signaled to the CPU interface. 2186 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 2187 - Target all secure SPIs to CPU0. 2188 - Enable these secure interrupts in the GIC distributor. 2189 - Configure all other interrupts as non-secure. 2190 - Enable signaling of secure interrupts in the GIC distributor. 2191 2192- Enable system-level implementation of the generic timer counter through the 2193 memory mapped interface. 2194 2195- Grant access to the system counter timer module 2196 2197- Initialize the power controller device. 2198 2199 In particular, initialise the locks that prevent concurrent accesses to the 2200 power controller device. 2201 2202Function : bl31_plat_runtime_setup() [optional] 2203~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2204 2205:: 2206 2207 Argument : void 2208 Return : void 2209 2210The purpose of this function is allow the platform to perform any BL31 runtime 2211setup just prior to BL31 exit during cold boot. The default weak 2212implementation of this function will invoke ``console_switch_state()`` to switch 2213console output to consoles marked for use in the ``runtime`` state. 2214 2215Function : bl31_plat_get_next_image_ep_info() [mandatory] 2216~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2217 2218:: 2219 2220 Argument : uint32_t 2221 Return : entry_point_info * 2222 2223This function may execute with the MMU and data caches enabled if the platform 2224port does the necessary initializations in ``bl31_plat_arch_setup()``. 2225 2226This function is called by ``bl31_main()`` to retrieve information provided by 2227BL2 for the next image in the security state specified by the argument. BL31 2228uses this information to pass control to that image in the specified security 2229state. This function must return a pointer to the ``entry_point_info`` structure 2230(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2231should return NULL otherwise. 2232 2233Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] 2234~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2235 2236:: 2237 2238 Argument : uintptr_t, size_t *, uintptr_t, size_t 2239 Return : int 2240 2241This function returns the Platform attestation token. 2242 2243The parameters of the function are: 2244 2245 arg0 - A pointer to the buffer where the Platform token should be copied by 2246 this function. The buffer must be big enough to hold the Platform 2247 token. 2248 2249 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2250 function returns the platform token length in this parameter. 2251 2252 arg2 - A pointer to the buffer where the challenge object is stored. 2253 2254 arg3 - The length of the challenge object in bytes. Possible values are 32, 2255 48 and 64. 2256 2257The function returns 0 on success, -EINVAL on failure. 2258 2259Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] 2260~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2261 2262:: 2263 2264 Argument : uintptr_t, size_t *, unsigned int 2265 Return : int 2266 2267This function returns the delegated realm attestation key which will be used to 2268sign Realm attestation token. The API currently only supports P-384 ECC curve 2269key. 2270 2271The parameters of the function are: 2272 2273 arg0 - A pointer to the buffer where the attestation key should be copied 2274 by this function. The buffer must be big enough to hold the 2275 attestation key. 2276 2277 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The 2278 function returns the attestation key length in this parameter. 2279 2280 arg2 - The type of the elliptic curve to which the requested attestation key 2281 belongs. 2282 2283The function returns 0 on success, -EINVAL on failure. 2284 2285Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] 2286~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2287 2288:: 2289 2290 Argument : uintptr_t * 2291 Return : size_t 2292 2293This function returns the size of the shared area between EL3 and RMM (or 0 on 2294failure). A pointer to the shared area (or a NULL pointer on failure) is stored 2295in the pointer passed as argument. 2296 2297Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] 2298~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2299 2300:: 2301 2302 Arguments : rmm_manifest_t *manifest 2303 Return : int 2304 2305When ENABLE_RME is enabled, this function populates a boot manifest for the 2306RMM image and stores it in the area specified by manifest. 2307 2308When ENABLE_RME is disabled, this function is not used. 2309 2310Function : bl31_plat_enable_mmu [optional] 2311~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2312 2313:: 2314 2315 Argument : uint32_t 2316 Return : void 2317 2318This function enables the MMU. The boot code calls this function with MMU and 2319caches disabled. This function should program necessary registers to enable 2320translation, and upon return, the MMU on the calling PE must be enabled. 2321 2322The function must honor flags passed in the first argument. These flags are 2323defined by the translation library, and can be found in the file 2324``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2325 2326On DynamIQ systems, this function must not use stack while enabling MMU, which 2327is how the function in xlat table library version 2 is implemented. 2328 2329Function : plat_init_apkey [optional] 2330~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2331 2332:: 2333 2334 Argument : void 2335 Return : uint128_t 2336 2337This function returns the 128-bit value which can be used to program ARMv8.3 2338pointer authentication keys. 2339 2340The value should be obtained from a reliable source of randomness. 2341 2342This function is only needed if ARMv8.3 pointer authentication is used in the 2343Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. 2344 2345Function : plat_get_syscnt_freq2() [mandatory] 2346~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2347 2348:: 2349 2350 Argument : void 2351 Return : unsigned int 2352 2353This function is used by the architecture setup code to retrieve the counter 2354frequency for the CPU's generic timer. This value will be programmed into the 2355``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2356of the system counter, which is retrieved from the first entry in the frequency 2357modes table. 2358 2359#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] 2360~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2361 2362When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2363bytes) aligned to the cache line boundary that should be allocated per-cpu to 2364accommodate all the bakery locks. 2365 2366If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2367calculates the size of the ``.bakery_lock`` input section, aligns it to the 2368nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2369and stores the result in a linker symbol. This constant prevents a platform 2370from relying on the linker and provide a more efficient mechanism for 2371accessing per-cpu bakery lock information. 2372 2373If this constant is defined and its value is not equal to the value 2374calculated by the linker then a link time assertion is raised. A compile time 2375assertion is raised if the value of the constant is not aligned to the cache 2376line boundary. 2377 2378.. _porting_guide_sdei_requirements: 2379 2380SDEI porting requirements 2381~~~~~~~~~~~~~~~~~~~~~~~~~ 2382 2383The |SDEI| dispatcher requires the platform to provide the following macros 2384and functions, of which some are optional, and some others mandatory. 2385 2386Macros 2387...... 2388 2389Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2390^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2391 2392This macro must be defined to the EL3 exception priority level associated with 2393Normal |SDEI| events on the platform. This must have a higher value 2394(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2395 2396Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2397^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2398 2399This macro must be defined to the EL3 exception priority level associated with 2400Critical |SDEI| events on the platform. This must have a lower value 2401(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2402 2403**Note**: |SDEI| exception priorities must be the lowest among Secure 2404priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must 2405be higher than Normal |SDEI| priority. 2406 2407Functions 2408......... 2409 2410Function: int plat_sdei_validate_entry_point() [optional] 2411^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2412 2413:: 2414 2415 Argument: uintptr_t ep, unsigned int client_mode 2416 Return: int 2417 2418This function validates the entry point address of the event handler provided by 2419the client for both event registration and *Complete and Resume* |SDEI| calls. 2420The function ensures that the address is valid in the client translation regime. 2421 2422The second argument is the exception level that the client is executing in. It 2423can be Non-Secure EL1 or Non-Secure EL2. 2424 2425The function must return ``0`` for successful validation, or ``-1`` upon failure. 2426 2427The default implementation always returns ``0``. On Arm platforms, this function 2428translates the entry point address within the client translation regime and 2429further ensures that the resulting physical address is located in Non-secure 2430DRAM. 2431 2432Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2433^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2434 2435:: 2436 2437 Argument: uint64_t 2438 Argument: unsigned int 2439 Return: void 2440 2441|SDEI| specification requires that a PE comes out of reset with the events 2442masked. The client therefore is expected to call ``PE_UNMASK`` to unmask 2443|SDEI| events on the PE. No |SDEI| events can be dispatched until such 2444time. 2445 2446Should a PE receive an interrupt that was bound to an |SDEI| event while the 2447events are masked on the PE, the dispatcher implementation invokes the function 2448``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2449interrupt and the interrupt ID are passed as parameters. 2450 2451The default implementation only prints out a warning message. 2452 2453.. _porting_guide_trng_requirements: 2454 2455TRNG porting requirements 2456~~~~~~~~~~~~~~~~~~~~~~~~~ 2457 2458The |TRNG| backend requires the platform to provide the following values 2459and mandatory functions. 2460 2461Values 2462...... 2463 2464value: uuid_t plat_trng_uuid [mandatory] 2465^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2466 2467This value must be defined to the UUID of the TRNG backend that is specific to 2468the hardware after ``plat_entropy_setup`` function is called. This value must 2469conform to the SMCCC calling convention; The most significant 32 bits of the 2470UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in 2471w0 indicates failure to get a TRNG source. 2472 2473Functions 2474......... 2475 2476Function: void plat_entropy_setup(void) [mandatory] 2477^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2478 2479:: 2480 2481 Argument: none 2482 Return: none 2483 2484This function is expected to do platform-specific initialization of any TRNG 2485hardware. This may include generating a UUID from a hardware-specific seed. 2486 2487Function: bool plat_get_entropy(uint64_t \*out) [mandatory] 2488^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2489 2490:: 2491 2492 Argument: uint64_t * 2493 Return: bool 2494 Out : when the return value is true, the entropy has been written into the 2495 storage pointed to 2496 2497This function writes entropy into storage provided by the caller. If no entropy 2498is available, it must return false and the storage must not be written. 2499 2500.. _psci_in_bl31: 2501 2502Power State Coordination Interface (in BL31) 2503-------------------------------------------- 2504 2505The TF-A implementation of the PSCI API is based around the concept of a 2506*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2507share some state on which power management operations can be performed as 2508specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2509a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2510*power domains* are arranged in a hierarchical tree structure and each 2511*power domain* can be identified in a system by the cpu index of any CPU that 2512is part of that domain and a *power domain level*. A processing element (for 2513example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2514logical grouping of CPUs that share some state, then level 1 is that group of 2515CPUs (for example, a cluster), and level 2 is a group of clusters (for 2516example, the system). More details on the power domain topology and its 2517organization can be found in :ref:`PSCI Power Domain Tree Structure`. 2518 2519BL31's platform initialization code exports a pointer to the platform-specific 2520power management operations required for the PSCI implementation to function 2521correctly. This information is populated in the ``plat_psci_ops`` structure. The 2522PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2523power management operations on the power domains. For example, the target 2524CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2525handler (if present) is called for the CPU power domain. 2526 2527The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2528describe composite power states specific to a platform. The PSCI implementation 2529defines a generic representation of the power-state parameter, which is an 2530array of local power states where each index corresponds to a power domain 2531level. Each entry contains the local power state the power domain at that power 2532level could enter. It depends on the ``validate_power_state()`` handler to 2533convert the power-state parameter (possibly encoding a composite power state) 2534passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2535 2536The following functions form part of platform port of PSCI functionality. 2537 2538Function : plat_psci_stat_accounting_start() [optional] 2539~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2540 2541:: 2542 2543 Argument : const psci_power_state_t * 2544 Return : void 2545 2546This is an optional hook that platforms can implement for residency statistics 2547accounting before entering a low power state. The ``pwr_domain_state`` field of 2548``state_info`` (first argument) can be inspected if stat accounting is done 2549differently at CPU level versus higher levels. As an example, if the element at 2550index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2551state, special hardware logic may be programmed in order to keep track of the 2552residency statistics. For higher levels (array indices > 0), the residency 2553statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2554default implementation will use PMF to capture timestamps. 2555 2556Function : plat_psci_stat_accounting_stop() [optional] 2557~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2558 2559:: 2560 2561 Argument : const psci_power_state_t * 2562 Return : void 2563 2564This is an optional hook that platforms can implement for residency statistics 2565accounting after exiting from a low power state. The ``pwr_domain_state`` field 2566of ``state_info`` (first argument) can be inspected if stat accounting is done 2567differently at CPU level versus higher levels. As an example, if the element at 2568index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2569state, special hardware logic may be programmed in order to keep track of the 2570residency statistics. For higher levels (array indices > 0), the residency 2571statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2572default implementation will use PMF to capture timestamps. 2573 2574Function : plat_psci_stat_get_residency() [optional] 2575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2576 2577:: 2578 2579 Argument : unsigned int, const psci_power_state_t *, unsigned int 2580 Return : u_register_t 2581 2582This is an optional interface that is is invoked after resuming from a low power 2583state and provides the time spent resident in that low power state by the power 2584domain at a particular power domain level. When a CPU wakes up from suspend, 2585all its parent power domain levels are also woken up. The generic PSCI code 2586invokes this function for each parent power domain that is resumed and it 2587identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2588argument) describes the low power state that the power domain has resumed from. 2589The current CPU is the first CPU in the power domain to resume from the low 2590power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2591CPU in the power domain to suspend and may be needed to calculate the residency 2592for that power domain. 2593 2594Function : plat_get_target_pwr_state() [optional] 2595~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2596 2597:: 2598 2599 Argument : unsigned int, const plat_local_state_t *, unsigned int 2600 Return : plat_local_state_t 2601 2602The PSCI generic code uses this function to let the platform participate in 2603state coordination during a power management operation. The function is passed 2604a pointer to an array of platform specific local power state ``states`` (second 2605argument) which contains the requested power state for each CPU at a particular 2606power domain level ``lvl`` (first argument) within the power domain. The function 2607is expected to traverse this array of upto ``ncpus`` (third argument) and return 2608a coordinated target power state by the comparing all the requested power 2609states. The target power state should not be deeper than any of the requested 2610power states. 2611 2612A weak definition of this API is provided by default wherein it assumes 2613that the platform assigns a local state value in order of increasing depth 2614of the power state i.e. for two power states X & Y, if X < Y 2615then X represents a shallower power state than Y. As a result, the 2616coordinated target local power state for a power domain will be the minimum 2617of the requested local power state values. 2618 2619Function : plat_get_power_domain_tree_desc() [mandatory] 2620~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2621 2622:: 2623 2624 Argument : void 2625 Return : const unsigned char * 2626 2627This function returns a pointer to the byte array containing the power domain 2628topology tree description. The format and method to construct this array are 2629described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI 2630initialization code requires this array to be described by the platform, either 2631statically or dynamically, to initialize the power domain topology tree. In case 2632the array is populated dynamically, then plat_core_pos_by_mpidr() and 2633plat_my_core_pos() should also be implemented suitably so that the topology tree 2634description matches the CPU indices returned by these APIs. These APIs together 2635form the platform interface for the PSCI topology framework. 2636 2637Function : plat_setup_psci_ops() [mandatory] 2638~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2639 2640:: 2641 2642 Argument : uintptr_t, const plat_psci_ops ** 2643 Return : int 2644 2645This function may execute with the MMU and data caches enabled if the platform 2646port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2647called by the primary CPU. 2648 2649This function is called by PSCI initialization code. Its purpose is to let 2650the platform layer know about the warm boot entrypoint through the 2651``sec_entrypoint`` (first argument) and to export handler routines for 2652platform-specific psci power management actions by populating the passed 2653pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2654 2655A description of each member of this structure is given below. Please refer to 2656the Arm FVP specific implementation of these handlers in 2657``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the 2658platform wants to support, the associated operation or operations in this 2659structure must be provided and implemented (Refer section 4 of 2660:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI 2661function in a platform port, the operation should be removed from this 2662structure instead of providing an empty implementation. 2663 2664plat_psci_ops.cpu_standby() 2665........................... 2666 2667Perform the platform-specific actions to enter the standby state for a cpu 2668indicated by the passed argument. This provides a fast path for CPU standby 2669wherein overheads of PSCI state management and lock acquisition is avoided. 2670For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2671the suspend state type specified in the ``power-state`` parameter should be 2672STANDBY and the target power domain level specified should be the CPU. The 2673handler should put the CPU into a low power retention state (usually by 2674issuing a wfi instruction) and ensure that it can be woken up from that 2675state by a normal interrupt. The generic code expects the handler to succeed. 2676 2677plat_psci_ops.pwr_domain_on() 2678............................. 2679 2680Perform the platform specific actions to power on a CPU, specified 2681by the ``MPIDR`` (first argument). The generic code expects the platform to 2682return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. 2683 2684plat_psci_ops.pwr_domain_off_early() [optional] 2685............................................... 2686 2687This optional function performs the platform specific actions to check if 2688powering off the calling CPU and its higher parent power domain levels as 2689indicated by the ``target_state`` (first argument) is possible or allowed. 2690 2691The ``target_state`` encodes the platform coordinated target local power states 2692for the CPU power domain and its parent power domain levels. 2693 2694For this handler, the local power state for the CPU power domain will be a 2695power down state where as it could be either power down, retention or run state 2696for the higher power domain levels depending on the result of state 2697coordination. The generic code expects PSCI_E_DENIED return code if the 2698platform thinks that CPU_OFF should not proceed on the calling CPU. 2699 2700plat_psci_ops.pwr_domain_off() 2701.............................. 2702 2703Perform the platform specific actions to prepare to power off the calling CPU 2704and its higher parent power domain levels as indicated by the ``target_state`` 2705(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2706 2707The ``target_state`` encodes the platform coordinated target local power states 2708for the CPU power domain and its parent power domain levels. The handler 2709needs to perform power management operation corresponding to the local state 2710at each power level. 2711 2712For this handler, the local power state for the CPU power domain will be a 2713power down state where as it could be either power down, retention or run state 2714for the higher power domain levels depending on the result of state 2715coordination. The generic code expects the handler to succeed. 2716 2717plat_psci_ops.pwr_domain_validate_suspend() [optional] 2718...................................................... 2719 2720This is an optional function that is only compiled into the build if the build 2721option ``PSCI_OS_INIT_MODE`` is enabled. 2722 2723If implemented, this function allows the platform to perform platform specific 2724validations based on hardware states. The generic code expects this function to 2725return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or 2726PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. 2727 2728plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] 2729........................................................... 2730 2731This optional function may be used as a performance optimization to replace 2732or complement pwr_domain_suspend() on some platforms. Its calling semantics 2733are identical to pwr_domain_suspend(), except the PSCI implementation only 2734calls this function when suspending to a power down state, and it guarantees 2735that data caches are enabled. 2736 2737When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2738before calling pwr_domain_suspend(). If the target_state corresponds to a 2739power down state and it is safe to perform some or all of the platform 2740specific actions in that function with data caches enabled, it may be more 2741efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2742= 1, data caches remain enabled throughout, and so there is no advantage to 2743moving platform specific actions to this function. 2744 2745plat_psci_ops.pwr_domain_suspend() 2746.................................. 2747 2748Perform the platform specific actions to prepare to suspend the calling 2749CPU and its higher parent power domain levels as indicated by the 2750``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2751API implementation. 2752 2753The ``target_state`` has a similar meaning as described in 2754the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2755target local power states for the CPU power domain and its parent 2756power domain levels. The handler needs to perform power management operation 2757corresponding to the local state at each power level. The generic code 2758expects the handler to succeed. 2759 2760The difference between turning a power domain off versus suspending it is that 2761in the former case, the power domain is expected to re-initialize its state 2762when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2763case, the power domain is expected to save enough state so that it can resume 2764execution by restoring this state when its powered on (see 2765``pwr_domain_suspend_finish()``). 2766 2767When suspending a core, the platform can also choose to power off the GICv3 2768Redistributor and ITS through an implementation-defined sequence. To achieve 2769this safely, the ITS context must be saved first. The architectural part is 2770implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2771sequence is implementation defined and it is therefore the responsibility of 2772the platform code to implement the necessary sequence. Then the GIC 2773Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2774Powering off the Redistributor requires the implementation to support it and it 2775is the responsibility of the platform code to execute the right implementation 2776defined sequence. 2777 2778When a system suspend is requested, the platform can also make use of the 2779``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2780it has saved the context of the Redistributors and ITS of all the cores in the 2781system. The context of the Distributor can be large and may require it to be 2782allocated in a special area if it cannot fit in the platform's global static 2783data, for example in DRAM. The Distributor can then be powered down using an 2784implementation-defined sequence. 2785 2786plat_psci_ops.pwr_domain_pwr_down_wfi() 2787....................................... 2788 2789This is an optional function and, if implemented, is expected to perform 2790platform specific actions including the ``wfi`` invocation which allows the 2791CPU to powerdown. Since this function is invoked outside the PSCI locks, 2792the actions performed in this hook must be local to the CPU or the platform 2793must ensure that races between multiple CPUs cannot occur. 2794 2795The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2796operation and it encodes the platform coordinated target local power states for 2797the CPU power domain and its parent power domain levels. This function must 2798not return back to the caller (by calling wfi in an infinite loop to ensure 2799some CPUs power down mitigations work properly). 2800 2801If this function is not implemented by the platform, PSCI generic 2802implementation invokes ``psci_power_down_wfi()`` for power down. 2803 2804plat_psci_ops.pwr_domain_on_finish() 2805.................................... 2806 2807This function is called by the PSCI implementation after the calling CPU is 2808powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2809It performs the platform-specific setup required to initialize enough state for 2810this CPU to enter the normal world and also provide secure runtime firmware 2811services. 2812 2813The ``target_state`` (first argument) is the prior state of the power domains 2814immediately before the CPU was turned on. It indicates which power domains 2815above the CPU might require initialization due to having previously been in 2816low power states. The generic code expects the handler to succeed. 2817 2818plat_psci_ops.pwr_domain_on_finish_late() [optional] 2819........................................................... 2820 2821This optional function is called by the PSCI implementation after the calling 2822CPU is fully powered on with respective data caches enabled. The calling CPU and 2823the associated cluster are guaranteed to be participating in coherency. This 2824function gives the flexibility to perform any platform-specific actions safely, 2825such as initialization or modification of shared data structures, without the 2826overhead of explicit cache maintainace operations. 2827 2828The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` 2829operation. The generic code expects the handler to succeed. 2830 2831plat_psci_ops.pwr_domain_suspend_finish() 2832......................................... 2833 2834This function is called by the PSCI implementation after the calling CPU is 2835powered on and released from reset in response to an asynchronous wakeup 2836event, for example a timer interrupt that was programmed by the CPU during the 2837``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2838setup required to restore the saved state for this CPU to resume execution 2839in the normal world and also provide secure runtime firmware services. 2840 2841The ``target_state`` (first argument) has a similar meaning as described in 2842the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2843to succeed. 2844 2845If the Distributor, Redistributors or ITS have been powered off as part of a 2846suspend, their context must be restored in this function in the reverse order 2847to how they were saved during suspend sequence. 2848 2849plat_psci_ops.system_off() 2850.......................... 2851 2852This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2853call. It performs the platform-specific system poweroff sequence after 2854notifying the Secure Payload Dispatcher. 2855 2856plat_psci_ops.system_reset() 2857............................ 2858 2859This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2860call. It performs the platform-specific system reset sequence after 2861notifying the Secure Payload Dispatcher. 2862 2863plat_psci_ops.validate_power_state() 2864.................................... 2865 2866This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2867call to validate the ``power_state`` parameter of the PSCI API and if valid, 2868populate it in ``req_state`` (second argument) array as power domain level 2869specific local states. If the ``power_state`` is invalid, the platform must 2870return PSCI_E_INVALID_PARAMS as error, which is propagated back to the 2871normal world PSCI client. 2872 2873plat_psci_ops.validate_ns_entrypoint() 2874...................................... 2875 2876This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2877``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2878parameter passed by the normal world. If the ``entry_point`` is invalid, 2879the platform must return PSCI_E_INVALID_ADDRESS as error, which is 2880propagated back to the normal world PSCI client. 2881 2882plat_psci_ops.get_sys_suspend_power_state() 2883........................................... 2884 2885This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2886call to get the ``req_state`` parameter from platform which encodes the power 2887domain level specific local states to suspend to system affinity level. The 2888``req_state`` will be utilized to do the PSCI state coordination and 2889``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2890enter system suspend. 2891 2892plat_psci_ops.get_pwr_lvl_state_idx() 2893..................................... 2894 2895This is an optional function and, if implemented, is invoked by the PSCI 2896implementation to convert the ``local_state`` (first argument) at a specified 2897``pwr_lvl`` (second argument) to an index between 0 and 2898``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2899supports more than two local power states at each power domain level, that is 2900``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2901local power states. 2902 2903plat_psci_ops.translate_power_state_by_mpidr() 2904.............................................. 2905 2906This is an optional function and, if implemented, verifies the ``power_state`` 2907(second argument) parameter of the PSCI API corresponding to a target power 2908domain. The target power domain is identified by using both ``MPIDR`` (first 2909argument) and the power domain level encoded in ``power_state``. The power domain 2910level specific local states are to be extracted from ``power_state`` and be 2911populated in the ``output_state`` (third argument) array. The functionality 2912is similar to the ``validate_power_state`` function described above and is 2913envisaged to be used in case the validity of ``power_state`` depend on the 2914targeted power domain. If the ``power_state`` is invalid for the targeted power 2915domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this 2916function is not implemented, then the generic implementation relies on 2917``validate_power_state`` function to translate the ``power_state``. 2918 2919This function can also be used in case the platform wants to support local 2920power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY 2921APIs as described in Section 5.18 of `PSCI`_. 2922 2923plat_psci_ops.get_node_hw_state() 2924................................. 2925 2926This is an optional function. If implemented this function is intended to return 2927the power state of a node (identified by the first parameter, the ``MPIDR``) in 2928the power domain topology (identified by the second parameter, ``power_level``), 2929as retrieved from a power controller or equivalent component on the platform. 2930Upon successful completion, the implementation must map and return the final 2931status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2932must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2933appropriate. 2934 2935Implementations are not expected to handle ``power_levels`` greater than 2936``PLAT_MAX_PWR_LVL``. 2937 2938plat_psci_ops.system_reset2() 2939............................. 2940 2941This is an optional function. If implemented this function is 2942called during the ``SYSTEM_RESET2`` call to perform a reset 2943based on the first parameter ``reset_type`` as specified in 2944`PSCI`_. The parameter ``cookie`` can be used to pass additional 2945reset information. If the ``reset_type`` is not supported, the 2946function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2947resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2948and vendor reset can return other PSCI error codes as defined 2949in `PSCI`_. On success this function will not return. 2950 2951plat_psci_ops.write_mem_protect() 2952................................. 2953 2954This is an optional function. If implemented it enables or disables the 2955``MEM_PROTECT`` functionality based on the value of ``val``. 2956A non-zero value enables ``MEM_PROTECT`` and a value of zero 2957disables it. Upon encountering failures it must return a negative value 2958and on success it must return 0. 2959 2960plat_psci_ops.read_mem_protect() 2961................................ 2962 2963This is an optional function. If implemented it returns the current 2964state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2965failures it must return a negative value and on success it must 2966return 0. 2967 2968plat_psci_ops.mem_protect_chk() 2969............................... 2970 2971This is an optional function. If implemented it checks if a memory 2972region defined by a base address ``base`` and with a size of ``length`` 2973bytes is protected by ``MEM_PROTECT``. If the region is protected 2974then it must return 0, otherwise it must return a negative number. 2975 2976.. _porting_guide_imf_in_bl31: 2977 2978Interrupt Management framework (in BL31) 2979---------------------------------------- 2980 2981BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2982generated in either security state and targeted to EL1 or EL2 in the non-secure 2983state or EL3/S-EL1 in the secure state. The design of this framework is 2984described in the :ref:`Interrupt Management Framework` 2985 2986A platform should export the following APIs to support the IMF. The following 2987text briefly describes each API and its implementation in Arm standard 2988platforms. The API implementation depends upon the type of interrupt controller 2989present in the platform. Arm standard platform layer supports both 2990`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2991and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2992FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2993``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more 2994details). 2995 2996See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. 2997 2998Function : plat_interrupt_type_to_line() [mandatory] 2999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3000 3001:: 3002 3003 Argument : uint32_t, uint32_t 3004 Return : uint32_t 3005 3006The Arm processor signals an interrupt exception either through the IRQ or FIQ 3007interrupt line. The specific line that is signaled depends on how the interrupt 3008controller (IC) reports different interrupt types from an execution context in 3009either security state. The IMF uses this API to determine which interrupt line 3010the platform IC uses to signal each type of interrupt supported by the framework 3011from a given security state. This API must be invoked at EL3. 3012 3013The first parameter will be one of the ``INTR_TYPE_*`` values (see 3014:ref:`Interrupt Management Framework`) indicating the target type of the 3015interrupt, the second parameter is the security state of the originating 3016execution context. The return result is the bit position in the ``SCR_EL3`` 3017register of the respective interrupt trap: IRQ=1, FIQ=2. 3018 3019In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 3020configured as FIQs and Non-secure interrupts as IRQs from either security 3021state. 3022 3023In the case of Arm standard platforms using GICv3, the interrupt line to be 3024configured depends on the security state of the execution context when the 3025interrupt is signalled and are as follows: 3026 3027- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 3028 NS-EL0/1/2 context. 3029- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 3030 in the NS-EL0/1/2 context. 3031- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 3032 context. 3033 3034Function : plat_ic_get_pending_interrupt_type() [mandatory] 3035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3036 3037:: 3038 3039 Argument : void 3040 Return : uint32_t 3041 3042This API returns the type of the highest priority pending interrupt at the 3043platform IC. The IMF uses the interrupt type to retrieve the corresponding 3044handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 3045pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 3046``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 3047 3048In the case of Arm standard platforms using GICv2, the *Highest Priority 3049Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 3050the pending interrupt. The type of interrupt depends upon the id value as 3051follows. 3052 3053#. id < 1022 is reported as a S-EL1 interrupt 3054#. id = 1022 is reported as a Non-secure interrupt. 3055#. id = 1023 is reported as an invalid interrupt type. 3056 3057In the case of Arm standard platforms using GICv3, the system register 3058``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 3059is read to determine the id of the pending interrupt. The type of interrupt 3060depends upon the id value as follows. 3061 3062#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 3063#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 3064#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 3065#. All other interrupt id's are reported as EL3 interrupt. 3066 3067Function : plat_ic_get_pending_interrupt_id() [mandatory] 3068~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3069 3070:: 3071 3072 Argument : void 3073 Return : uint32_t 3074 3075This API returns the id of the highest priority pending interrupt at the 3076platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 3077pending. 3078 3079In the case of Arm standard platforms using GICv2, the *Highest Priority 3080Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 3081pending interrupt. The id that is returned by API depends upon the value of 3082the id read from the interrupt controller as follows. 3083 3084#. id < 1022. id is returned as is. 3085#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 3086 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 3087 This id is returned by the API. 3088#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 3089 3090In the case of Arm standard platforms using GICv3, if the API is invoked from 3091EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 3092group 0 Register*, is read to determine the id of the pending interrupt. The id 3093that is returned by API depends upon the value of the id read from the 3094interrupt controller as follows. 3095 3096#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 3097#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 3098 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 3099 Register* is read to determine the id of the group 1 interrupt. This id 3100 is returned by the API as long as it is a valid interrupt id 3101#. If the id is any of the special interrupt identifiers, 3102 ``INTR_ID_UNAVAILABLE`` is returned. 3103 3104When the API invoked from S-EL1 for GICv3 systems, the id read from system 3105register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 3106Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else 3107``INTR_ID_UNAVAILABLE`` is returned. 3108 3109Function : plat_ic_acknowledge_interrupt() [mandatory] 3110~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3111 3112:: 3113 3114 Argument : void 3115 Return : uint32_t 3116 3117This API is used by the CPU to indicate to the platform IC that processing of 3118the highest pending interrupt has begun. It should return the raw, unmodified 3119value obtained from the interrupt controller when acknowledging an interrupt. 3120The actual interrupt number shall be extracted from this raw value using the API 3121`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. 3122 3123This function in Arm standard platforms using GICv2, reads the *Interrupt 3124Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 3125priority pending interrupt from pending to active in the interrupt controller. 3126It returns the value read from the ``GICC_IAR``, unmodified. 3127 3128In the case of Arm standard platforms using GICv3, if the API is invoked 3129from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 3130Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 3131reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 3132group 1*. The read changes the state of the highest pending interrupt from 3133pending to active in the interrupt controller. The value read is returned 3134unmodified. 3135 3136The TSP uses this API to start processing of the secure physical timer 3137interrupt. 3138 3139Function : plat_ic_end_of_interrupt() [mandatory] 3140~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3141 3142:: 3143 3144 Argument : uint32_t 3145 Return : void 3146 3147This API is used by the CPU to indicate to the platform IC that processing of 3148the interrupt corresponding to the id (passed as the parameter) has 3149finished. The id should be the same as the id returned by the 3150``plat_ic_acknowledge_interrupt()`` API. 3151 3152Arm standard platforms write the id to the *End of Interrupt Register* 3153(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 3154system register in case of GICv3 depending on where the API is invoked from, 3155EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 3156controller. 3157 3158The TSP uses this API to finish processing of the secure physical timer 3159interrupt. 3160 3161Function : plat_ic_get_interrupt_type() [mandatory] 3162~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3163 3164:: 3165 3166 Argument : uint32_t 3167 Return : uint32_t 3168 3169This API returns the type of the interrupt id passed as the parameter. 3170``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 3171interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 3172returned depending upon how the interrupt has been configured by the platform 3173IC. This API must be invoked at EL3. 3174 3175Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 3176and Non-secure interrupts as Group1 interrupts. It reads the group value 3177corresponding to the interrupt id from the relevant *Interrupt Group Register* 3178(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 3179 3180In the case of Arm standard platforms using GICv3, both the *Interrupt Group 3181Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 3182(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 3183as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 3184 3185Common helper functions 3186----------------------- 3187Function : elx_panic() 3188~~~~~~~~~~~~~~~~~~~~~~ 3189 3190:: 3191 3192 Argument : void 3193 Return : void 3194 3195This API is called from assembly files when reporting a critical failure 3196that has occured in lower EL and is been trapped in EL3. This call 3197**must not** return. 3198 3199Function : el3_panic() 3200~~~~~~~~~~~~~~~~~~~~~~ 3201 3202:: 3203 3204 Argument : void 3205 Return : void 3206 3207This API is called from assembly files when encountering a critical failure that 3208cannot be recovered from. This function assumes that it is invoked from a C 3209runtime environment i.e. valid stack exists. This call **must not** return. 3210 3211Function : panic() 3212~~~~~~~~~~~~~~~~~~ 3213 3214:: 3215 3216 Argument : void 3217 Return : void 3218 3219This API called from C files when encountering a critical failure that cannot 3220be recovered from. This function in turn prints backtrace (if enabled) and calls 3221el3_panic(). This call **must not** return. 3222 3223Crash Reporting mechanism (in BL31) 3224----------------------------------- 3225 3226BL31 implements a crash reporting mechanism which prints the various registers 3227of the CPU to enable quick crash analysis and debugging. This mechanism relies 3228on the platform implementing ``plat_crash_console_init``, 3229``plat_crash_console_putc`` and ``plat_crash_console_flush``. 3230 3231The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample 3232implementation of all of them. Platforms may include this file to their 3233makefiles in order to benefit from them. By default, they will cause the crash 3234output to be routed over the normal console infrastructure and get printed on 3235consoles configured to output in crash state. ``console_set_scope()`` can be 3236used to control whether a console is used for crash output. 3237 3238.. note:: 3239 Platforms are responsible for making sure that they only mark consoles for 3240 use in the crash scope that are able to support this, i.e. that are written 3241 in assembly and conform with the register clobber rules for putc() 3242 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. 3243 3244In some cases (such as debugging very early crashes that happen before the 3245normal boot console can be set up), platforms may want to control crash output 3246more explicitly. These platforms may instead provide custom implementations for 3247these. They are executed outside of a C environment and without a stack. Many 3248console drivers provide functions named ``console_xxx_core_init/putc/flush`` 3249that are designed to be used by these functions. See Arm platforms (like juno) 3250for an example of this. 3251 3252Function : plat_crash_console_init [mandatory] 3253~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3254 3255:: 3256 3257 Argument : void 3258 Return : int 3259 3260This API is used by the crash reporting mechanism to initialize the crash 3261console. It must only use the general purpose registers x0 through x7 to do the 3262initialization and returns 1 on success. 3263 3264Function : plat_crash_console_putc [mandatory] 3265~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3266 3267:: 3268 3269 Argument : int 3270 Return : int 3271 3272This API is used by the crash reporting mechanism to print a character on the 3273designated crash console. It must only use general purpose registers x1 and 3274x2 to do its work. The parameter and the return value are in general purpose 3275register x0. 3276 3277Function : plat_crash_console_flush [mandatory] 3278~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3279 3280:: 3281 3282 Argument : void 3283 Return : void 3284 3285This API is used by the crash reporting mechanism to force write of all buffered 3286data on the designated crash console. It should only use general purpose 3287registers x0 through x5 to do its work. 3288 3289Function : plat_setup_early_console [optional] 3290~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3291 3292:: 3293 3294 Argument : void 3295 Return : void 3296 3297This API is used to setup the early console, it is required only if the flag 3298``EARLY_CONSOLE`` is enabled. 3299 3300.. _External Abort handling and RAS Support: 3301 3302External Abort handling and RAS Support 3303--------------------------------------- 3304 3305Function : plat_ea_handler 3306~~~~~~~~~~~~~~~~~~~~~~~~~~ 3307 3308:: 3309 3310 Argument : int 3311 Argument : uint64_t 3312 Argument : void * 3313 Argument : void * 3314 Argument : uint64_t 3315 Return : void 3316 3317This function is invoked by the runtime exception handling framework for the 3318platform to handle an External Abort received at EL3. The intention of the 3319function is to attempt to resolve the cause of External Abort and return; 3320if that's not possible then an orderly shutdown of the system is initiated. 3321 3322The first parameter (``int ea_reason``) indicates the reason for External Abort. 3323Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 3324 3325The second parameter (``uint64_t syndrome``) is the respective syndrome 3326presented to EL3 after having received the External Abort. Depending on the 3327nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 3328can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 3329 3330The third parameter (``void *cookie``) is unused for now. The fourth parameter 3331(``void *handle``) is a pointer to the preempted context. The fifth parameter 3332(``uint64_t flags``) indicates the preempted security state. These parameters 3333are received from the top-level exception handler. 3334 3335This function must be implemented if a platform expects Firmware First handling 3336of External Aborts. 3337 3338Function : plat_handle_uncontainable_ea 3339~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3340 3341:: 3342 3343 Argument : int 3344 Argument : uint64_t 3345 Return : void 3346 3347This function is invoked by the RAS framework when an External Abort of 3348Uncontainable type is received at EL3. Due to the critical nature of 3349Uncontainable errors, the intention of this function is to initiate orderly 3350shutdown of the system, and is not expected to return. 3351 3352This function must be implemented in assembly. 3353 3354The first and second parameters are the same as that of ``plat_ea_handler``. 3355 3356The default implementation of this function calls 3357``report_unhandled_exception``. 3358 3359Function : plat_handle_double_fault 3360~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3361 3362:: 3363 3364 Argument : int 3365 Argument : uint64_t 3366 Return : void 3367 3368This function is invoked by the RAS framework when another External Abort is 3369received at EL3 while one is already being handled. I.e., a call to 3370``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 3371this function is to initiate orderly shutdown of the system, and is not expected 3372recover or return. 3373 3374This function must be implemented in assembly. 3375 3376The first and second parameters are the same as that of ``plat_ea_handler``. 3377 3378The default implementation of this function calls 3379``report_unhandled_exception``. 3380 3381Function : plat_handle_el3_ea 3382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3383 3384:: 3385 3386 Return : void 3387 3388This function is invoked when an External Abort is received while executing in 3389EL3. Due to its critical nature, the intention of this function is to initiate 3390orderly shutdown of the system, and is not expected recover or return. 3391 3392This function must be implemented in assembly. 3393 3394The default implementation of this function calls 3395``report_unhandled_exception``. 3396 3397Function : plat_handle_rng_trap 3398~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3399 3400:: 3401 3402 Argument : uint64_t 3403 Argument : cpu_context_t * 3404 Return : int 3405 3406This function is invoked by BL31's exception handler when there is a synchronous 3407system register trap caused by access to the RNDR or RNDRRS registers. It allows 3408platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to 3409emulate those system registers by returing back some entropy to the lower EL. 3410 3411The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3412syndrome register, which encodes the instruction that was trapped. The interesting 3413information in there is the target register (``get_sysreg_iss_rt()``). 3414 3415The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3416lower exception level, at the time when the execution of the ``mrs`` instruction 3417was trapped. Its content can be changed, to put the entropy into the target 3418register. 3419 3420The return value indicates how to proceed: 3421 3422- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3423- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3424 to the same instruction, so its execution will be repeated. 3425- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3426 to the next instruction. 3427 3428This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. 3429 3430Function : plat_handle_impdef_trap 3431~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3432 3433:: 3434 3435 Argument : uint64_t 3436 Argument : cpu_context_t * 3437 Return : int 3438 3439This function is invoked by BL31's exception handler when there is a synchronous 3440system register trap caused by access to the implementation defined registers. 3441It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system 3442registers choosing to program bits of their choice. 3443 3444The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 3445syndrome register, which encodes the instruction that was trapped. 3446 3447The second parameter (``cpu_context_t *ctx``) represents the CPU state in the 3448lower exception level, at the time when the execution of the ``mrs`` instruction 3449was trapped. 3450 3451The return value indicates how to proceed: 3452 3453- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. 3454- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return 3455 to the same instruction, so its execution will be repeated. 3456- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return 3457 to the next instruction. 3458 3459This function needs to be implemented by a platform if it enables 3460IMPDEF_SYSREG_TRAP. 3461 3462Build flags 3463----------- 3464 3465There are some build flags which can be defined by the platform to control 3466inclusion or exclusion of certain BL stages from the FIP image. These flags 3467need to be defined in the platform makefile which will get included by the 3468build system. 3469 3470- **NEED_BL33** 3471 By default, this flag is defined ``yes`` by the build system and ``BL33`` 3472 build option should be supplied as a build option. The platform has the 3473 option of excluding the BL33 image in the ``fip`` image by defining this flag 3474 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 3475 are used, this flag will be set to ``no`` automatically. 3476 3477- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** 3478 By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, 3479 if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and 3480 ARM_ARCH_MINOR then mandatory Architectural features available for that Arch 3481 version will be enabled by default and any optional Arch feature supported by 3482 the Architecture and available in TF-A can be enabled from platform specific 3483 makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory 3484 and optional Arch specific features. 3485 3486Platform include paths 3487---------------------- 3488 3489Platforms are allowed to add more include paths to be passed to the compiler. 3490The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in 3491particular for the file ``platform_def.h``. 3492 3493Example: 3494 3495.. code:: c 3496 3497 PLAT_INCLUDES += -Iinclude/plat/myplat/include 3498 3499C Library 3500--------- 3501 3502To avoid subtle toolchain behavioral dependencies, the header files provided 3503by the compiler are not used. The software is built with the ``-nostdinc`` flag 3504to ensure no headers are included from the toolchain inadvertently. Instead the 3505required headers are included in the TF-A source tree. The library only 3506contains those C library definitions required by the local implementation. If 3507more functionality is required, the needed library functions will need to be 3508added to the local implementation. 3509 3510Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 3511been written specifically for TF-A. Some implementation files have been obtained 3512from `FreeBSD`_, others have been written specifically for TF-A as well. The 3513files can be found in ``include/lib/libc`` and ``lib/libc``. 3514 3515SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources 3516can be obtained from http://github.com/freebsd/freebsd. 3517 3518Storage abstraction layer 3519------------------------- 3520 3521In order to improve platform independence and portability a storage abstraction 3522layer is used to load data from non-volatile platform storage. Currently 3523storage access is only required by BL1 and BL2 phases and performed inside the 3524``load_image()`` function in ``bl_common.c``. 3525 3526.. uml:: resources/diagrams/plantuml/io_framework_usage_overview.puml 3527 3528It is mandatory to implement at least one storage driver. For the Arm 3529development platforms the Firmware Image Package (FIP) driver is provided as 3530the default means to load data from storage (see :ref:`firmware_design_fip`). 3531The storage layer is described in the header file 3532``include/drivers/io/io_storage.h``. The implementation of the common library is 3533in ``drivers/io/io_storage.c`` and the driver files are located in 3534``drivers/io/``. 3535 3536.. uml:: resources/diagrams/plantuml/io_arm_class_diagram.puml 3537 3538Each IO driver must provide ``io_dev_*`` structures, as described in 3539``drivers/io/io_driver.h``. These are returned via a mandatory registration 3540function that is called on platform initialization. The semi-hosting driver 3541implementation in ``io_semihosting.c`` can be used as an example. 3542 3543Each platform should register devices and their drivers via the storage 3544abstraction layer. These drivers then need to be initialized by bootloader 3545phases as required in their respective ``blx_platform_setup()`` functions. 3546 3547.. uml:: resources/diagrams/plantuml/io_dev_registration.puml 3548 3549The storage abstraction layer provides mechanisms (``io_dev_init()``) to 3550initialize storage devices before IO operations are called. 3551 3552.. uml:: resources/diagrams/plantuml/io_dev_init_and_check.puml 3553 3554The basic operations supported by the layer 3555include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3556Drivers do not have to implement all operations, but each platform must 3557provide at least one driver for a device capable of supporting generic 3558operations such as loading a bootloader image. 3559 3560The current implementation only allows for known images to be loaded by the 3561firmware. These images are specified by using their identifiers, as defined in 3562``include/plat/common/common_def.h`` (or a separate header file included from 3563there). The platform layer (``plat_get_image_source()``) then returns a reference 3564to a device and a driver-specific ``spec`` which will be understood by the driver 3565to allow access to the image data. 3566 3567The layer is designed in such a way that is it possible to chain drivers with 3568other drivers. For example, file-system drivers may be implemented on top of 3569physical block devices, both represented by IO devices with corresponding 3570drivers. In such a case, the file-system "binding" with the block device may 3571be deferred until the file-system device is initialised. 3572 3573The abstraction currently depends on structures being statically allocated 3574by the drivers and callers, as the system does not yet provide a means of 3575dynamically allocating memory. This may also have the affect of limiting the 3576amount of open resources per driver. 3577 3578Measured Boot Platform Interface 3579-------------------------------- 3580 3581Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer 3582to :ref:`Measured Boot Design` for more details. 3583 3584-------------- 3585 3586*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.* 3587 3588.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 3589.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3590.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3591.. _FreeBSD: https://www.freebsd.org 3592.. _SCC: http://www.simple-cc.org/ 3593.. _DRTM: https://developer.arm.com/documentation/den0113/a 3594