1Allwinner ARMv8 SoCs 2==================== 3 4Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner 5SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and 6PSCI runtime services. 7 8Building TF-A 9------------- 10 11There is one build target per supported SoC: 12 13+------+-------------------+ 14| SoC | TF-A build target | 15+======+===================+ 16| A64 | sun50i_a64 | 17+------+-------------------+ 18| H5 | sun50i_a64 | 19+------+-------------------+ 20| H6 | sun50i_h6 | 21+------+-------------------+ 22| H616 | sun50i_h616 | 23+------+-------------------+ 24| H313 | sun50i_h616 | 25+------+-------------------+ 26| T507 | sun50i_h616 | 27+------+-------------------+ 28| R329 | sun50i_r329 | 29+------+-------------------+ 30 31To build with the default settings for a particular SoC: 32 33.. code:: shell 34 35 make CROSS_COMPILE=aarch64-linux-gnu- PLAT=<build target> DEBUG=1 36 37So for instance to build for a board with the Allwinner A64 SoC:: 38 39 make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 40 41Platform-specific build options 42~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 43 44The default build options should generate a working firmware image. There are 45some build options that allow to fine-tune the firmware, or to disable support 46for optional features. 47 48- ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown 49 and powerup sequence by BL31. This requires either support for a code snippet 50 to be loaded into the ARISC SCP (A64, H5), or the power sequence control 51 registers to be programmed directly (H6, H616). This supports only basic 52 control, like core on/off and system off/reset. 53 This option defaults to 1. If an active SCP supporting the SCPI protocol 54 is detected at runtime, this control scheme will be ignored, and SCPI 55 will be used instead, unless support has been explicitly disabled. 56 57- ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and 58 powerup sequence by talking to the SCP processor via the SCPI protocol. 59 This allows more advanced power saving techniques, like suspend to RAM. 60 This option defaults to 1 on SoCs that feature an SCP. If no SCP firmware 61 using the SCPI protocol is detected, the native sequence will be used 62 instead. If both native and SCPI methods are included, SCPI will be favoured 63 if SCP support is detected. 64 65- ``SUNXI_SETUP_REGULATORS`` : On SoCs that typically ship with a PMIC 66 power management controller, BL31 tries to set up all needed power rails, 67 programming them to their respective voltages. That allows bootloader 68 software like U-Boot to ignore power control via the PMIC. 69 This setting defaults to 1. In some situations that enables too many 70 regulators, or some regulators need to be enabled in a very specific 71 sequence. To avoid problems with those boards, ``SUNXI_SETUP_REGULATORS`` 72 can bet set to ``0`` on the build command line, to skip the PMIC setup 73 entirely. Any bootloader or OS would need to setup the PMIC on its own then. 74 75Installation 76------------ 77 78U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot). 79Loading is done from SD card, eMMC or SPI flash, also via an USB debug 80interface (FEL). 81 82After building bl31.bin, the binary must be fed to the U-Boot build system 83to include it in the FIT image that the SPL loader will process. 84bl31.bin can be either copied (or sym-linked) into U-Boot's root directory, 85or the environment variable BL31 must contain the binary's path. 86See the respective `U-Boot documentation`_ for more details. 87 88.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64 89 90Memory layout 91------------- 92 93A64, H5 and H6 SoCs 94~~~~~~~~~~~~~~~~~~~ 95 96BL31 lives in SRAM A2, which is documented to be accessible from secure 97world only. Since this SRAM region is very limited (48 KB), we take 98several measures to reduce memory consumption. One of them is to confine 99BL31 to only 28 bits of virtual address space, which reduces the number 100of required page tables (each occupying 4KB of memory). 101The mapping we use on those SoCs is as follows: 102 103:: 104 105 0 64K 16M 1GB 1G+160M physical address 106 +-+------+-+---+------+--...---+-------+----+------+---------- 107 |B| |S|///| |//...///| |////| | 108 |R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ... 109 |O| |P|///| MMIO |//...///| DRAM |////| | 110 |M| | |///| |//...///| (32M) |////| | 111 +-+------+-+---+------+--...---+-------+----+------+---------- 112 | | | | | | / / / / 113 | | | | | | / / / / 114 | | | | | | / / / / 115 | | | | | | / // / 116 | | | | | | / / / 117 +-+------+-+---+------+--+-------+------+ 118 |B| |S|///| |//| | | 119 |R| SRAM |C|///| dev |//| sec | BL33 | 120 |O| |P|///| MMIO |//| DRAM | | 121 |M| | |///| |//| | | 122 +-+------+-+---+------+--+-------+------+ 123 0 64K 16M 160M 192M 256M virtual address 124 125 126H616 SoC 127~~~~~~~~ 128 129The H616 lacks the secure SRAM region present on the other SoCs, also 130lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to 131run from DRAM, which prevents our compressed virtual memory map described 132above. Since running in DRAM also lifts the restriction of the limited 133SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual 134address space. So the virtual addresses used in BL31 match the physical 135addresses as presented above. 136 137Trusted OS dispatcher 138--------------------- 139 140One can boot Trusted OS(OP-TEE OS, bl32 image) along side bl31 image on Allwinner A64. 141 142In order to include the 'opteed' dispatcher in the image, pass 'SPD=opteed' on the command line 143while compiling the bl31 image and make sure the loader (SPL) loads the Trusted OS binary to 144the beginning of DRAM (0x40000000). 145