1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL32_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        ASSERT(. == ALIGN(PAGE_SIZE),
29        ".text address is not aligned on a page boundary.");
30
31        __TEXT_START__ = .;
32
33        *tsp_entrypoint.o(.text*)
34        *(.text*)
35        *(.vectors)
36        __TEXT_END_UNALIGNED__ = .;
37
38        . = ALIGN(PAGE_SIZE);
39
40        __TEXT_END__ = .;
41    } >RAM
42
43    .rodata . : {
44        __RODATA_START__ = .;
45
46        *(.rodata*)
47
48        RODATA_COMMON
49
50        __RODATA_END_UNALIGNED__ = .;
51        . = ALIGN(PAGE_SIZE);
52
53        __RODATA_END__ = .;
54    } >RAM
55#else /* SEPARATE_CODE_AND_RODATA */
56    .ro . : {
57        ASSERT(. == ALIGN(PAGE_SIZE),
58        ".ro address is not aligned on a page boundary.");
59
60        __RO_START__ = .;
61
62        *tsp_entrypoint.o(.text*)
63        *(.text*)
64        *(.rodata*)
65
66        RODATA_COMMON
67
68        *(.vectors)
69
70        __RO_END_UNALIGNED__ = .;
71
72        /*
73         * Memory page(s) mapped to this section will be marked as read-only,
74         * executable. No RW data from the next section must creep in. Ensure
75         * that the rest of the current memory page is unused.
76         */
77        . = ALIGN(PAGE_SIZE);
78
79        __RO_END__ = .;
80    } >RAM
81#endif /* SEPARATE_CODE_AND_RODATA */
82
83    __RW_START__ = .;
84
85    DATA_SECTION >RAM
86    RELA_SECTION >RAM
87
88#ifdef TSP_PROGBITS_LIMIT
89    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
90#endif /* TSP_PROGBITS_LIMIT */
91
92    STACK_SECTION >RAM
93    BSS_SECTION >RAM
94    XLAT_TABLE_SECTION >RAM
95
96#if USE_COHERENT_MEM
97    /*
98     * The base address of the coherent memory section must be page-aligned to
99     * guarantee that the coherent data are stored on their own pages and are
100     * not mixed with normal data. This is required to set up the correct memory
101     * attributes for the coherent data page tables.
102     */
103    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
104        __COHERENT_RAM_START__ = .;
105        *(.tzfw_coherent_mem)
106        __COHERENT_RAM_END_UNALIGNED__ = .;
107
108        /*
109         * Memory page(s) mapped to this section will be marked as device
110         * memory. No other unexpected data must creep in. Ensure that the rest
111         * of the current memory page is unused.
112         */
113        . = ALIGN(PAGE_SIZE);
114
115        __COHERENT_RAM_END__ = .;
116    } >RAM
117#endif /* USE_COHERENT_MEM */
118
119    __RW_END__ = .;
120    __BL32_END__ = .;
121
122    /DISCARD/ : {
123        *(.dynsym .dynstr .hash .gnu.hash)
124    }
125
126    __BSS_SIZE__ = SIZEOF(.bss);
127
128#if USE_COHERENT_MEM
129    __COHERENT_RAM_UNALIGNED_SIZE__ =
130        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
131#endif /* USE_COHERENT_MEM */
132
133    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
134    RAM_REGION_END = .;
135}
136