1/*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <arch.h>
10#include <common/bl_common.h>
11#include <el3_common_macros.S>
12#include <lib/pmf/aarch64/pmf_asm_macros.S>
13#include <lib/runtime_instr.h>
14#include <lib/xlat_tables/xlat_mmu_helpers.h>
15
16	.globl	bl31_entrypoint
17	.globl	bl31_warm_entrypoint
18
19	/* -----------------------------------------------------
20	 * bl31_entrypoint() is the cold boot entrypoint,
21	 * executed only by the primary cpu.
22	 * -----------------------------------------------------
23	 */
24
25func bl31_entrypoint
26	/* ---------------------------------------------------------------
27	 * Stash the previous bootloader arguments x0 - x3 for later use.
28	 * ---------------------------------------------------------------
29	 */
30	mov	x20, x0
31	mov	x21, x1
32	mov	x22, x2
33	mov	x23, x3
34
35#if !RESET_TO_BL31
36	/* ---------------------------------------------------------------------
37	 * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
38	 * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
39	 * and primary/secondary CPU logic should not be executed in this case.
40	 *
41	 * Also, assume that the previous bootloader has already initialised the
42	 * SCTLR_EL3, including the endianness, and has initialised the memory.
43	 * ---------------------------------------------------------------------
44	 */
45	el3_entrypoint_common					\
46		_init_sctlr=0					\
47		_warm_boot_mailbox=0				\
48		_secondary_cold_boot=0				\
49		_init_memory=0					\
50		_init_c_runtime=1				\
51		_exception_vectors=runtime_exceptions		\
52		_pie_fixup_size=BL31_LIMIT - BL31_BASE
53#else
54
55	/* ---------------------------------------------------------------------
56	 * For RESET_TO_BL31 systems which have a programmable reset address,
57	 * bl31_entrypoint() is executed only on the cold boot path so we can
58	 * skip the warm boot mailbox mechanism.
59	 * ---------------------------------------------------------------------
60	 */
61	el3_entrypoint_common					\
62		_init_sctlr=1					\
63		_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS	\
64		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU	\
65		_init_memory=1					\
66		_init_c_runtime=1				\
67		_exception_vectors=runtime_exceptions		\
68		_pie_fixup_size=BL31_LIMIT - BL31_BASE
69#endif /* RESET_TO_BL31 */
70
71	/* --------------------------------------------------------------------
72	 * Perform BL31 setup
73	 * --------------------------------------------------------------------
74	 */
75	mov	x0, x20
76	mov	x1, x21
77	mov	x2, x22
78	mov	x3, x23
79	bl	bl31_setup
80
81#if ENABLE_PAUTH
82	/* --------------------------------------------------------------------
83	 * Program APIAKey_EL1 and enable pointer authentication
84	 * --------------------------------------------------------------------
85	 */
86	bl	pauth_init_enable_el3
87#endif /* ENABLE_PAUTH */
88
89	/* --------------------------------------------------------------------
90	 * Jump to main function
91	 * --------------------------------------------------------------------
92	 */
93	bl	bl31_main
94
95	/* --------------------------------------------------------------------
96	 * Clean the .data & .bss sections to main memory. This ensures
97	 * that any global data which was initialised by the primary CPU
98	 * is visible to secondary CPUs before they enable their data
99	 * caches and participate in coherency.
100	 * --------------------------------------------------------------------
101	 */
102	adrp	x0, __DATA_START__
103	add	x0, x0, :lo12:__DATA_START__
104	adrp	x1, __DATA_END__
105	add	x1, x1, :lo12:__DATA_END__
106	sub	x1, x1, x0
107	bl	clean_dcache_range
108
109	adrp	x0, __BSS_START__
110	add	x0, x0, :lo12:__BSS_START__
111	adrp	x1, __BSS_END__
112	add	x1, x1, :lo12:__BSS_END__
113	sub	x1, x1, x0
114	bl	clean_dcache_range
115
116	b	el3_exit
117endfunc bl31_entrypoint
118
119	/* --------------------------------------------------------------------
120	 * This CPU has been physically powered up. It is either resuming from
121	 * suspend or has simply been turned on. In both cases, call the BL31
122	 * warmboot entrypoint
123	 * --------------------------------------------------------------------
124	 */
125func bl31_warm_entrypoint
126#if ENABLE_RUNTIME_INSTRUMENTATION
127
128	/*
129	 * This timestamp update happens with cache off.  The next
130	 * timestamp collection will need to do cache maintenance prior
131	 * to timestamp update.
132	 */
133	pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
134	mrs	x1, cntpct_el0
135	str	x1, [x0]
136#endif
137
138	/*
139	 * On the warm boot path, most of the EL3 initialisations performed by
140	 * 'el3_entrypoint_common' must be skipped:
141	 *
142	 *  - Only when the platform bypasses the BL1/BL31 entrypoint by
143	 *    programming the reset address do we need to initialise SCTLR_EL3.
144	 *    In other cases, we assume this has been taken care by the
145	 *    entrypoint code.
146	 *
147	 *  - No need to determine the type of boot, we know it is a warm boot.
148	 *
149	 *  - Do not try to distinguish between primary and secondary CPUs, this
150	 *    notion only exists for a cold boot.
151	 *
152	 *  - No need to initialise the memory or the C runtime environment,
153	 *    it has been done once and for all on the cold boot path.
154	 */
155	el3_entrypoint_common					\
156		_init_sctlr=PROGRAMMABLE_RESET_ADDRESS		\
157		_warm_boot_mailbox=0				\
158		_secondary_cold_boot=0				\
159		_init_memory=0					\
160		_init_c_runtime=0				\
161		_exception_vectors=runtime_exceptions		\
162		_pie_fixup_size=0
163
164	/*
165	 * We're about to enable MMU and participate in PSCI state coordination.
166	 *
167	 * The PSCI implementation invokes platform routines that enable CPUs to
168	 * participate in coherency. On a system where CPUs are not
169	 * cache-coherent without appropriate platform specific programming,
170	 * having caches enabled until such time might lead to coherency issues
171	 * (resulting from stale data getting speculatively fetched, among
172	 * others). Therefore we keep data caches disabled even after enabling
173	 * the MMU for such platforms.
174	 *
175	 * On systems with hardware-assisted coherency, or on single cluster
176	 * platforms, such platform specific programming is not required to
177	 * enter coherency (as CPUs already are); and there's no reason to have
178	 * caches disabled either.
179	 */
180#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
181	mov	x0, xzr
182#else
183	mov	x0, #DISABLE_DCACHE
184#endif
185	bl	bl31_plat_enable_mmu
186
187#if ENABLE_RME
188	/*
189	 * At warm boot GPT data structures have already been initialized in RAM
190	 * but the sysregs for this CPU need to be initialized. Note that the GPT
191	 * accesses are controlled attributes in GPCCR and do not depend on the
192	 * SCR_EL3.C bit.
193	 */
194	bl	gpt_enable
195	cbz	x0, 1f
196	no_ret plat_panic_handler
1971:
198#endif
199
200#if ENABLE_PAUTH
201	/* --------------------------------------------------------------------
202	 * Program APIAKey_EL1 and enable pointer authentication
203	 * --------------------------------------------------------------------
204	 */
205	bl	pauth_init_enable_el3
206#endif /* ENABLE_PAUTH */
207
208	bl	psci_warmboot_entrypoint
209
210#if ENABLE_RUNTIME_INSTRUMENTATION
211	pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
212	mov	x19, x0
213
214	/*
215	 * Invalidate before updating timestamp to ensure previous timestamp
216	 * updates on the same cache line with caches disabled are properly
217	 * seen by the same core. Without the cache invalidate, the core might
218	 * write into a stale cache line.
219	 */
220	mov	x1, #PMF_TS_SIZE
221	mov	x20, x30
222	bl	inv_dcache_range
223	mov	x30, x20
224
225	mrs	x0, cntpct_el0
226	str	x0, [x19]
227#endif
228	b	el3_exit
229endfunc bl31_warm_entrypoint
230