1/*
2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9#include <common/bl_common.ld.h>
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
13OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
14ENTRY(bl2u_entrypoint)
15
16MEMORY {
17    RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
18}
19
20SECTIONS {
21    RAM_REGION_START = ORIGIN(RAM);
22    RAM_REGION_LENGTH = LENGTH(RAM);
23    . = BL2U_BASE;
24
25    ASSERT(. == ALIGN(PAGE_SIZE),
26        "BL2U_BASE address is not aligned on a page boundary.")
27
28#if SEPARATE_CODE_AND_RODATA
29    .text . : {
30        ASSERT(. == ALIGN(PAGE_SIZE),
31        ".text address is not aligned on a page boundary.");
32
33        __TEXT_START__ = .;
34
35        *bl2u_entrypoint.o(.text*)
36        *(SORT_BY_ALIGNMENT(.text*))
37        *(.vectors)
38        __TEXT_END_UNALIGNED__ = .;
39
40        . = ALIGN(PAGE_SIZE);
41
42        __TEXT_END__ = .;
43    } >RAM
44
45    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
46    .ARM.extab . : {
47        *(.ARM.extab* .gnu.linkonce.armextab.*)
48    } >RAM
49
50    .ARM.exidx . : {
51        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
52    } >RAM
53
54    .rodata . : {
55        __RODATA_START__ = .;
56        *(SORT_BY_ALIGNMENT(.rodata*))
57
58        RODATA_COMMON
59
60        __RODATA_END_UNALIGNED__ = .;
61        . = ALIGN(PAGE_SIZE);
62        __RODATA_END__ = .;
63    } >RAM
64#else /* SEPARATE_CODE_AND_RODATA */
65    .ro . : {
66        ASSERT(. == ALIGN(PAGE_SIZE),
67        ".ro address is not aligned on a page boundary.");
68
69        __RO_START__ = .;
70
71        *bl2u_entrypoint.o(.text*)
72        *(SORT_BY_ALIGNMENT(.text*))
73        *(SORT_BY_ALIGNMENT(.rodata*))
74
75        RODATA_COMMON
76
77        *(.vectors)
78
79        __RO_END_UNALIGNED__ = .;
80
81        /*
82         * Memory page(s) mapped to this section will be marked as read-only,
83         * executable. No RW data from the next section must creep in. Ensure
84         * that the rest of the current memory page is unused.
85         */
86        . = ALIGN(PAGE_SIZE);
87
88        __RO_END__ = .;
89    } >RAM
90#endif /* SEPARATE_CODE_AND_RODATA */
91
92    __RW_START__ = .;
93
94    DATA_SECTION >RAM
95    STACK_SECTION >RAM
96    BSS_SECTION >RAM
97    XLAT_TABLE_SECTION >RAM
98
99#if USE_COHERENT_MEM
100    /*
101     * The base address of the coherent memory section must be page-aligned to
102     * guarantee that the coherent data are stored on their own pages and are
103     * not mixed with normal data.  This is required to set up the correct
104     * memory attributes for the coherent data page tables.
105     */
106    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
107        __COHERENT_RAM_START__ = .;
108        *(.tzfw_coherent_mem)
109        __COHERENT_RAM_END_UNALIGNED__ = .;
110
111        /*
112         * Memory page(s) mapped to this section will be marked as device
113         * memory. No other unexpected data must creep in. Ensure the rest of
114         * the current memory page is unused.
115         */
116        . = ALIGN(PAGE_SIZE);
117
118        __COHERENT_RAM_END__ = .;
119    } >RAM
120#endif /* USE_COHERENT_MEM */
121
122    __RW_END__ = .;
123    __BL2U_END__ = .;
124
125    __BSS_SIZE__ = SIZEOF(.bss);
126
127    ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
128    RAM_REGION_END = .;
129}
130