1/*
2 * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15#if BL2_IN_XIP_MEM
16    ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17    RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
18#else /* BL2_IN_XIP_MEM */
19    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
20#endif /* BL2_IN_XIP_MEM */
21
22#if SEPARATE_BL2_NOLOAD_REGION
23    RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
24#else /* SEPARATE_BL2_NOLOAD_REGION */
25#   define RAM_NOLOAD RAM
26#endif /* SEPARATE_BL2_NOLOAD_REGION */
27}
28
29#if !BL2_IN_XIP_MEM
30#   define ROM RAM
31#endif /* !BL2_IN_XIP_MEM */
32
33SECTIONS {
34    RAM_REGION_START = ORIGIN(RAM);
35    RAM_REGION_LENGTH = LENGTH(RAM);
36#if BL2_IN_XIP_MEM
37    ROM_REGION_START = ORIGIN(ROM);
38    ROM_REGION_LENGTH = LENGTH(ROM);
39
40    . = BL2_RO_BASE;
41
42    ASSERT(. == ALIGN(PAGE_SIZE),
43        "BL2_RO_BASE address is not aligned on a page boundary.")
44#else /* BL2_IN_XIP_MEM */
45    . = BL2_BASE;
46
47    ASSERT(. == ALIGN(PAGE_SIZE),
48        "BL2_BASE address is not aligned on a page boundary.")
49#endif /* BL2_IN_XIP_MEM */
50
51#if SEPARATE_BL2_NOLOAD_REGION
52    RAM_NOLOAD_REGION_START = ORIGIN(RAM_NOLOAD);
53    RAM_NOLOAD_REGION_LENGTH = LENGTH(RAM_NOLOAD);
54#endif
55
56#if SEPARATE_CODE_AND_RODATA
57    .text . : {
58        ASSERT(. == ALIGN(PAGE_SIZE),
59        ".text address is not aligned on a page boundary.");
60
61        __TEXT_START__ = .;
62        __TEXT_RESIDENT_START__ = .;
63
64        *bl2_el3_entrypoint.o(.text*)
65        *(.text.asm.*)
66
67        __TEXT_RESIDENT_END__ = .;
68
69        *(SORT_BY_ALIGNMENT(.text*))
70        *(.vectors)
71        __TEXT_END_UNALIGNED__ = .;
72
73        . = ALIGN(PAGE_SIZE);
74
75        __TEXT_END__ = .;
76    } >ROM
77
78    .rodata . : {
79        __RODATA_START__ = .;
80
81        *(SORT_BY_ALIGNMENT(.rodata*))
82
83        RODATA_COMMON
84
85        __RODATA_END_UNALIGNED__ = .;
86        . = ALIGN(PAGE_SIZE);
87
88        __RODATA_END__ = .;
89    } >ROM
90
91    ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
92        "Resident part of BL2 has exceeded its limit.")
93#else /* SEPARATE_CODE_AND_RODATA */
94    .ro . : {
95        ASSERT(. == ALIGN(PAGE_SIZE),
96        ".ro address is not aligned on a page boundary.");
97
98        __RO_START__ = .;
99        __TEXT_RESIDENT_START__ = .;
100
101        *bl2_el3_entrypoint.o(.text*)
102        *(.text.asm.*)
103
104        __TEXT_RESIDENT_END__ = .;
105
106        *(SORT_BY_ALIGNMENT(.text*))
107        *(SORT_BY_ALIGNMENT(.rodata*))
108
109        RODATA_COMMON
110
111        *(.vectors)
112
113        __RO_END_UNALIGNED__ = .;
114
115        /*
116         * Memory page(s) mapped to this section will be marked as read-only,
117         * executable. No RW data from the next section must creep in. Ensure
118         * that the rest of the current memory page is unused.
119         */
120        . = ALIGN(PAGE_SIZE);
121
122        __RO_END__ = .;
123    } >ROM
124#endif /* SEPARATE_CODE_AND_RODATA */
125
126    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
127        "cpu_ops not defined for this platform.")
128
129#if BL2_IN_XIP_MEM
130    ROM_REGION_END = .;
131    . = BL2_RW_BASE;
132
133    ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
134           "BL2_RW_BASE address is not aligned on a page boundary.")
135#endif /* BL2_IN_XIP_MEM */
136
137    __RW_START__ = .;
138
139    DATA_SECTION >RAM AT>ROM
140
141    __DATA_RAM_START__ = __DATA_START__;
142    __DATA_RAM_END__ = __DATA_END__;
143
144    RELA_SECTION >RAM
145
146#if SEPARATE_BL2_NOLOAD_REGION
147    SAVED_ADDR = .;
148
149    . = BL2_NOLOAD_START;
150
151    __BL2_NOLOAD_START__ = .;
152#endif /* SEPARATE_BL2_NOLOAD_REGION */
153
154    STACK_SECTION >RAM_NOLOAD
155    BSS_SECTION >RAM_NOLOAD
156    XLAT_TABLE_SECTION >RAM_NOLOAD
157
158#if SEPARATE_BL2_NOLOAD_REGION
159    __BL2_NOLOAD_END__ = .;
160    RAM_NOLOAD_REGION_END = .;
161
162    . = SAVED_ADDR;
163#endif /* SEPARATE_BL2_NOLOAD_REGION */
164
165#if USE_COHERENT_MEM
166    /*
167     * The base address of the coherent memory section must be page-aligned to
168     * guarantee that the coherent data are stored on their own pages and are
169     * not mixed with normal data.  This is required to set up the correct
170     * memory attributes for the coherent data page tables.
171     */
172    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
173        __COHERENT_RAM_START__ = .;
174
175        *(.tzfw_coherent_mem)
176
177        __COHERENT_RAM_END_UNALIGNED__ = .;
178
179        /*
180         * Memory page(s) mapped to this section will be marked as device
181         * memory. No other unexpected data must creep in. Ensure the rest of
182         * the current memory page is unused.
183         */
184        . = ALIGN(PAGE_SIZE);
185
186        __COHERENT_RAM_END__ = .;
187    } >RAM
188#endif /* USE_COHERENT_MEM */
189
190    __RW_END__ = .;
191    __BL2_END__ = .;
192
193    /DISCARD/ : {
194        *(.dynsym .dynstr .hash .gnu.hash)
195    }
196
197#if BL2_IN_XIP_MEM
198    __BL2_RAM_START__ = ADDR(.data);
199    __BL2_RAM_END__ = .;
200
201    __DATA_ROM_START__ = LOADADDR(.data);
202    __DATA_SIZE__ = SIZEOF(.data);
203
204    /*
205     * The .data section is the last PROGBITS section so its end marks the end
206     * of BL2's RO content in XIP memory.
207     */
208    __BL2_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
209
210    ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
211           "BL2's RO content has exceeded its limit.")
212#endif /* BL2_IN_XIP_MEM */
213
214    __BSS_SIZE__ = SIZEOF(.bss);
215
216#if USE_COHERENT_MEM
217    __COHERENT_RAM_UNALIGNED_SIZE__ =
218        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
219#endif /* USE_COHERENT_MEM */
220
221    RAM_REGION_END = .;
222#if BL2_IN_XIP_MEM
223    ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
224#else /* BL2_IN_XIP_MEM */
225    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
226#endif /* BL2_IN_XIP_MEM */
227}
228