1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL2_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL2_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        ASSERT(. == ALIGN(PAGE_SIZE),
29        ".text address is not aligned on a page boundary.");
30
31        __TEXT_START__ = .;
32
33#if ENABLE_RME
34        *bl2_rme_entrypoint.o(.text*)
35#else /* ENABLE_RME */
36        *bl2_entrypoint.o(.text*)
37#endif /* ENABLE_RME */
38
39        *(SORT_BY_ALIGNMENT(.text*))
40        *(.vectors)
41        __TEXT_END_UNALIGNED__ = .;
42
43        . = ALIGN(PAGE_SIZE);
44
45        __TEXT_END__ = .;
46    } >RAM
47
48    /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
49    .ARM.extab . : {
50        *(.ARM.extab* .gnu.linkonce.armextab.*)
51    } >RAM
52
53    .ARM.exidx . : {
54        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
55    } >RAM
56
57    .rodata . : {
58        __RODATA_START__ = .;
59
60        *(SORT_BY_ALIGNMENT(.rodata*))
61
62        RODATA_COMMON
63
64        __RODATA_END_UNALIGNED__ = .;
65        . = ALIGN(PAGE_SIZE);
66
67        __RODATA_END__ = .;
68    } >RAM
69#else /* SEPARATE_CODE_AND_RODATA */
70    .ro . : {
71        ASSERT(. == ALIGN(PAGE_SIZE),
72        ".ro address is not aligned on a page boundary.");
73
74        __RO_START__ = .;
75
76        *bl2_entrypoint.o(.text*)
77        *(SORT_BY_ALIGNMENT(.text*))
78        *(SORT_BY_ALIGNMENT(.rodata*))
79
80        RODATA_COMMON
81
82        *(.vectors)
83
84        __RO_END_UNALIGNED__ = .;
85
86        /*
87         * Memory page(s) mapped to this section will be marked as read-only,
88         * executable. No RW data from the next section must creep in. Ensure
89         * that the rest of the current memory page is unused.
90         */
91        . = ALIGN(PAGE_SIZE);
92
93        __RO_END__ = .;
94    } >RAM
95#endif /* SEPARATE_CODE_AND_RODATA */
96
97    __RW_START__ = .;
98
99    DATA_SECTION >RAM
100    STACK_SECTION >RAM
101    BSS_SECTION >RAM
102    XLAT_TABLE_SECTION >RAM
103
104#if USE_COHERENT_MEM
105    /*
106     * The base address of the coherent memory section must be page-aligned to
107     * guarantee that the coherent data are stored on their own pages and are
108     * not mixed with normal data.  This is required to set up the correct
109     * memory attributes for the coherent data page tables.
110     */
111    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
112        __COHERENT_RAM_START__ = .;
113        *(.tzfw_coherent_mem)
114        __COHERENT_RAM_END_UNALIGNED__ = .;
115
116        /*
117         * Memory page(s) mapped to this section will be marked as device
118         * memory. No other unexpected data must creep in. Ensure the rest of
119         * the current memory page is unused.
120         */
121        . = ALIGN(PAGE_SIZE);
122
123        __COHERENT_RAM_END__ = .;
124    } >RAM
125#endif /* USE_COHERENT_MEM */
126
127    __RW_END__ = .;
128    __BL2_END__ = .;
129    RAM_REGION_END = .;
130
131    __BSS_SIZE__ = SIZEOF(.bss);
132
133#if USE_COHERENT_MEM
134    __COHERENT_RAM_UNALIGNED_SIZE__ =
135        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
136#endif /* USE_COHERENT_MEM */
137
138    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
139}
140