1/*
2 * Copyright (c) 2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10
11	.globl	bl2_run_next_image
12
13
14func bl2_run_next_image
15	mov	x20,x0
16	/* ---------------------------------------------
17	 * MMU needs to be disabled because both BL2 and BL31 execute
18	 * in EL3, and therefore share the same address space.
19	 * BL31 will initialize the address space according to its
20	 * own requirement.
21	 * ---------------------------------------------
22	 */
23	bl	disable_mmu_icache_el3
24	tlbi	alle3
25	bl	bl2_el3_plat_prepare_exit
26
27	ldp	x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
28	msr	elr_el3, x0
29	msr	spsr_el3, x1
30
31	ldp	x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
32	ldp	x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
33	ldp	x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
34	ldp	x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
35	exception_return
36endfunc bl2_run_next_image
37