1 /*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
4 * Copyright (c) 1997--2022 Martin Mares <[email protected]>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13
14 #include "lspci.h"
15
16 static void
cap_tph(struct device * d,int where)17 cap_tph(struct device *d, int where)
18 {
19 u32 tph_cap;
20 printf("Transaction Processing Hints\n");
21 if (verbose < 2)
22 return;
23
24 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
25 return;
26
27 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
28
29 if (tph_cap & PCI_TPH_INTVEC_SUP)
30 printf("\t\tInterrupt vector mode supported\n");
31 if (tph_cap & PCI_TPH_DEV_SUP)
32 printf("\t\tDevice specific mode supported\n");
33 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
34 printf("\t\tExtended requester support\n");
35
36 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
37 case PCI_TPH_ST_NONE:
38 printf("\t\tNo steering table available\n");
39 break;
40 case PCI_TPH_ST_CAP:
41 printf("\t\tSteering table in TPH capability structure\n");
42 break;
43 case PCI_TPH_ST_MSIX:
44 printf("\t\tSteering table in MSI-X table\n");
45 break;
46 default:
47 printf("\t\tReserved steering table location\n");
48 break;
49 }
50 }
51
52 static u32
cap_ltr_scale(u8 scale)53 cap_ltr_scale(u8 scale)
54 {
55 return 1 << (scale * 5);
56 }
57
58 static void
cap_ltr(struct device * d,int where)59 cap_ltr(struct device *d, int where)
60 {
61 u32 scale;
62 u16 snoop, nosnoop;
63 printf("Latency Tolerance Reporting\n");
64 if (verbose < 2)
65 return;
66
67 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
68 return;
69
70 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
71 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
72 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
73 ((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
74
75 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
76 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
77 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
78 ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
79 }
80
81 static void
cap_sec(struct device * d,int where)82 cap_sec(struct device *d, int where)
83 {
84 u32 ctrl3, lane_err_stat;
85 u8 lane;
86 printf("Secondary PCI Express\n");
87 if (verbose < 2)
88 return;
89
90 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
91 return;
92
93 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
94 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
95 FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
96 FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
97
98 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
99 printf("\t\tLaneErrStat: ");
100 if (lane_err_stat)
101 {
102 printf("LaneErr at lane:");
103 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
104 if (BITS(lane_err_stat, 0, 1))
105 printf(" %u", lane);
106 }
107 else
108 printf("0");
109 printf("\n");
110 }
111
112 static void
cap_dsn(struct device * d,int where)113 cap_dsn(struct device *d, int where)
114 {
115 u32 t1, t2;
116 if (!config_fetch(d, where + 4, 8))
117 return;
118 t1 = get_conf_long(d, where + 4);
119 t2 = get_conf_long(d, where + 8);
120 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
121 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
122 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
123 }
124
125 static void
cap_aer(struct device * d,int where,int type)126 cap_aer(struct device *d, int where, int type)
127 {
128 u32 l, l0, l1, l2, l3;
129 u16 w;
130
131 printf("Advanced Error Reporting\n");
132 if (verbose < 2)
133 return;
134
135 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
136 return;
137
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
139 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
140 "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
141 "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
142 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
143 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
144 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
145 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
146 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
147 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
148 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
149 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
150 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
151 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
152 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
153 "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
154 "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
155 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
156 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
157 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
158 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
159 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
160 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
161 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
162 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
163 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
164 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
165 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c\n"
166 "\t\t\tECRC%c UnsupReq%c ACSViol%c UncorrIntErr%c BlockedTLP%c AtomicOpBlocked%c TLPBlockedErr%c\n"
167 "\t\t\tPoisonTLPBlocked%c DMWrReqBlocked%c IDECheck%c MisIDETLP%c PCRC_CHECK%c TLPXlatBlocked%c\n",
168 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
169 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
170 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
171 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL),
172 FLAG(l, PCI_ERR_UNC_INTERNAL), FLAG(l, PCI_ERR_UNC_MC_BLOCKED_TLP),
173 FLAG(l, PCI_ERR_UNC_ATOMICOP_EGRESS_BLOCKED), FLAG(l, PCI_ERR_UNC_TLP_PREFIX_BLOCKED),
174 FLAG(l, PCI_ERR_UNC_POISONED_TLP_EGRESS), FLAG(l, PCI_ERR_UNC_DMWR_REQ_EGRESS_BLOCKED),
175 FLAG(l, PCI_ERR_UNC_IDE_CHECK), FLAG(l, PCI_ERR_UNC_MISR_IDE_TLP), FLAG(l, PCI_ERR_UNC_PCRC_CHECK),
176 FLAG(l, PCI_ERR_UNC_TLP_XLAT_EGRESS_BLOCKED));
177 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
178 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c "
179 "CorrIntErr%c HeaderOF%c\n",
180 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
181 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE),
182 FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER));
183 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
184 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c "
185 "CorrIntErr%c HeaderOF%c\n",
186 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
187 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE),
188 FLAG(l, PCI_ERR_COR_INTERNAL), FLAG(l, PCI_ERR_COR_HDRLOG_OVER));
189 l = get_conf_long(d, where + PCI_ERR_CAP);
190 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
191 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
192 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
193 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
194 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
195 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
196
197 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
198 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
199 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
200 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
201 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
202
203 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
204 {
205 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
206 return;
207
208 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
209 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
210 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
211 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
212 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
213
214 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
215 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
216 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
217 FLAG(l, PCI_ERR_ROOT_COR_RCV),
218 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
219 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
220 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
221 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
222 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
223 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
224 PCI_ERR_MSG_NUM(l));
225
226 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
227 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
228
229 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
230 printf("ERR_FATAL/NONFATAL: %04x\n", w);
231 }
232 }
233
cap_dpc(struct device * d,int where)234 static void cap_dpc(struct device *d, int where)
235 {
236 u16 l;
237
238 printf("Downstream Port Containment\n");
239 if (verbose < 2)
240 return;
241
242 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
243 return;
244
245 l = get_conf_word(d, where + PCI_DPC_CAP);
246 printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
247 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
248 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
249
250 l = get_conf_word(d, where + PCI_DPC_CTL);
251 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
252 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
253 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
254 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
255
256 l = get_conf_word(d, where + PCI_DPC_STATUS);
257 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
258 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
259 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
260
261 l = get_conf_word(d, where + PCI_DPC_SOURCE);
262 printf("\t\tSource:\t%04x\n", l);
263 }
264
265 static void
cap_acs(struct device * d,int where)266 cap_acs(struct device *d, int where)
267 {
268 u16 w;
269
270 printf("Access Control Services\n");
271 if (verbose < 2)
272 return;
273
274 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
275 return;
276
277 w = get_conf_word(d, where + PCI_ACS_CAP);
278 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
279 "DirectTrans%c\n",
280 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
281 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
282 FLAG(w, PCI_ACS_CAP_TRANS));
283 w = get_conf_word(d, where + PCI_ACS_CTRL);
284 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
285 "DirectTrans%c\n",
286 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
287 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
288 FLAG(w, PCI_ACS_CTRL_TRANS));
289 }
290
291 static void
cap_ari(struct device * d,int where)292 cap_ari(struct device *d, int where)
293 {
294 u16 w;
295
296 printf("Alternative Routing-ID Interpretation (ARI)\n");
297 if (verbose < 2)
298 return;
299
300 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
301 return;
302
303 w = get_conf_word(d, where + PCI_ARI_CAP);
304 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
305 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
306 PCI_ARI_CAP_NFN(w));
307 w = get_conf_word(d, where + PCI_ARI_CTRL);
308 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
309 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
310 PCI_ARI_CTRL_FG(w));
311 }
312
313 static void
cap_ats(struct device * d,int where)314 cap_ats(struct device *d, int where)
315 {
316 u16 w;
317
318 printf("Address Translation Service (ATS)\n");
319 if (verbose < 2)
320 return;
321
322 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
323 return;
324
325 w = get_conf_word(d, where + PCI_ATS_CAP);
326 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
327 w = get_conf_word(d, where + PCI_ATS_CTRL);
328 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
329 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
330 }
331
332 static void
cap_pri(struct device * d,int where)333 cap_pri(struct device *d, int where)
334 {
335 u16 w;
336 u32 l;
337
338 printf("Page Request Interface (PRI)\n");
339 if (verbose < 2)
340 return;
341
342 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
343 return;
344
345 w = get_conf_word(d, where + PCI_PRI_CTRL);
346 printf("\t\tPRICtl: Enable%c Reset%c\n",
347 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
348 w = get_conf_word(d, where + PCI_PRI_STATUS);
349 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
350 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
351 FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID));
352 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
353 printf("\t\tPage Request Capacity: %08x, ", l);
354 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
355 printf("Page Request Allocation: %08x\n", l);
356 }
357
358 static void
cap_pasid(struct device * d,int where)359 cap_pasid(struct device *d, int where)
360 {
361 u16 w;
362
363 printf("Process Address Space ID (PASID)\n");
364 if (verbose < 2)
365 return;
366
367 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
368 return;
369
370 w = get_conf_word(d, where + PCI_PASID_CAP);
371 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
372 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
373 PCI_PASID_CAP_WIDTH(w));
374 w = get_conf_word(d, where + PCI_PASID_CTRL);
375 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
376 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
377 FLAG(w, PCI_PASID_CTRL_PRIV));
378 }
379
380 static void
cap_sriov(struct device * d,int where)381 cap_sriov(struct device *d, int where)
382 {
383 u16 b;
384 u16 w;
385 u32 l;
386 int i;
387
388 printf("Single Root I/O Virtualization (SR-IOV)\n");
389 if (verbose < 2)
390 return;
391
392 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
393 return;
394
395 l = get_conf_long(d, where + PCI_IOV_CAP);
396 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
397 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
398 w = get_conf_word(d, where + PCI_IOV_CTRL);
399 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
400 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
401 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
402 FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
403 w = get_conf_word(d, where + PCI_IOV_STATUS);
404 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
405 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
406 printf("\t\tInitial VFs: %d, ", w);
407 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
408 printf("Total VFs: %d, ", w);
409 w = get_conf_word(d, where + PCI_IOV_NUMVF);
410 printf("Number of VFs: %d, ", w);
411 b = get_conf_byte(d, where + PCI_IOV_FDL);
412 printf("Function Dependency Link: %02x\n", b);
413 w = get_conf_word(d, where + PCI_IOV_OFFSET);
414 printf("\t\tVF offset: %d, ", w);
415 w = get_conf_word(d, where + PCI_IOV_STRIDE);
416 printf("stride: %d, ", w);
417 w = get_conf_word(d, where + PCI_IOV_DID);
418 printf("Device ID: %04x\n", w);
419 l = get_conf_long(d, where + PCI_IOV_SUPPS);
420 printf("\t\tSupported Page Size: %08x, ", l);
421 l = get_conf_long(d, where + PCI_IOV_SYSPS);
422 printf("System Page Size: %08x\n", l);
423
424 for (i=0; i < PCI_IOV_NUM_BAR; i++)
425 {
426 u32 addr;
427 int type;
428 u32 h;
429 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
430 if (l == 0xffffffff)
431 l = 0;
432 if (!l)
433 continue;
434 printf("\t\tRegion %d: Memory at ", i);
435 addr = l & PCI_ADDR_MEM_MASK;
436 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
437 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
438 {
439 i++;
440 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
441 printf("%08x", h);
442 }
443 printf("%08x (%s-bit, %sprefetchable)\n",
444 addr,
445 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
446 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
447 }
448
449 l = get_conf_long(d, where + PCI_IOV_MSAO);
450 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
451 PCI_IOV_MSA_BIR(l));
452 }
453
454 static void
cap_multicast(struct device * d,int where,int type)455 cap_multicast(struct device *d, int where, int type)
456 {
457 u16 w;
458 u32 l;
459 u64 bar, rcv, block;
460
461 printf("Multicast\n");
462 if (verbose < 2)
463 return;
464
465 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
466 return;
467
468 w = get_conf_word(d, where + PCI_MCAST_CAP);
469 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
470 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
471 printf(", WindowSz %d (%d bytes)",
472 PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
473 if (type == PCI_EXP_TYPE_ROOT_PORT ||
474 type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
475 printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
476 w = get_conf_word(d, where + PCI_MCAST_CTRL);
477 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
478 PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
479 bar = get_conf_long(d, where + PCI_MCAST_BAR);
480 l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
481 bar |= (u64) l << 32;
482 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
483 PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
484 rcv = get_conf_long(d, where + PCI_MCAST_RCV);
485 l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
486 rcv |= (u64) l << 32;
487 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
488 block = get_conf_long(d, where + PCI_MCAST_BLOCK);
489 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
490 block |= (u64) l << 32;
491 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
492 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
493 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
494 block |= (u64) l << 32;
495 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
496
497 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
498 return;
499 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
500 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
501 bar |= (u64) l << 32;
502 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
503 if (PCI_MCAST_OVL_SIZE(bar) >= 6)
504 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
505 else
506 printf("(disabled)");
507 printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
508 }
509
510 static void
cap_vc(struct device * d,int where)511 cap_vc(struct device *d, int where)
512 {
513 u32 cr1, cr2;
514 u16 ctrl, status;
515 int evc_cnt;
516 int arb_table_pos;
517 int i, j;
518 static const char ref_clocks[][6] = { "100ns" };
519 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
520 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
521 char buf[8];
522
523 printf("Virtual Channel\n");
524 if (verbose < 2)
525 return;
526
527 if (!config_fetch(d, where + 4, 0x1c - 4))
528 return;
529
530 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
531 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
532 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
533 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
534
535 evc_cnt = BITS(cr1, 0, 3);
536 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
537 BITS(cr1, 4, 3),
538 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
539 1 << BITS(cr1, 10, 2));
540
541 printf("\t\tArb:");
542 for (i=0; i<8; i++)
543 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
544 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
545 arb_table_pos = BITS(cr2, 24, 8);
546
547 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
548 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
549
550 if (arb_table_pos)
551 {
552 arb_table_pos = where + 16*arb_table_pos;
553 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
554 }
555
556 for (i=0; i<=evc_cnt; i++)
557 {
558 int pos = where + PCI_VC_RES_CAP + 12*i;
559 u32 rcap, rctrl;
560 u16 rstatus;
561 int pat_pos;
562
563 printf("\t\tVC%d:\t", i);
564 if (!config_fetch(d, pos, 12))
565 {
566 printf("<unreadable>\n");
567 continue;
568 }
569 rcap = get_conf_long(d, pos);
570 rctrl = get_conf_long(d, pos+4);
571 rstatus = get_conf_word(d, pos+10);
572
573 pat_pos = BITS(rcap, 24, 8);
574 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
575 pat_pos,
576 BITS(rcap, 16, 7) + 1,
577 FLAG(rcap, 1 << 15));
578
579 printf("\t\t\tArb:");
580 for (j=0; j<8; j++)
581 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
582 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
583
584 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
585 FLAG(rctrl, 1 << 31),
586 BITS(rctrl, 24, 3),
587 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
588 BITS(rctrl, 0, 8));
589
590 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
591 FLAG(rstatus, 2),
592 FLAG(rstatus, 1));
593
594 if (pat_pos)
595 printf("\t\t\tPort Arbitration Table <?>\n");
596 }
597 }
598
599 static void
cap_rclink(struct device * d,int where)600 cap_rclink(struct device *d, int where)
601 {
602 u32 esd;
603 int num_links;
604 int i;
605 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
606 char buf[8];
607
608 printf("Root Complex Link\n");
609 if (verbose < 2)
610 return;
611
612 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
613 return;
614
615 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
616 num_links = BITS(esd, 8, 8);
617 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
618 BITS(esd, 24, 8),
619 BITS(esd, 16, 8),
620 TABLE(elt_types, BITS(esd, 0, 8), buf));
621
622 for (i=0; i<num_links; i++)
623 {
624 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
625 u32 desc;
626 u32 addr_lo, addr_hi;
627
628 printf("\t\tLink%d:\t", i);
629 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
630 {
631 printf("<unreadable>\n");
632 return;
633 }
634 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
635 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
636 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
637
638 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
639 BITS(desc, 24, 8),
640 BITS(desc, 16, 8),
641 FLAG(desc, 4),
642 ((desc & 2) ? "Config" : "MemMapped"),
643 FLAG(desc, 1));
644
645 if (desc & 2)
646 {
647 int n = addr_lo & 7;
648 if (!n)
649 n = 8;
650 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
651 BITS(addr_lo, 20, n),
652 BITS(addr_lo, 15, 5),
653 BITS(addr_lo, 12, 3),
654 addr_hi, addr_lo);
655 }
656 else
657 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
658 }
659 }
660
661 static void
cap_rcec(struct device * d,int where)662 cap_rcec(struct device *d, int where)
663 {
664 printf("Root Complex Event Collector Endpoint Association\n");
665 if (verbose < 2)
666 return;
667
668 if (!config_fetch(d, where, 12))
669 return;
670
671 u32 hdr = get_conf_long(d, where);
672 byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
673 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
674 printf("\t\tRCiEPBitmap: ");
675 if (bmap)
676 {
677 int prevmatched=0;
678 int adjcount=0;
679 int prevdev=0;
680 printf("RCiEP at Device(s):");
681 for (int dev=0; dev < 32; dev++)
682 {
683 if (BITS(bmap, dev, 1))
684 {
685 if (!adjcount)
686 printf("%s %u", (prevmatched) ? "," : "", dev);
687 adjcount++;
688 prevdev=dev;
689 prevmatched=1;
690 }
691 else
692 {
693 if (adjcount > 1)
694 printf("-%u", prevdev);
695 adjcount=0;
696 }
697 }
698 }
699 else
700 printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
701 printf("\n");
702
703 if (cap_ver < PCI_RCEC_BUSN_REG_VER)
704 return;
705
706 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
707 u8 lastbusn = BITS(busn, 16, 8);
708 u8 nextbusn = BITS(busn, 8, 8);
709
710 if ((lastbusn == 0x00) && (nextbusn == 0xff))
711 printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
712 else
713 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
714 }
715
716 static void
cap_lmr(struct device * d,int where)717 cap_lmr(struct device *d, int where)
718 {
719 printf("Lane Margining at the Receiver\n");
720
721 if (verbose < 2)
722 return;
723
724 if (!config_fetch(d, where, 8))
725 return;
726
727 u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS);
728 u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS);
729
730 printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR));
731 printf("\t\tPortSta: MargReady%c MargSoftReady%c\n",
732 FLAG(port_status, PCI_LMR_PORT_STS_READY),
733 FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY));
734 }
735
736 static void
cxl_range(u64 base,u64 size,int n)737 cxl_range(u64 base, u64 size, int n)
738 {
739 u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
740 const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
741 const char *class[] = { "DRAM", "Storage", "CDAT" };
742 u16 w;
743
744 w = (u16) size;
745
746 size &= ~0x0fffffffULL;
747
748 printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X" [size=0x%"PCI_U64_FMT_X"]\n", n, base, base + size - 1, size);
749 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
750 FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
751 type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
752 interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
753 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
754 }
755
756 static void
dvsec_cxl_device(struct device * d,int rev,int where,int len)757 dvsec_cxl_device(struct device *d, int rev, int where, int len)
758 {
759 u32 cache_size, cache_unit_size;
760 u64 range_base, range_size;
761 u16 w;
762
763 /* Legacy 1.1 revs aren't handled */
764 if (rev == 0)
765 return;
766
767 if (rev >= 1 && len >= PCI_CXL_DEV_LEN)
768 {
769 w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
770 printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
771 FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
772 FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
773
774 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
775 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
776 FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
777 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
778 FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
779
780 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
781 printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
782
783 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
784 printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
785 FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
786 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
787 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
788 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
789 if (rev >= 2)
790 printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
791 printf("\n");
792
793 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
794 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
795 FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
796
797 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
798 printf("\t\tCXLCap2:\t");
799 cache_unit_size = BITS(w, 0, 4);
800 cache_size = BITS(w, 8, 8);
801 switch (cache_unit_size)
802 {
803 case PCI_CXL_DEV_CAP2_CACHE_1M:
804 printf("Cache Size: %08x\n", cache_size * (1<<20));
805 break;
806 case PCI_CXL_DEV_CAP2_CACHE_64K:
807 printf("Cache Size: %08x\n", cache_size * (64<<10));
808 break;
809 case PCI_CXL_DEV_CAP2_CACHE_UNK:
810 printf("Cache Size Not Reported\n");
811 break;
812 default:
813 printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
814 break;
815 }
816
817 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
818 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
819 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
820 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
821 cxl_range(range_base, range_size, 1);
822
823 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
824 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
825 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
826 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
827 cxl_range(range_base, range_size, 2);
828 }
829
830 if (rev >= 2 && len >= PCI_CXL_DEV_LEN_REV2)
831 {
832 w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
833 printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
834 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
835 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
836 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
837 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
838 }
839
840 // Unparsed data
841 if (len > PCI_CXL_DEV_LEN_REV2)
842 printf("\t\t<?>\n");
843 }
844
845 static void
dvsec_cxl_port(struct device * d,int where,int len)846 dvsec_cxl_port(struct device *d, int where, int len)
847 {
848 u16 w, m1, m2;
849 u8 b1, b2;
850
851 if (len < PCI_CXL_PORT_EXT_LEN)
852 return;
853
854 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
855 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
856
857 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
858 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
859 FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
860 FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
861 FLAG(w, PCI_CXL_PORT_VIRAL_EN));
862
863 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
864 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
865 printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
866 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
867 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
868 printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
869 }
870
871 static void
dvsec_cxl_register_locator(struct device * d,int where,int len)872 dvsec_cxl_register_locator(struct device *d, int where, int len)
873 {
874 static const char * const id_names[] = {
875 "empty",
876 "component registers",
877 "BAR virtualization",
878 "CXL device registers",
879 "CPMU registers",
880 };
881
882 for (int i=0; ; i++)
883 {
884 int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
885 if (pos + 7 >= where + len)
886 break;
887
888 u32 lo = get_conf_long(d, pos);
889 u32 hi = get_conf_long(d, pos + 4);
890
891 unsigned int bir = BITS(lo, 0, 3);
892 unsigned int block_id = BITS(lo, 8, 8);
893 u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
894
895 if (!block_id)
896 continue;
897
898 const char *id_name;
899 if (block_id < sizeof(id_names) / sizeof(*id_names))
900 id_name = id_names[block_id];
901 else if (block_id == 0xff)
902 id_name = "vendor-specific";
903 else
904 id_name = "<?>";
905
906 printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
907 }
908 }
909
910 static void
dvsec_cxl_gpf_device(struct device * d,int where)911 dvsec_cxl_gpf_device(struct device *d, int where)
912 {
913 u32 l;
914 u16 w, duration;
915 u8 time_base, time_scale;
916
917 w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
918 time_base = BITS(w, 0, 4);
919 time_scale = BITS(w, 8, 4);
920
921 switch (time_scale)
922 {
923 case PCI_CXL_GPF_DEV_100US:
924 case PCI_CXL_GPF_DEV_100MS:
925 duration = time_base * 100;
926 break;
927 case PCI_CXL_GPF_DEV_10US:
928 case PCI_CXL_GPF_DEV_10MS:
929 case PCI_CXL_GPF_DEV_10S:
930 duration = time_base * 10;
931 break;
932 case PCI_CXL_GPF_DEV_1US:
933 case PCI_CXL_GPF_DEV_1MS:
934 case PCI_CXL_GPF_DEV_1S:
935 duration = time_base;
936 break;
937 default:
938 /* Reserved */
939 printf("\t\tReserved time scale encoding %x\n", time_scale);
940 duration = time_base;
941 }
942
943 printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
944 (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
945 (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
946 (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
947
948 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
949 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
950 }
951
952 static void
dvsec_cxl_gpf_port(struct device * d,int where)953 dvsec_cxl_gpf_port(struct device *d, int where)
954 {
955 u16 w, timeout;
956 u8 time_base, time_scale;
957
958 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
959 time_base = BITS(w, 0, 4);
960 time_scale = BITS(w, 8, 4);
961
962 switch (time_scale)
963 {
964 case PCI_CXL_GPF_PORT_100US:
965 case PCI_CXL_GPF_PORT_100MS:
966 timeout = time_base * 100;
967 break;
968 case PCI_CXL_GPF_PORT_10US:
969 case PCI_CXL_GPF_PORT_10MS:
970 case PCI_CXL_GPF_PORT_10S:
971 timeout = time_base * 10;
972 break;
973 case PCI_CXL_GPF_PORT_1US:
974 case PCI_CXL_GPF_PORT_1MS:
975 case PCI_CXL_GPF_PORT_1S:
976 timeout = time_base;
977 break;
978 default:
979 /* Reserved */
980 printf("\t\tReserved time scale encoding %x\n", time_scale);
981 timeout = time_base;
982 }
983
984 printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
985 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
986 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
987 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
988
989 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
990 time_base = BITS(w, 0, 4);
991 time_scale = BITS(w, 8, 4);
992
993 switch (time_scale)
994 {
995 case PCI_CXL_GPF_PORT_100US:
996 case PCI_CXL_GPF_PORT_100MS:
997 timeout = time_base * 100;
998 break;
999 case PCI_CXL_GPF_PORT_10US:
1000 case PCI_CXL_GPF_PORT_10MS:
1001 case PCI_CXL_GPF_PORT_10S:
1002 timeout = time_base * 10;
1003 break;
1004 case PCI_CXL_GPF_PORT_1US:
1005 case PCI_CXL_GPF_PORT_1MS:
1006 case PCI_CXL_GPF_PORT_1S:
1007 timeout = time_base;
1008 break;
1009 default:
1010 /* Reserved */
1011 printf("\t\tReserved time scale encoding %x\n", time_scale);
1012 timeout = time_base;
1013 }
1014
1015 printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
1016 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
1017 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
1018 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
1019 }
1020
1021 static void
dvsec_cxl_flex_bus(struct device * d,int where,int rev,int len)1022 dvsec_cxl_flex_bus(struct device *d, int where, int rev, int len)
1023 {
1024 u16 w;
1025 u32 l, data;
1026
1027 // Sanity check: Does the length correspond to its revision?
1028 switch (rev) {
1029 case 0:
1030 if (len != PCI_CXL_FB_MOD_TS_DATA)
1031 printf("\t\t<Wrong length for Revision %d>\n", rev);
1032 break;
1033 case 1:
1034 if (len != PCI_CXL_FB_PORT_CAP2)
1035 printf("\t\t<Wrong length for Revision %d>\n", rev);
1036 break;
1037 case 2:
1038 if (len != PCI_CXL_FB_NEXT_UNSUPPORTED)
1039 printf("\t\t<Wrong length for Revision %d>\n", rev);
1040 break;
1041 default:
1042 break;
1043 }
1044
1045 // From Rev 0
1046 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
1047 printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
1048 FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
1049 FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
1050 FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
1051
1052 if (rev > 1)
1053 printf(" 256BFlit%c PBRFlit%c",
1054 FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
1055
1056 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
1057 printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
1058 FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
1059 FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
1060 FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
1061 FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
1062 FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
1063
1064 if (rev > 1)
1065 printf(" 256BFlit%c PBRFlit%c",
1066 FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
1067
1068 w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
1069 printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
1070 FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
1071 FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
1072 FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
1073 FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
1074
1075 if (rev > 1)
1076 printf(" 256BFlit%c PBRFlit%c",
1077 FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
1078 printf("\n");
1079
1080 // From Rev 1
1081 if (rev >= 1)
1082 {
1083 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
1084 data = BITS(l, 0, 24);
1085 printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
1086 }
1087
1088 // From Rev 2
1089 if (rev >= 2)
1090 {
1091 u8 nop;
1092
1093 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
1094 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
1095
1096 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
1097 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
1098
1099 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
1100 nop = BITS(l, 0, 2);
1101 printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
1102 }
1103
1104 // Unparsed data
1105 if (len > PCI_CXL_FB_LEN)
1106 printf("\t\t<?>\n");
1107 }
1108
1109 static void
dvsec_cxl_mld(struct device * d,int where)1110 dvsec_cxl_mld(struct device *d, int where)
1111 {
1112 u16 w;
1113
1114 w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
1115
1116 /* Encodings greater than 16 are reserved */
1117 if (w && w <= PCI_CXL_MLD_MAX_LD)
1118 printf("\t\tNumLogDevs: %d\n", w);
1119 }
1120
1121 static void
dvsec_cxl_function_map(struct device * d,int where)1122 dvsec_cxl_function_map(struct device *d, int where)
1123 {
1124
1125 printf("\t\tFuncMap 0: %08x\n",
1126 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
1127
1128 printf("\t\tFuncMap 1: %08x\n",
1129 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
1130
1131 printf("\t\tFuncMap 2: %08x\n",
1132 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
1133
1134 printf("\t\tFuncMap 3: %08x\n",
1135 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
1136
1137 printf("\t\tFuncMap 4: %08x\n",
1138 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
1139
1140 printf("\t\tFuncMap 5: %08x\n",
1141 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
1142
1143 printf("\t\tFuncMap 6: %08x\n",
1144 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
1145
1146 printf("\t\tFuncMap 7: %08x\n",
1147 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
1148 }
1149
1150 static void
cap_dvsec_cxl(struct device * d,int id,int rev,int where,int len)1151 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
1152 {
1153 printf(": CXL\n");
1154 if (verbose < 2)
1155 return;
1156
1157 if (!config_fetch(d, where, len))
1158 return;
1159
1160 switch (id)
1161 {
1162 case 0:
1163 printf("\t\tPCIe DVSEC for CXL Devices\n");
1164 dvsec_cxl_device(d, rev, where, len);
1165 break;
1166 case 2:
1167 printf("\t\tNon-CXL Function Map DVSEC\n");
1168 dvsec_cxl_function_map(d, where);
1169 break;
1170 case 3:
1171 printf("\t\tCXL Extensions DVSEC for Ports\n");
1172 dvsec_cxl_port(d, where, len);
1173 break;
1174 case 4:
1175 printf("\t\tGPF DVSEC for CXL Ports\n");
1176 dvsec_cxl_gpf_port(d, where);
1177 break;
1178 case 5:
1179 printf("\t\tGPF DVSEC for CXL Devices\n");
1180 dvsec_cxl_gpf_device(d, where);
1181 break;
1182 case 7:
1183 printf("\t\tPCIe DVSEC for Flex Bus Port\n");
1184 dvsec_cxl_flex_bus(d, where, rev, len);
1185 break;
1186 case 8:
1187 printf("\t\tRegister Locator DVSEC\n");
1188 dvsec_cxl_register_locator(d, where, len);
1189 break;
1190 case 9:
1191 printf("\t\tMLD DVSEC\n");
1192 dvsec_cxl_mld(d, where);
1193 break;
1194 case 0xa:
1195 printf("\t\tPCIe DVSEC for Test Capability <?>\n");
1196 break;
1197 default:
1198 printf("\t\tUnknown ID %04x\n", id);
1199 }
1200 }
1201
1202 static void
cap_dvsec(struct device * d,int where)1203 cap_dvsec(struct device *d, int where)
1204 {
1205 printf("Designated Vendor-Specific: ");
1206 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
1207 {
1208 printf("<unreadable>\n");
1209 return;
1210 }
1211
1212 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
1213 u16 vendor = BITS(hdr, 0, 16);
1214 byte rev = BITS(hdr, 16, 4);
1215 u16 len = BITS(hdr, 20, 12);
1216
1217 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
1218
1219 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
1220 if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
1221 cap_dvsec_cxl(d, id, rev, where, len);
1222 else
1223 printf(" <?>\n");
1224 }
1225
1226 static void
cap_evendor(struct device * d,int where)1227 cap_evendor(struct device *d, int where)
1228 {
1229 u32 hdr;
1230
1231 printf("Vendor Specific Information: ");
1232 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
1233 {
1234 printf("<unreadable>\n");
1235 return;
1236 }
1237
1238 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
1239 printf("ID=%04x Rev=%d Len=%03x <?>\n",
1240 BITS(hdr, 0, 16),
1241 BITS(hdr, 16, 4),
1242 BITS(hdr, 20, 12));
1243 }
1244
l1pm_calc_pwron(int scale,int value)1245 static int l1pm_calc_pwron(int scale, int value)
1246 {
1247 switch (scale)
1248 {
1249 case 0:
1250 return 2 * value;
1251 case 1:
1252 return 10 * value;
1253 case 2:
1254 return 100 * value;
1255 }
1256 return -1;
1257 }
1258
1259 static void
cap_l1pm(struct device * d,int where)1260 cap_l1pm(struct device *d, int where)
1261 {
1262 u32 l1_cap, val, scale;
1263 int time;
1264
1265 printf("L1 PM Substates\n");
1266
1267 if (verbose < 2)
1268 return;
1269
1270 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
1271 {
1272 printf("\t\t<unreadable>\n");
1273 return;
1274 }
1275
1276 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
1277 printf("\t\tL1SubCap: ");
1278 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
1279 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
1280 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
1281 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
1282 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
1283 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
1284
1285 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1286 {
1287 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
1288 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
1289 if (time != -1)
1290 printf("PortTPowerOnTime=%dus\n", time);
1291 else
1292 printf("PortTPowerOnTime=<error>\n");
1293 }
1294
1295 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
1296 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
1297 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
1298 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
1299 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
1300 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
1301
1302 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1303 {
1304 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
1305
1306 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1307 {
1308 scale = BITS(val, 29, 3);
1309 if (scale > 5)
1310 printf(" LTR1.2_Threshold=<error>");
1311 else
1312 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale));
1313 }
1314 printf("\n");
1315 }
1316
1317 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
1318 printf("\t\tL1SubCtl2:");
1319 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1320 {
1321 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
1322 if (time != -1)
1323 printf(" T_PwrOn=%dus", time);
1324 else
1325 printf(" T_PwrOn=<error>");
1326 }
1327 printf("\n");
1328 }
1329
1330 static void
cap_ptm(struct device * d,int where)1331 cap_ptm(struct device *d, int where)
1332 {
1333 u32 buff;
1334 u16 clock;
1335
1336 printf("Precision Time Measurement\n");
1337
1338 if (verbose < 2)
1339 return;
1340
1341 if (!config_fetch(d, where + 4, 8))
1342 {
1343 printf("\t\t<unreadable>\n");
1344 return;
1345 }
1346
1347 buff = get_conf_long(d, where + 4);
1348 printf("\t\tPTMCap: ");
1349 printf("Requester%c Responder%c Root%c\n",
1350 FLAG(buff, 0x1),
1351 FLAG(buff, 0x2),
1352 FLAG(buff, 0x4));
1353
1354 clock = BITS(buff, 8, 8);
1355 printf("\t\tPTMClockGranularity: ");
1356 switch (clock)
1357 {
1358 case 0x00:
1359 printf("Unimplemented\n");
1360 break;
1361 case 0xff:
1362 printf("Greater than 254ns\n");
1363 break;
1364 default:
1365 printf("%huns\n", clock);
1366 }
1367
1368 buff = get_conf_long(d, where + 8);
1369 printf("\t\tPTMControl: ");
1370 printf("Enabled%c RootSelected%c\n",
1371 FLAG(buff, 0x1),
1372 FLAG(buff, 0x2));
1373
1374 clock = BITS(buff, 8, 8);
1375 printf("\t\tPTMEffectiveGranularity: ");
1376 switch (clock)
1377 {
1378 case 0x00:
1379 printf("Unknown\n");
1380 break;
1381 case 0xff:
1382 printf("Greater than 254ns\n");
1383 break;
1384 default:
1385 printf("%huns\n", clock);
1386 }
1387 }
1388
1389 static void
print_rebar_range_size(int ld2_size)1390 print_rebar_range_size(int ld2_size)
1391 {
1392 // This function prints the input as a power-of-2 size value
1393 // It is biased with 1MB = 0, ...
1394 // Maximum resizable BAR value supported is 2^63 bytes = 43
1395 // for the extended resizable BAR capability definition
1396 // (otherwise it would stop at 2^28)
1397
1398 if (ld2_size >= 0 && ld2_size < 10)
1399 printf(" %dMB", (1 << ld2_size));
1400 else if (ld2_size >= 10 && ld2_size < 20)
1401 printf(" %dGB", (1 << (ld2_size-10)));
1402 else if (ld2_size >= 20 && ld2_size < 30)
1403 printf(" %dTB", (1 << (ld2_size-20)));
1404 else if (ld2_size >= 30 && ld2_size < 40)
1405 printf(" %dPB", (1 << (ld2_size-30)));
1406 else if (ld2_size >= 40 && ld2_size < 44)
1407 printf(" %dEB", (1 << (ld2_size-40)));
1408 else
1409 printf(" <unknown>");
1410 }
1411
1412 static void
cap_rebar(struct device * d,int where,int virtual)1413 cap_rebar(struct device *d, int where, int virtual)
1414 {
1415 u32 sizes_buffer, control_buffer, ext_sizes, current_size;
1416 u16 bar_index, barcount, i;
1417 // If the structure exists, at least one bar is defined
1418 u16 num_bars = 1;
1419
1420 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1421
1422 if (verbose < 2)
1423 return;
1424
1425 // Go through all defined BAR definitions of the caps, at minimum 1
1426 // (loop also terminates if num_bars read from caps is > 6)
1427 for (barcount = 0; barcount < num_bars; barcount++)
1428 {
1429 where += 4;
1430
1431 // Get the next BAR configuration
1432 if (!config_fetch(d, where, 8))
1433 {
1434 printf("\t\t<unreadable>\n");
1435 return;
1436 }
1437
1438 sizes_buffer = get_conf_long(d, where) >> 4;
1439 where += 4;
1440 control_buffer = get_conf_long(d, where);
1441
1442 bar_index = BITS(control_buffer, 0, 3);
1443 current_size = BITS(control_buffer, 8, 6);
1444 ext_sizes = BITS(control_buffer, 16, 16);
1445
1446 if (barcount == 0)
1447 {
1448 // Only index 0 controlreg has the num_bar count definition
1449 num_bars = BITS(control_buffer, 5, 3);
1450 if (num_bars < 1 || num_bars > 6)
1451 {
1452 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars);
1453 break;
1454 }
1455 }
1456
1457 // Resizable BAR list entry have an arbitrary index and current size
1458 printf("\t\tBAR %d: current size:", bar_index);
1459 print_rebar_range_size(current_size);
1460
1461 if (sizes_buffer || ext_sizes)
1462 {
1463 printf(", supported:");
1464
1465 for (i=0; i<28; i++)
1466 if (sizes_buffer & (1U << i))
1467 print_rebar_range_size(i);
1468
1469 for (i=0; i<16; i++)
1470 if (ext_sizes & (1U << i))
1471 print_rebar_range_size(i + 28);
1472 }
1473
1474 printf("\n");
1475 }
1476 }
1477
1478 static void
cap_doe(struct device * d,int where)1479 cap_doe(struct device *d, int where)
1480 {
1481 u32 l;
1482
1483 printf("Data Object Exchange\n");
1484
1485 if (verbose < 2)
1486 return;
1487
1488 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
1489 {
1490 printf("\t\t<unreadable>\n");
1491 return;
1492 }
1493
1494 l = get_conf_long(d, where + PCI_DOE_CAP);
1495 printf("\t\tDOECap: IntSup%c\n",
1496 FLAG(l, PCI_DOE_CAP_INT_SUPP));
1497 if (l & PCI_DOE_CAP_INT_SUPP)
1498 printf("\t\t\tIntMsgNum %d\n",
1499 PCI_DOE_CAP_INT_MSG(l));
1500
1501 l = get_conf_long(d, where + PCI_DOE_CTL);
1502 printf("\t\tDOECtl: IntEn%c\n",
1503 FLAG(l, PCI_DOE_CTL_INT));
1504
1505 l = get_conf_long(d, where + PCI_DOE_STS);
1506 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1507 FLAG(l, PCI_DOE_STS_BUSY),
1508 FLAG(l, PCI_DOE_STS_INT),
1509 FLAG(l, PCI_DOE_STS_ERROR),
1510 FLAG(l, PCI_DOE_STS_OBJECT_READY));
1511 }
1512
offstr(char * buf,u32 off)1513 static const char *offstr(char *buf, u32 off)
1514 {
1515 if (verbose < 3)
1516 return "";
1517
1518 sprintf(buf, "[%x]", off);
1519 return buf;
1520 }
1521
ide_alg(char * buf,size_t len,u32 l)1522 static const char *ide_alg(char *buf, size_t len, u32 l)
1523 {
1524 const char *algo[] = { "AES-GCM-256-96b" }; // AES-GCM 256 key size, 96b MAC
1525
1526 if (l == 0)
1527 snprintf(buf, len, "%s", algo[l]);
1528 else
1529 snprintf(buf, len, "%s", "reserved");
1530 return buf;
1531 }
1532
1533 static void
cap_ide(struct device * d,int where)1534 cap_ide(struct device *d, int where)
1535 {
1536 const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" };
1537 const char *stream_state[] = { "insecure", "reserved", "secure" };
1538 const char *aggr[] = { "-", "=2", "=4", "=8" };
1539 u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j;
1540 char buf1[16], buf2[16], offs[16];
1541
1542 printf("Integrity & Data Encryption\n");
1543
1544 if (verbose < 2)
1545 return;
1546
1547 if (!config_fetch(d, where + PCI_IDE_CAP, 8))
1548 {
1549 printf("\t\t<unreadable>\n");
1550 return;
1551 }
1552
1553 l = get_conf_long(d, where + PCI_IDE_CAP);
1554 if (l & PCI_IDE_CAP_LINK_IDE_SUPP)
1555 linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1;
1556 if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP)
1557 selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1;
1558
1559 printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c\n",
1560 linknum,
1561 selnum,
1562 FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP),
1563 FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP),
1564 FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP),
1565 FLAG(l, PCI_IDE_CAP_PCRC_SUPP),
1566 FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP),
1567 ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)),
1568 PCI_IDE_CAP_LINK_TC_NUM(l) + 1,
1569 FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP)
1570 );
1571
1572 l = get_conf_long(d, where + PCI_IDE_CTL);
1573 printf("\t\tIDECtl: FTEn%c\n",
1574 FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE));
1575
1576 // The rest of the capability is variable length arrays
1577 off = where + PCI_IDE_LINK_STREAM;
1578
1579 // Link IDE Register Block repeated 0 to 8 times
1580 if (linknum)
1581 {
1582 if (!config_fetch(d, off, 8 * linknum))
1583 {
1584 printf("\t\t<unreadable>\n");
1585 return;
1586 }
1587 for (i = 0; i < linknum; ++i)
1588 {
1589 // Link IDE Stream Control Register
1590 l = get_conf_long(d, off);
1591 printf("\t\t%sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n",
1592 offstr(offs, off),
1593 i,
1594 FLAG(l, PCI_IDE_LINK_CTL_EN),
1595 aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)],
1596 aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)],
1597 aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)],
1598 FLAG(l, PCI_IDE_LINK_CTL_EN),
1599 TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1),
1600 ide_alg(buf2, sizeof(buf2), PCI_IDE_LINK_CTL_ALG(l)),
1601 PCI_IDE_LINK_CTL_TC(l),
1602 PCI_IDE_LINK_CTL_ID(l)
1603 );
1604 off += 4;
1605
1606 /* Link IDE Stream Status Register */
1607 l = get_conf_long(d, off);
1608 printf("\t\t%sLinkIDE#%d Sta: Status=%s RecvChkFail%c\n",
1609 offstr(offs, off),
1610 i,
1611 TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1),
1612 FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK));
1613 off += 4;
1614 }
1615 }
1616
1617 for (i = 0; i < selnum; ++i)
1618 {
1619 // Fetching Selective IDE Stream Capability/Control/Status/RID1/RID2
1620 if (!config_fetch(d, off, 20))
1621 {
1622 printf("\t\t<unreadable>\n");
1623 return;
1624 }
1625
1626 // Selective IDE Stream Capability Register
1627 l = get_conf_long(d, off);
1628 printf("\t\t%sSelectiveIDE#%d Cap: RID#=%d\n",
1629 offstr(offs, off),
1630 i,
1631 PCI_IDE_SEL_CAP_BLOCKS_NUM(l));
1632 off += 4;
1633 addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l);
1634
1635 // Selective IDE Stream Control Register
1636 l = get_conf_long(d, off);
1637
1638 printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n",
1639 offstr(offs, off),
1640 i,
1641 FLAG(l, PCI_IDE_SEL_CTL_EN),
1642 aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)],
1643 aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)],
1644 aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)],
1645 FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN),
1646 FLAG(l, PCI_IDE_SEL_CTL_CFG_EN),
1647 TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1),
1648 ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)),
1649 PCI_IDE_SEL_CTL_TC(l),
1650 PCI_IDE_SEL_CTL_ID(l),
1651 (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : ""
1652 );
1653 off += 4;
1654
1655 // Selective IDE Stream Status Register
1656 l = get_conf_long(d, off);
1657 printf("\t\t%sSelectiveIDE#%d Sta: %s RecvChkFail%c\n",
1658 offstr(offs, off),
1659 i ,
1660 TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1),
1661 FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK));
1662 off += 4;
1663
1664 // IDE RID Association Registers
1665 l = get_conf_long(d, off);
1666 l2 = get_conf_long(d, off + 4);
1667
1668 printf("\t\t%sSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x\n",
1669 offstr(offs, off),
1670 i,
1671 FLAG(l2, PCI_IDE_SEL_RID_2_VALID),
1672 PCI_IDE_SEL_RID_2_BASE(l2),
1673 PCI_IDE_SEL_RID_1_LIMIT(l),
1674 PCI_IDE_SEL_RID_2_SEG_BASE(l2));
1675 off += 8;
1676
1677 if (!config_fetch(d, off, addrnum * 12))
1678 {
1679 printf("\t\t<unreadable>\n");
1680 return;
1681 }
1682
1683 // IDE Address Association Registers
1684 for (j = 0; j < addrnum; ++j)
1685 {
1686 u64 limit, base;
1687
1688 l = get_conf_long(d, off);
1689 limit = get_conf_long(d, off + 4);
1690 limit <<= 32;
1691 limit |= (PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l) << 20) | 0xFFFFF;
1692 base = get_conf_long(d, off + 8);
1693 base <<= 32;
1694 base |= PCI_IDE_SEL_ADDR_1_BASE_LOW(l) << 20;
1695 printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n",
1696 offstr(offs, off),
1697 i,
1698 j,
1699 FLAG(l, PCI_IDE_SEL_ADDR_1_VALID),
1700 base,
1701 limit);
1702 off += 12;
1703 }
1704 }
1705 }
1706
1707 void
show_ext_caps(struct device * d,int type)1708 show_ext_caps(struct device *d, int type)
1709 {
1710 int where = 0x100;
1711 char been_there[0x1000];
1712 memset(been_there, 0, 0x1000);
1713 do
1714 {
1715 u32 header;
1716 int id, version;
1717
1718 if (!config_fetch(d, where, 4))
1719 break;
1720 header = get_conf_long(d, where);
1721 if (!header || header == 0xffffffff)
1722 break;
1723 id = header & 0xffff;
1724 version = (header >> 16) & 0xf;
1725 printf("\tCapabilities: [%03x", where);
1726 if (verbose > 1)
1727 printf(" v%d", version);
1728 printf("] ");
1729 if (been_there[where]++)
1730 {
1731 printf("<chain looped>\n");
1732 break;
1733 }
1734 switch (id)
1735 {
1736 case PCI_EXT_CAP_ID_NULL:
1737 printf("Null\n");
1738 break;
1739 case PCI_EXT_CAP_ID_AER:
1740 cap_aer(d, where, type);
1741 break;
1742 case PCI_EXT_CAP_ID_DPC:
1743 cap_dpc(d, where);
1744 break;
1745 case PCI_EXT_CAP_ID_VC:
1746 case PCI_EXT_CAP_ID_VC2:
1747 cap_vc(d, where);
1748 break;
1749 case PCI_EXT_CAP_ID_DSN:
1750 cap_dsn(d, where);
1751 break;
1752 case PCI_EXT_CAP_ID_PB:
1753 printf("Power Budgeting <?>\n");
1754 break;
1755 case PCI_EXT_CAP_ID_RCLINK:
1756 cap_rclink(d, where);
1757 break;
1758 case PCI_EXT_CAP_ID_RCILINK:
1759 printf("Root Complex Internal Link <?>\n");
1760 break;
1761 case PCI_EXT_CAP_ID_RCEC:
1762 cap_rcec(d, where);
1763 break;
1764 case PCI_EXT_CAP_ID_MFVC:
1765 printf("Multi-Function Virtual Channel <?>\n");
1766 break;
1767 case PCI_EXT_CAP_ID_RCRB:
1768 printf("Root Complex Register Block <?>\n");
1769 break;
1770 case PCI_EXT_CAP_ID_VNDR:
1771 cap_evendor(d, where);
1772 break;
1773 case PCI_EXT_CAP_ID_ACS:
1774 cap_acs(d, where);
1775 break;
1776 case PCI_EXT_CAP_ID_ARI:
1777 cap_ari(d, where);
1778 break;
1779 case PCI_EXT_CAP_ID_ATS:
1780 cap_ats(d, where);
1781 break;
1782 case PCI_EXT_CAP_ID_SRIOV:
1783 cap_sriov(d, where);
1784 break;
1785 case PCI_EXT_CAP_ID_MRIOV:
1786 printf("Multi-Root I/O Virtualization <?>\n");
1787 break;
1788 case PCI_EXT_CAP_ID_MCAST:
1789 cap_multicast(d, where, type);
1790 break;
1791 case PCI_EXT_CAP_ID_PRI:
1792 cap_pri(d, where);
1793 break;
1794 case PCI_EXT_CAP_ID_REBAR:
1795 cap_rebar(d, where, 0);
1796 break;
1797 case PCI_EXT_CAP_ID_DPA:
1798 printf("Dynamic Power Allocation <?>\n");
1799 break;
1800 case PCI_EXT_CAP_ID_TPH:
1801 cap_tph(d, where);
1802 break;
1803 case PCI_EXT_CAP_ID_LTR:
1804 cap_ltr(d, where);
1805 break;
1806 case PCI_EXT_CAP_ID_SECPCI:
1807 cap_sec(d, where);
1808 break;
1809 case PCI_EXT_CAP_ID_PMUX:
1810 printf("Protocol Multiplexing <?>\n");
1811 break;
1812 case PCI_EXT_CAP_ID_PASID:
1813 cap_pasid(d, where);
1814 break;
1815 case PCI_EXT_CAP_ID_LNR:
1816 printf("LN Requester <?>\n");
1817 break;
1818 case PCI_EXT_CAP_ID_L1PM:
1819 cap_l1pm(d, where);
1820 break;
1821 case PCI_EXT_CAP_ID_PTM:
1822 cap_ptm(d, where);
1823 break;
1824 case PCI_EXT_CAP_ID_M_PCIE:
1825 printf("PCI Express over M_PHY <?>\n");
1826 break;
1827 case PCI_EXT_CAP_ID_FRS:
1828 printf("FRS Queueing <?>\n");
1829 break;
1830 case PCI_EXT_CAP_ID_RTR:
1831 printf("Readiness Time Reporting <?>\n");
1832 break;
1833 case PCI_EXT_CAP_ID_DVSEC:
1834 cap_dvsec(d, where);
1835 break;
1836 case PCI_EXT_CAP_ID_VF_REBAR:
1837 cap_rebar(d, where, 1);
1838 break;
1839 case PCI_EXT_CAP_ID_DLNK:
1840 printf("Data Link Feature <?>\n");
1841 break;
1842 case PCI_EXT_CAP_ID_16GT:
1843 printf("Physical Layer 16.0 GT/s <?>\n");
1844 break;
1845 case PCI_EXT_CAP_ID_LMR:
1846 cap_lmr(d, where);
1847 break;
1848 case PCI_EXT_CAP_ID_HIER_ID:
1849 printf("Hierarchy ID <?>\n");
1850 break;
1851 case PCI_EXT_CAP_ID_NPEM:
1852 printf("Native PCIe Enclosure Management <?>\n");
1853 break;
1854 case PCI_EXT_CAP_ID_32GT:
1855 printf("Physical Layer 32.0 GT/s <?>\n");
1856 break;
1857 case PCI_EXT_CAP_ID_DOE:
1858 cap_doe(d, where);
1859 break;
1860 case PCI_EXT_CAP_ID_IDE:
1861 cap_ide(d, where);
1862 break;
1863 default:
1864 printf("Extended Capability ID %#02x\n", id);
1865 break;
1866 }
1867 where = (header >> 20) & ~3;
1868 } while (where);
1869 }
1870