1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <[email protected]>
3 * Copyright (C) 2019-2020 Collabora, Ltd.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include <math.h>
26
27 #include "util/bitscan.h"
28 #include "util/half_float.h"
29 #include "compiler.h"
30 #include "helpers.h"
31 #include "midgard_ops.h"
32
33 /* Pretty printer for Midgard IR, for use debugging compiler-internal
34 * passes like register allocation. The output superficially resembles
35 * Midgard assembly, with the exception that unit information and such is
36 * (normally) omitted, and generic indices are usually used instead of
37 * registers */
38
39 static void
mir_print_index(int source)40 mir_print_index(int source)
41 {
42 if (source == ~0) {
43 printf("_");
44 return;
45 }
46
47 if (source >= SSA_FIXED_MINIMUM) {
48 /* Specific register */
49 int reg = SSA_REG_FROM_FIXED(source);
50
51 /* TODO: Moving threshold */
52 if (reg > 16 && reg < 24)
53 printf("U%d", 23 - reg);
54 else
55 printf("R%d", reg);
56 } else if (source & PAN_IS_REG) {
57 printf("r%d", source >> 1);
58 } else {
59 printf("%d", source >> 1);
60 }
61 }
62
63 static const char components[16] = "xyzwefghijklmnop";
64
65 static void
mir_print_mask(unsigned mask)66 mir_print_mask(unsigned mask)
67 {
68 printf(".");
69
70 for (unsigned i = 0; i < 16; ++i) {
71 if (mask & (1 << i))
72 putchar(components[i]);
73 }
74 }
75
76 /*
77 * Print a swizzle. We only print the components enabled by the corresponding
78 * writemask, as the other components will be ignored by the hardware and so
79 * don't matter.
80 */
81 static void
mir_print_swizzle(unsigned mask,unsigned * swizzle)82 mir_print_swizzle(unsigned mask, unsigned *swizzle)
83 {
84 printf(".");
85
86 for (unsigned i = 0; i < 16; ++i) {
87 if (mask & BITFIELD_BIT(i)) {
88 unsigned C = swizzle[i];
89 putchar(components[C]);
90 }
91 }
92 }
93
94 static const char *
mir_get_unit(unsigned unit)95 mir_get_unit(unsigned unit)
96 {
97 switch (unit) {
98 case ALU_ENAB_VEC_MUL:
99 return "vmul";
100 case ALU_ENAB_SCAL_ADD:
101 return "sadd";
102 case ALU_ENAB_VEC_ADD:
103 return "vadd";
104 case ALU_ENAB_SCAL_MUL:
105 return "smul";
106 case ALU_ENAB_VEC_LUT:
107 return "lut";
108 case ALU_ENAB_BR_COMPACT:
109 return "br";
110 case ALU_ENAB_BRANCH:
111 return "brx";
112 default:
113 return "???";
114 }
115 }
116
117 static void
mir_print_embedded_constant(midgard_instruction * ins,unsigned src_idx)118 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
119 {
120 assert(src_idx <= 1);
121
122 unsigned base_size = max_bitsize_for_alu(ins);
123 unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]);
124 bool half = (sz == (base_size >> 1));
125 unsigned mod = mir_pack_mod(ins, src_idx, false);
126 unsigned *swizzle = ins->swizzle[src_idx];
127 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
128 unsigned comp_mask = effective_writemask(ins->op, ins->mask);
129 unsigned num_comp = util_bitcount(comp_mask);
130 unsigned max_comp = mir_components_for_type(ins->dest_type);
131 bool first = true;
132
133 printf("#");
134
135 if (num_comp > 1)
136 printf("vec%d(", num_comp);
137
138 for (unsigned comp = 0; comp < max_comp; comp++) {
139 if (!(comp_mask & (1 << comp)))
140 continue;
141
142 if (first)
143 first = false;
144 else
145 printf(", ");
146
147 mir_print_constant_component(stdout, &ins->constants, swizzle[comp],
148 reg_mode, half, mod, ins->op);
149 }
150
151 if (num_comp > 1)
152 printf(")");
153 }
154
155 static void
mir_print_src(midgard_instruction * ins,unsigned c)156 mir_print_src(midgard_instruction *ins, unsigned c)
157 {
158 mir_print_index(ins->src[c]);
159
160 if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) {
161 pan_print_alu_type(ins->src_types[c], stdout);
162 mir_print_swizzle(ins->mask, ins->swizzle[c]);
163 }
164 }
165
166 void
mir_print_instruction(midgard_instruction * ins)167 mir_print_instruction(midgard_instruction *ins)
168 {
169 printf("\t");
170
171 if (midgard_is_branch_unit(ins->unit)) {
172 const char *branch_target_names[] = {"goto", "break", "continue",
173 "discard"};
174
175 printf("%s.", mir_get_unit(ins->unit));
176 if (ins->branch.target_type == TARGET_DISCARD)
177 printf("discard.");
178 else if (ins->writeout)
179 printf("write.");
180 else if (ins->unit == ALU_ENAB_BR_COMPACT && !ins->branch.conditional)
181 printf("uncond.");
182 else
183 printf("cond.");
184
185 if (!ins->branch.conditional)
186 printf("always");
187 else if (ins->branch.invert_conditional)
188 printf("false");
189 else
190 printf("true");
191
192 if (ins->writeout) {
193 printf(" (c: ");
194 mir_print_src(ins, 0);
195 printf(", z: ");
196 mir_print_src(ins, 2);
197 printf(", s: ");
198 mir_print_src(ins, 3);
199 printf(")");
200 }
201
202 if (ins->branch.target_type != TARGET_DISCARD)
203 printf(" %s -> block(%d)\n",
204 ins->branch.target_type < 4
205 ? branch_target_names[ins->branch.target_type]
206 : "??",
207 ins->branch.target_block);
208
209 return;
210 }
211
212 switch (ins->type) {
213 case TAG_ALU_4: {
214 midgard_alu_op op = ins->op;
215 const char *name = alu_opcode_props[op].name;
216
217 if (ins->unit)
218 printf("%s.", mir_get_unit(ins->unit));
219
220 printf("%s", name ? name : "??");
221
222 if (!(midgard_is_integer_out_op(ins->op) &&
223 ins->outmod == midgard_outmod_keeplo)) {
224 mir_print_outmod(stdout, ins->outmod,
225 midgard_is_integer_out_op(ins->op));
226 }
227
228 break;
229 }
230
231 case TAG_LOAD_STORE_4: {
232 midgard_load_store_op op = ins->op;
233 const char *name = load_store_opcode_props[op].name;
234
235 assert(name);
236 printf("%s", name);
237 break;
238 }
239
240 case TAG_TEXTURE_4: {
241 printf("TEX");
242
243 if (ins->helper_terminate)
244 printf(".terminate");
245
246 if (ins->helper_execute)
247 printf(".execute");
248
249 break;
250 }
251
252 default:
253 assert(0);
254 }
255
256 if (ins->compact_branch && ins->branch.invert_conditional)
257 printf(".not");
258
259 printf(" ");
260 mir_print_index(ins->dest);
261
262 if (ins->dest != ~0) {
263 pan_print_alu_type(ins->dest_type, stdout);
264 mir_print_mask(ins->mask);
265 }
266
267 printf(", ");
268
269 /* Only ALU can have an embedded constant, r26 as read on load/store is
270 * something else entirely */
271 bool is_alu = ins->type == TAG_ALU_4;
272 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
273
274 if (is_alu && alu_opcode_props[ins->op].props & QUIRK_FLIPPED_R24) {
275 /* Moves (indicated by QUIRK_FLIPPED_R24) are 1-src, with their
276 * one source in the second slot
277 */
278 assert(ins->src[0] == ~0);
279 } else {
280 if (ins->src[0] == r_constant && is_alu)
281 mir_print_embedded_constant(ins, 0);
282 else
283 mir_print_src(ins, 0);
284
285 printf(", ");
286 }
287
288 if (ins->has_inline_constant)
289 printf("#%d", ins->inline_constant);
290 else if (ins->src[1] == r_constant && is_alu)
291 mir_print_embedded_constant(ins, 1);
292 else
293 mir_print_src(ins, 1);
294
295 if (is_alu) {
296 /* ALU ops are all 2-src, though CSEL is treated like a 3-src
297 * pseudo op with the third source scheduler lowered
298 */
299 switch (ins->op) {
300 case midgard_alu_op_icsel:
301 case midgard_alu_op_fcsel:
302 case midgard_alu_op_icsel_v:
303 case midgard_alu_op_fcsel_v:
304 printf(", ");
305 mir_print_src(ins, 2);
306 break;
307 default:
308 assert(ins->src[2] == ~0);
309 break;
310 }
311
312 assert(ins->src[3] == ~0);
313 } else {
314 for (unsigned c = 2; c <= 3; ++c) {
315 printf(", ");
316 mir_print_src(ins, c);
317 }
318 }
319
320 if (ins->no_spill)
321 printf(" /* no spill */");
322
323 printf("\n");
324 }
325
326 /* Dumps MIR for a block or entire shader respective */
327
328 void
mir_print_block(midgard_block * block)329 mir_print_block(midgard_block *block)
330 {
331 printf("block%u: {\n", block->base.name);
332
333 if (block->scheduled) {
334 mir_foreach_bundle_in_block(block, bundle) {
335 for (unsigned i = 0; i < bundle->instruction_count; ++i)
336 mir_print_instruction(bundle->instructions[i]);
337
338 printf("\n");
339 }
340 } else {
341 mir_foreach_instr_in_block(block, ins) {
342 mir_print_instruction(ins);
343 }
344 }
345
346 printf("}");
347
348 if (block->base.successors[0]) {
349 printf(" -> ");
350 pan_foreach_successor((&block->base), succ)
351 printf(" block%u ", succ->name);
352 }
353
354 printf(" from { ");
355 mir_foreach_predecessor(block, pred)
356 printf("block%u ", pred->base.name);
357 printf("}");
358
359 printf("\n\n");
360 }
361
362 void
mir_print_shader(compiler_context * ctx)363 mir_print_shader(compiler_context *ctx)
364 {
365 mir_foreach_block(ctx, block) {
366 mir_print_block((midgard_block *)block);
367 }
368 }
369